CN100461379C - Pixel structure of liquid crystal display and manufacturing method thereof - Google Patents

Abstract

The invention discloses a manufacturing method of a pixel structure, which can finish the pixel structure of a liquid crystal display by only using five photomasks. In the pixel structure, a metal light shielding layer is formed at the bottom of the thin film transistor to reduce the generation of photocurrent, and the storage capacitance of the storage capacitor is increased by using the metal wire.

Description

Pixel structure of liquid crystal display and manufacturing method thereof

technical field

The invention relates to a liquid crystal display and a manufacturing method thereof, and in particular to a pixel structure of a liquid crystal display and a manufacturing method thereof.

Background technique

Recently, the continuous innovation of optoelectronic technology, coupled with the arrival of the digital age, has promoted the vigorous development of the liquid crystal display market. Liquid crystal displays have many advantages such as high image quality, small size, light weight, low driving voltage and low power consumption. Therefore, it is widely used in consumer communication or electronic products such as personal digital assistants (PDAs), mobile phones, video recorders, notebook computers, desktop monitors, car monitors, and projection TVs, and gradually replaces cathodes. Ray tubes became the mainstream of displays.

Today's thin-film transistor array (TFT Array) substrate manufacturing methods for liquid crystal displays are mainly composed of three different processes: deposition, photolithography and etching. Among the three processes, the photolithography process accounts for the highest production cost. Therefore, how to reduce the number of photolithography processes required in the entire manufacturing process of TFT array substrates, that is, reduce the number of photomasks required, has become the primary issue for major panel manufacturers in various countries to reduce the production cost of liquid crystal displays.

Contents of the invention

Therefore, the object of the present invention is to provide a pixel structure suitable for a liquid crystal display and a manufacturing method thereof.

The first metal layer, the first dielectric layer and the silicon layer are sequentially formed on the substrate, and then the first metal layer, the first dielectric layer and the silicon layer are patterned to define the first metal layer, the first dielectric layer The transistor stack formed by the electrical layer and the silicon layer defines the data line and the first electrode formed by the first metal layer respectively. Next, a gate dielectric layer and a second metal layer are sequentially formed on the substrate, the transistor stack, the data line, and the first electrode, and then the second metal layer is patterned to define respectively on the transistor stack and the first electrode. Grid and second electrode. Using the gate as a doping mask, the silicon layer of the transistor stack is heavily doped to form a first heavily doped region and a second heavily doped region on both sides of the silicon layer.

A second dielectric layer is formed on the gate dielectric layer, the gate electrode and the second electrode, and then the second dielectric layer is patterned to form the first opening, the second opening, the third opening and the fourth opening to respectively expose the The data line, the first heavily doped region, the second heavily doped region and the first electrode are output. Subsequently, a third metal layer is formed to cover the second dielectric layer, and then the third metal layer is patterned to define the first wire and the second wire. Wherein, the first wire electrically connects the data line and the first heavily doped region through the first opening and the second opening, and the second wire electrically connects the second heavily doped region and the first heavily doped region through the third opening and the fourth opening. electrode, and the second wire extends above the second electrode to form a storage capacitor with the first electrode and the second electrode.

Then, a transparent conductive layer is formed on the second dielectric layer, the first wire and the second wire, and then the transparent conductive layer is patterned to define a pixel electrode on the second wire and the second dielectric layer.

Description of drawings

In order to make the above and other objects, features, advantages and embodiments of the present invention more comprehensible, the detailed description of the accompanying drawings is as follows:

1A-1F are cross-sectional schematic diagrams illustrating a manufacturing process of a pixel array structure of a liquid crystal display according to an embodiment of the present invention.

FIG. 2 is a schematic diagram of a cross-sectional structure of a general liquid crystal display.

Explanation of reference signs

100: substrate 105: first metal layer

105a: metal light-shielding layer 105b: data line

105c: first electrode 110: first dielectric layer

115: Silicon layer 120: Gate dielectric layer

130a: grid 130b: second electrode

135: Source 140: Drain

142: Lightly doped region 145: Second dielectric layer

150a: first opening 150b: second opening

150c: the third opening 150d: the fourth opening

155a: first wire 155b: second wire

160: pixel electrode 165: protective layer

190: Data line area 192: Active component area

194: storage capacitor area 196: pixel area

205: First substrate 210: Second substrate

215: Liquid crystal layer 220: Liquid crystal display

Detailed ways

Please refer to FIGS. 1A-1F , which are schematic cross-sectional views illustrating a manufacturing process of a pixel array structure of a liquid crystal display according to an embodiment of the present invention.

In FIG. 1A, a first metal layer 105, a first dielectric layer 110, and a silicon layer 115 are sequentially deposited on a substrate 100, wherein the material of the silicon layer is, for example, polysilicon or amorphous silicon, and the material of the first dielectric layer An example is silicon oxide. The substrate 100 can be divided into a data line area 190 , an active device area 192 and a storage capacitor area 194 .

In FIG. 1B , the first metal layer 105 , the first dielectric layer 110 and the silicon layer 115 are patterned. Only the first metal layer is left in the data line area 190 and the storage capacitor area 194 to serve as the data line 105b and the first electrode 105c respectively. In the active device region 192 , a transistor stack composed of the metal light-shielding layer 105 a , the first dielectric layer 110 a and the silicon layer 115 a is defined. The above patterning method, for example, can use photolithography etching; and the photomask used in photolithography, for example, can be a half-tone photomask.

In FIG. 1C, a gate dielectric layer 120 and a second metal layer are sequentially formed on the substrate 100, the data line 105b, the first electrode 105c and the silicon layer 115a, wherein the material of the gate dielectric layer includes silicon oxide, nitrogen silicon oxide or silicon oxynitride. The second metal layer is then patterned to form a gate 130a over the silicon layer 115a and a second electrode 130b over the first electrode 105c. Next, a doping process is performed on the silicon layer 115a to form a first heavily doped region and a second heavily doped region on both sides of the silicon layer 115a to serve as the source 135 and the drain 140 respectively. The metal light-shielding layer 105a is located under the TFT formed by the gate 130a, the source 135 and the drain 140, so it can help to block light and reduce the photocurrent of the TFT.

Here, the gate 130 a can also be further isotropically etched, and then the silicon layer 115 a is lightly doped to form a lightly doped region 142 inside the source 135 and the drain 140 .

In FIG. 1D , a second dielectric layer 145 is formed on the gate dielectric layer 120 , the gate electrode 130 a and the second electrode 130 b, wherein the material of the second dielectric layer 145 is, for example, silicon oxide. Then, pattern the second dielectric layer 145 to form first, second, third and fourth openings 150a, 150b, 150c, 150d in the second dielectric layer 145 to respectively expose the data line 105b, the source 135 (the first heavily doped region), the drain 140 (the second heavily doped region) and the first electrode 105c. In FIG. 1E , a third metal layer is firstly formed on the second dielectric layer 145 and in the first, second, third and fourth openings 150 a , 150 b , 150 c , 150 d. Next, the third metal layer is patterned to form a first wire 155a electrically connecting the source 135 and the data line 105b and a second wire 155b electrically connecting the drain 140 and the first electrode 105c. The above-mentioned first electrode 105c, second electrode 130b and second wire 155b overlapping with the second electrode 130b constitute a storage capacitor. The second wire 155b overlapping the second electrode 130b is electrically connected to the first electrode 105c, thereby greatly increasing the storage capacity of the storage capacitor.

In FIG. 1F, a transparent conductive layer is first formed on the second dielectric layer 145, the first conductive line 155a and the second conductive line 155b, wherein the material of the transparent conductive layer is, for example, indium tin oxide, indium zinc oxide or aluminum zinc oxide. . Then pattern the transparent conductive layer, form the pixel electrode 160 on the pixel area 196 overlapping with the storage capacitor area 194, and form the protective layer 165 on the first wire 155a to prevent the first wire 155a from being oxidized.

The above-mentioned pixel array structure can be applied to any applicable flat panel display, such as a liquid crystal display. Please refer to FIG. 2 , which shows a schematic cross-sectional structure diagram of a general liquid crystal display. In FIG. 2 , a liquid crystal display 220 has a first substrate 205 , a second substrate 210 and a liquid crystal layer 215 sandwiched therebetween. If the pixel array structure is disposed on the first substrate 205, the array structure of color filters can be disposed on the second substrate 210, so that the second substrate 210 can be used as a color filter plate. Since various changes in the structure of the liquid crystal display are well known to those skilled in the art, details will not be repeated one by one, and the detailed structure is not shown in FIG. 2 .

It can be seen from the above preferred embodiments of the present invention that the process of the entire pixel array structure can be completed by using five photomasks. Moreover, it can be known from the pixel structure shown in FIG. 1F that the storage capacitor is composed of the first electrode 105c, the second electrode 130b and the second wire 155b. In addition, the metal light-shielding layer 105a located under the TFT formed by the gate 130a, the source 135 and the drain 140 can help to block light to reduce the photocurrent of the TFT.

Although the present invention has been disclosed above with a preferred embodiment, it is not intended to limit the present invention. Any person skilled in the art may make various modifications and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be defined by the claims.

Claims (19)

1. A manufacturing method of a pixel structure, suitable for liquid crystal displays, the manufacturing method comprising: sequentially forming a first metal layer, a first dielectric layer and a silicon layer on the substrate; patterning the first metal layer, the first dielectric layer and the silicon layer to define transistor stacks formed by the first metal layer, the first dielectric layer and the silicon layer, and respectively defining The data line and the first electrode formed by the first metal layer; sequentially forming a gate dielectric layer and a second metal layer on the substrate, the transistor stack, the data line and the first electrode; patterning the second metal layer to define a gate and a second electrode over the transistor stack and the first electrode, respectively; Using the gate as a doping mask, performing a heavy doping process on the silicon layer of the transistor stack to form a first heavily doped region and a second heavily doped region on both sides of the silicon layer; forming a second dielectric layer on the gate dielectric layer, the gate and the second electrode; patterning the second dielectric layer to form a first opening, a second opening, a third opening and a fourth opening to respectively expose the data line, the first heavily doped region, the second heavily doped region and the first electrode; forming a third metal layer covering the second dielectric layer; patterning the third metal layer to define a first wire and a second wire, wherein the first wire is electrically connected to the data line and the first heavily doped region through the first opening and the second opening, and the A second wire electrically connects the second heavily doped region and the first electrode through the third opening and the fourth opening, and the second wire extends above the second electrode to communicate with the first electrode and the first electrode. the second electrode constitutes a storage capacitor; forming a transparent conductive layer on the second dielectric layer, the first wire and the second wire; and The transparent conductive layer is patterned to define a pixel electrode on the second wire and the second dielectric layer. 2. The manufacturing method of the pixel structure as claimed in claim 1, wherein the material of the silicon layer comprises polysilicon or amorphous silicon. 3. The manufacturing method of the pixel structure as claimed in claim 1, wherein the material of the first dielectric layer and the second dielectric layer comprises silicon oxide. 4. The manufacturing method of the pixel structure as claimed in claim 1, wherein the material of the gate dielectric layer comprises silicon oxide, silicon nitride or silicon oxynitride. 5. The manufacturing method of the pixel structure as claimed in claim 1, wherein the material of the transparent conductive layer comprises indium tin oxide, indium zinc oxide or aluminum zinc oxide. 6. The method for manufacturing a pixel structure as claimed in claim 1, further comprising: between performing the heavy doping process and forming the second dielectric layer: isotropically etching the gate to reduce the size of the gate; and Using the etched gate as a doping mask, lightly doping the silicon layer of the transistor stack to form lightly doped layers inside the first heavily doped region and the second heavily doped region respectively district. 7. The manufacturing method of the pixel structure as claimed in claim 1, wherein the step of patterning the second metal layer further comprises forming a scan line to electrically connect the gate. 8. A pixel structure suitable for liquid crystal displays, the pixel structure at least comprising: The transistor stack is located on the active element area of the substrate. The transistor stack is sequentially composed of a metal light-shielding layer, a first dielectric layer and a silicon layer from bottom to top. Both ends of the silicon layer have a first heavily doped region and a silicon layer. the second heavily doped region; The data line is located in the data line area of the substrate; a first electrode located in the storage capacitor region of the substrate; a gate dielectric layer located on the substrate, the transistor stack, the data line and the first electrode; a gate on the gate dielectric layer above the transistor stack; a second electrode located on the gate dielectric layer above the first electrode; The second dielectric layer is located on the gate dielectric layer, the gate and the second electrode, and the second dielectric layer has a first opening, a second opening, a third opening and a fourth opening to respectively expose the data line, the first heavily doped region, the second heavily doped region and the first electrode; a first wire, located on the second dielectric layer and electrically connecting the data line and the first heavily doped region through the first opening and the second opening; a second wire, located on the second dielectric layer, electrically connecting the second heavily doped region and the first electrode through the third opening and the fourth opening and extending to the second electrode, wherein the first electrode, the second electrode and the second wire form a storage capacitor; and The pixel electrode is located on the second wire and the pixel area on the second dielectric layer. 9. The pixel structure as claimed in claim 8, wherein the gate is located on the gate dielectric layer above the center of the transistor stack. 10. The pixel structure as claimed in claim 8, wherein the metal light-shielding layer, the data line and the first electrode are formed by a first metal layer, the gate and the second electrode are formed by a second metal layer, And the first wire and the second wire are formed by the third metal layer. 11. The pixel structure as claimed in claim 10, further comprising a scan line electrically connected to the gate. 12. The pixel structure as claimed in claim 11, wherein the scan line is formed by the second metal layer. 13. The pixel structure as claimed in claim 8, wherein the material of the silicon layer comprises polysilicon or amorphous silicon. 14. The pixel structure as claimed in claim 8, wherein the material of the first dielectric layer and the second dielectric layer comprises silicon oxide. 15. The pixel structure as claimed in claim 8, wherein the material of the gate dielectric layer comprises silicon oxide, silicon nitride or silicon oxynitride. 16. The pixel structure as claimed in claim 8, wherein the material of the pixel electrode comprises indium tin oxide, indium zinc oxide or aluminum zinc oxide. 17. The pixel structure according to claim 8, wherein the first heavily doped region and the second heavily doped region on both sides of the silicon layer serve as a source and a drain respectively, and the gate, the source and the The drain constitutes a thin film transistor. 18. The pixel structure as claimed in claim 8, further comprising a protective layer on the first conductive line. 19. The pixel structure as claimed in claim 18, wherein a material of the protective layer comprises indium tin oxide, indium zinc oxide or aluminum zinc oxide.

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