CN100446124C - Method for detecting data strobe signal - Google Patents

Abstract

A method for detecting Data strobe signal is used in Data receiving unit to predict the arrival time of Data output from Double Data Rate synchronous dynamic Random Access Memory (DDR SDRAM). The method comprises the following steps: first, a latency is estimated, comprising the steps of: when a read command signal is sent out, enabling a first signal and determining the state of a second signal according to the level voltage of the data strobe signal and a reference voltage; when the first signal is converted from the disabled state to the enabled state, a counting value is calculated according to a reference clock pulse; and stopping calculating the count value according to the reference clock when the second signal is converted from the enabled state to the disabled state; the obtained counting value is the latency time; then, when another reading instruction signal is sent out, counting is carried out according to the latency time and the reference clock pulse; when the count value equals the latency, a signal is asserted to indicate the leading of the data strobe signal.

Description

Method for detecting data strobe signal

technical field

The present invention relates to a method for detecting an output data strobe (strobe) signal of a double data rate synchronous dynamic random access memory (Double Data Rate Synchronous DRAM, DDR SDRAM), in particular to a method for DDR When SDRAM outputs data, it detects the method of data strobe signal.

Background technique

In current general data processing systems (data process systems), synchronous dynamic access memory (Synchronous DRAM, SDRAM) architecture is often used in memory units. It operates synchronously with the system, and each data access operation is triggered by the rising edge of the system clock, so it can provide faster data transmission efficiency than traditional clock-independent memory architectures.

The new generation of SDRAM architecture called Double Data Rate (DDR) SDRAM is similar to the general SDRAM architecture. But the difference is that both the positive edge and the falling edge of the system clock will trigger a data access action, so theoretically DDR SDRAM can provide twice the data transfer efficiency of the general SDRAM architecture, and in the architecture Only minor modifications are required. However, as the system clock continues to increase, some new problems also arise.

Please refer to Figure 1, which is a timing diagram for reading data from DDR SDRAM in a traditional method. Among them, the signal CLK is the system clock, when a clock low logic level (lowlogic level) enabling signal RC is sent to the DDR SDRAM as a read command (read command), and after a period of latency (latency) time 102 , the data will appear on the data line DQ at a rate of two data per clock for reading. Here, it is assumed that eight data data can be read in one data reading operation, that is, data D0 to data D7. While providing data to the data line DQ, DDR SDRAM will also provide a data strobe (strobe) signal DQS that operates synchronously with the data on the data line DQ, and each positive and negative edge indicates the data line DQ The arrival of the last piece of data, and before the first data D0 on the data line DQ, a low logic level preamble (preamble) 104 of one clock cycle is provided to indicate that the data is about to arrive, and at the end, half an hour The low logic level of the pulse cycle is postambled (post amble) 106 to indicate the end of the data on the data line DQ. In these cases, the signal DQS is in a range between the high logic level (high logic level) and the low logic level. A high impedance (HI-Z) state between states, so the data strobe signal DQS is a tri-state signal.

After the DDR SDRAM returns the data and the data strobe signal DQS, the next step is to receive the data on the data line DQ. Generally speaking, the receiving unit can turn on the input enable signal TNI to receive the data line DQ and the data strobe signal DQS after a period of time after the read command signal RC is sent. When the input enable signal TNI detects the lead 104 of the data strobe signal DQS, it maintains the enable state of the high logic level until the follow 106 . During the enabling period of the input enabling signal TNI, the data receiving unit can provide a data reading signal ZI synchronous with the data strobe signal DQS for controlling data reception, and the data receiving unit will be in the normal state of the data reading signal ZI Edge and negative edge both read the data on the data line DQ.

However, due to various factors such as the improvement of the system clock frequency and the differences in the memory modules used in each product and the wiring of the motherboard, the latency 102 is not a constant value among different products, and it will vary with the product and product usage. The situation varies depending on the situation, and the appearance time of the preamble 104 of the data strobe signal DQS will also change accordingly. Traditionally, the input enable signal TNI detects the leading edge of the data strobe signal DQS after a fixed period of time after the read command signal RC is issued. At this time, if the input enable signal TNI detects the high impedance portion of the data strobe signal DQS due to the prolongation of the latency time 102 , an unknown state will be generated in the data read signal ZI. Also, if the input enable signal TNI is detected after missing the leading edge of the data strobe signal DQS due to the shortening of the latency time 102 , data loss will result. All of these situations will generate data reading errors, seriously reducing the efficiency of data reading.

This shows that above-mentioned existing method obviously still has inconvenience and defect, and demands urgently further improving. In order to solve the problems existing in the existing methods, relevant manufacturers have tried their best to find a solution, but no suitable design has been developed for a long time.

In view of the defects in the above-mentioned existing methods, it can be seen from the above that the method of detecting the arrival of data by the data receiving unit can be improved, and the front end of the data strobe signal can be captured more accurately to reduce the loss of data. Improve the reading efficiency of data reading unit to DDR SDRAM data.

Contents of the invention

The object of the present invention is to overcome the defects of the existing method for detecting data strobe signal, and provide a new method for detecting the arrival signal of output data in DDR SDRAM architecture.

Another object of the present invention is to provide a data detection method for the DDR SDRAM architecture, so as to improve the data reading efficiency.

Another object of the present invention is to provide a data detection method used in a data receiving unit. When using this data receiving unit to receive data in a DDR SDRAM module under various conditions, it can maintain a certain data reading efficiency.

The purpose of the present invention and the solution to its technical problems are achieved by adopting the following technical solutions. According to a method for detecting the preamble of a data strobe signal proposed by the present invention, the method includes the following steps: first estimating a latency time, including the following steps: when a read command signal is sent, enabling a first signal and according to the comparison The level voltage of the data strobe signal and a reference voltage determine the state of a second signal; when the first signal is turned from inactive to enabled, a count value is calculated according to a reference clock; When the second signal changes from an enabled state to a non-enabled state, stop calculating the count value based on the reference clock; the obtained count value is the latency time; then, when another read command signal is issued, according to The latency time and the reference clock are counted; when the count value is equal to the latency time, a signal is sent to mark the lead of the data strobe signal.

The purpose of the present invention and its technical problems can also be further realized by adopting the following technical measures.

In the aforementioned method for detecting a data strobe signal, wherein the reference voltage range is between a high impedance state voltage of the data strobe signal and a low logic level voltage of the data strobe signal.

The aforementioned method for detecting a data strobe signal, wherein if the level voltage of the data strobe signal is greater than the reference voltage, the second signal is disabled, and if the level voltage of the data strobe signal is lower than the reference voltage , the second signal is enabled.

In the aforementioned method for detecting data strobe signals, the initial state of the first signal is a disabled state, and the initial state of the second signal is a disabled state.

In the aforementioned method for detecting a data strobe signal, the disabled level of the first signal is a low logic level, and the enabled level is a high logic level.

In the aforementioned method for detecting a data strobe signal, the disabled level of the second signal is a high logic level, and the enabled level is a low logic level.

The aforementioned method for detecting a data strobe signal, wherein the method is used for reading data of a double data transfer rate synchronous dynamic random memory.

Compared with the prior art, the present invention has obvious advantages and beneficial effects. As can be seen from the above technical solutions, in order to achieve the aforementioned object of the invention, it is necessary to send a data read command to the memory unit formed by the DDR SDRAM structure at the beginning, so that the memory unit sends data. At the same time when the data read command is sent, the startup counter starts counting sequentially, and stops counting when the first data sent by the memory unit is received, and the count value at this time is stored. In subsequent data reading operations on the same memory unit, the stored value can be used to effectively detect the arrival time of data.

It can be seen from the above that the present invention relates to a method for detecting a data strobe signal, which is used in a data receiving unit to predict a double data rate synchronous dynamic random access memory (Double Data Rate Synchronous Dynamic Random Access Memory, The arrival time of data output by DDR SDRAM). At the beginning of the operation, a data reading program is performed on the DDR SDRAM, and the latency time spent in this reading operation is recorded, so as to facilitate the subsequent data reading operation, and the previous data strobe signal can be detected. The arrival time of the preamble part is predicted.

To sum up, the special method for detecting the data strobe signal of the present invention can be carried out at regular intervals or at any time during the initial operation and operation of the system to update the value of the data reading latency and keep the best data continuously. Reading efficiency; at the same time, a kind of data detection method used in the data receiving unit provided by the present invention can maintain a certain data reading efficiency. It has the above-mentioned many advantages and practical value, and there is no similar design published or used in similar methods, so it is indeed an innovation. It has great improvements in both methods and functions, and has a relatively large technical advantage. It has made great progress, and has produced easy-to-use and practical effects, and has improved multiple functions compared with the existing method of detecting data strobe signals, so it is more suitable for practical use, and has wide application value in the industry. Sincerely A novel, progressive and practical new design.

The above description is only an overview of the technical solutions of the present invention. In order to understand the technical means of the present invention more clearly and implement them according to the contents of the description, the preferred embodiments of the present invention and accompanying drawings are described in detail below.

Description of drawings

Figure 1 is a timing diagram of reading data from DDR SDRAM by traditional methods.

FIG. 2 is a sequence diagram of a method for acquiring data read latency according to the present invention.

Fig. 3 is a flowchart of a method for calculating latency in the method of the present invention.

Fig. 4 is a flow chart of the method of the present invention.

102: Latency time 104: Front

106: Rear position 202: Latency time

204: Signal negative edge 206: Signal positive edge

208: Signal positive edge 210: Signal negative edge

212: Positive signal edge

310: TINDQS signal and ZIX signal are in the initial state of disabling

320: When the read command signal is issued, enable the TINDQS signal and start counting

330: Determine the state of the ZIX signal according to the reference clock and the data strobe signal DQS

340: Stop counting when the ZIX signal changes from the enabled state to the disabled state

350: Store the count as the latency

410: Estimating Latency

420: When the read command signal is issued, start counting according to the latency

430: When the counting time is equal to the latency time, send a signal to mark the leading edge of the data strobe signal

CLK: system clock RC: read command signal

DQ: data line DQS: data strobe signal

TNI: input enabling signal ZI: data reading signal

D0-D7: data TNDQS: signal

ZIX: signal COUNT: count register

PHASE: count register

Detailed ways

In order to further explain the technical means and effects that the present invention adopts to achieve the intended invention purpose, below in conjunction with the accompanying drawings and preferred embodiments, the specific implementation methods, methods, Steps, features and effects thereof are described in detail below.

As can be seen from the above, in different information products, when a data receiving unit such as a central processing unit (Central Process Unit, CPU) reads data from a memory unit of a DDR SRAM architecture, the memory unit returns data and The time point of the data strobe signal may be different, which causes difficulties in designing the time point of detecting and receiving data for the data receiving unit. Therefore, in the embodiment of the present invention, the detection time point is not designed to be a certain value, but when the system starts to operate, the latency time of data reading is first counted and recorded, and then the count value can be used Infer the arrival time of the data and the data strobe signal, and then detect the data strobe signal. After the data strobe signal is detected accurately, the memory unit can be efficiently processed. Data read.

Please refer to FIG. 2 , which is a sequence diagram of the method for acquiring data and reading latency of the present invention. As shown in FIG. 2 , it describes an embodiment of the method, wherein the functions and actions of the system clock CLK, the read command signal RC, the data line DQ, and the data strobe signal DQS are the same as those described above. The purpose of this method is to count the latency 202 of data reading.

In this embodiment, a signal TNDQS is firstly defined, which can be a high logic level enable signal or a low logic level enable signal, and in this example is a high logic level enable signal. When the data access unit generates the read command signal RC, the driving signal TNDQS generates an enable positive edge 208 and is driven by the first positive edge 206 of the data strobe signal DQS to generate a disable negative edge 210 . That is to say, the enable period of the signal TNDQS is similar to the latency 202, but because there is some delay between the negative edge 210 of its disable and the first positive edge 206 of the data strobe signal DQS, it is necessary to define another signal Zix.

The signal ZIX can also be a high logic level enable signal or a low logic level enable signal, and in this example is a low logic level enable signal. In principle, the signal ZIX is a signal controlled by the data strobe signal DQS and the signal TNDQS. When the signal TNDQS is in a disabled state, that is, at a low logic level, the signal ZIX is in a high logic level disabled state. And when the signal TNDQS is in the enabled state, that is, at a high logic level, the signal ZIX is synchronized with the data strobe signal DQS. However, the high-impedance state of the data strobe signal DQS will be converted into a high-logic-level disable state in the signal ZIX, and the procedure for switching from the high-impedance state to the high-logic level can be used generally by those skilled in the art. Well-known voltage comparison method to achieve. For example, a reference voltage between the low logic level voltage and the high impedance state voltage can be used for voltage comparison with the data strobe signal DQS. Because the voltage of the data strobe signal DQS is higher than the reference voltage when it is in a high logic level or a high impedance state, it is assumed that a high logic level voltage will be output at this time, and this high logic level voltage can make the signal ZIX becomes the disable state of high logic level.

As shown in FIG. 2 , the rising edge 212 of signal ZIX is approximately synchronous with the first rising edge 206 of data strobe signal DQS. The period between the positive edge 208 of the TNDQS signal and the positive edge 212 of the signal ZIX is the latency 202 for data reading, so the positive edge 208 can be used to start the counting register COUNT and the counting register whose initial value is 0. The register PHASE counts sequentially, and then uses the positive edge 212 to stop, and latches the count value in the count register COUNT and the count register PHASE. Among them, the counting register COUNT is a counting register that counts at twice the speed of the system clock CLK, and the counting register PHASE is a counting register that counts at four times the speed of the system clock CLK to provide higher time resolution. In practical applications, the counting speed of the counting register can be designed according to requirements, and is not limited by this embodiment. At this time, the values in the counting register COUNT and the counting register PHASE can be used as the input enable signal TNI in FIG. 1 , and the basis for detecting the preceding time point in the subsequent data reading operation. For example, after the data receiving unit sends a read command signal again, it can simultaneously start a counting register identical to the counting register COUNT to start counting. When storing the same value, it means that a period of latency has elapsed, and the input enable signal TNI can be enabled at this time to read the data line DQ and the data strobe signal DQS. Alternatively, another counting register that is the same as the counting register PHASE can also be started to start counting, and when this counting register counts to the same value as the value stored in the counting register PHASE, the enable input is enabled The signal TNI is used to read the data line DQ and the data strobe signal DQS. In comparison, using the counting register PHASE as the basis for detection can provide a higher time resolution.

Please refer to FIG. 3 , which is a flowchart of a method for calculating latency in the method of the present invention. As shown in FIG. 3 , in step 310 , the states of the signal TINDQS and the signal ZIX are first initialized to an initial state. In step 320, when the read command signal is issued, the signal TINDQS is enabled (high logic level), and starts counting. In step 330, compare and determine the logic state of the signal ZIX according to the logic level voltage of the data strobe signal DQS and a reference voltage. At this time, if the potential of the data strobe signal DQS is greater than the reference voltage, the signal ZIX is disabled. state (high logic level), if the potential of the data strobe signal DQS is lower than the reference voltage, the signal ZIX is in an enabled state (low logic level). In step 340 , stop counting when the signal ZIX changes from enabled to disabled. In step 350, the count after the counting is stopped is stored, and this count value is approximate to the latency.

Please refer to FIG. 4 , which is a flow chart of the method of the present invention. As shown in FIG. 4 , first in step 410 , a data read command is issued to the memory unit, such as the read command signal RC shown in FIG. 1 and FIG. 2 , and a latency value is obtained according to the above method. Then start counting according to the latency value in step 420 ; finally in step 430 , when the counting time is equal to the latency value, the signal TIN is enabled at this time to mark the previous arrival time point.

The above description is only a preferred embodiment of the present invention, and does not limit the present invention in any form. Although the present invention has been disclosed as above with preferred embodiments, it is not intended to limit the present invention. Anyone familiar with this field Those skilled in the art, without departing from the scope of the technical solution of the present invention, may use the method and technical content disclosed above to make some changes or modifications to equivalent embodiments with equivalent changes, but if they do not depart from the technical solution of the present invention, Any simple modifications, equivalent changes and modifications made to the above embodiments according to the technical essence of the present invention still fall within the scope of the technical solutions of the present invention.

Claims (7)

1, the preposition method of a kind of detecting information gating signal is characterized in that it may further comprise the steps:

Estimate a latent time, may further comprise the steps:

When sending a reading command signal, activation one first signal and the state that determines a secondary signal according to the accurate voltage in position and a reference voltage of this information gating signal relatively;

When this first signal transfers activation to by disabled, begin to calculate a count value with reference to clock pulse according to one; And

When this secondary signal transfers the disabled state to by enabled status, stop to calculate this count value with reference to clock pulse according to this;

Resulting count value is this latent time;

When sending another reading command signal, according to this latent time with describedly count with reference to clock pulse; And

When count value equals this latent time, send a signal in order to indicate the preposition of this information gating signal.

2, the preposition method of detecting information gating signal according to claim 1 is characterized in that wherein said reference voltage range is between the low logic level voltage of the high impedance status voltage of this information gating signal and this information gating signal.

3, the preposition method of detecting information gating signal according to claim 2, it is characterized in that wherein if the accurate voltage in position of this information gating signal greater than this reference voltage, this secondary signal of disabled then, if the accurate voltage in position of this information gating signal is less than this reference voltage, this secondary signal of activation then.

4, the preposition method of detecting information gating signal according to claim 1, the original state that it is characterized in that wherein said first signal is the disabled state, the original state of this secondary signal is the disabled state.

5, the preposition method of detecting information gating signal according to claim 1 is characterized in that the disabled position of wherein said first signal is accurate for hanging down logic level, and activation position standard is high logic level.

6, the preposition method of detecting information gating signal according to claim 1 is characterized in that the disabled position standard of wherein said secondary signal is high logic level, and the activation position is accurate for hanging down logic level.

7, the preposition method of detecting information gating signal according to claim 1 is characterized in that this method is the data that is used to read a double data transfer rate synchronous dynamic random memory body.

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