CN100444636C - A Method of Improving SDRAM Bus Efficiency in Video Decoder - Google Patents

Abstract

The present invention relates to a method for enhancing the efficiency of an SDRAM bus in a video decoder. The method comprises the steps that a new storage structure is used to make video data alternately stored in different groups of the SDRAM as an action unit; each row of images is alternately accessed according to a new access order. Thus, no matter a decoder requests for reading reference data or writing decoded data back to the SDRAM and no matter how many rows of the data are once accessed line by line or alternately, the sequence of accessing the SDRAM is alternated with different groups. Therefore, the present invention can realize the ping-pong operation of the SDRAM and largely enhance the efficiency of the bus.

Description

A Method of Improving SDRAM Bus Efficiency in Video Decoder

technical field

The invention belongs to the field of digital multimedia signal processing, in particular to a method for improving SDRAM bus efficiency in a video decoder.

Background technique

With the rapid development of network and multimedia technology, the application of digital video is more and more extensive. Due to the large amount of video data, in order to be able to transmit or store in existing media, it is usually necessary to first compress the video data through an encoder, transmit or store the compressed data, and then decode it through a decoder at the receiving end before displaying it. displayed on the device. The video data stream has a large amount of data and requires high real-time playback. The decoder needs a high-speed and large-capacity memory as a buffer for image data. Because SDRAM has the advantages of larger capacity and lower cost than SRAM and other memories, it has become a commonly used data memory in video decoders. However, the control of SDRAM is more complicated, and regular refreshing is required to maintain data, so a special SDRAM controller is required to realize the interface with SDRAM.

Figure 1 is a typical SDRAM structure diagram. 108 in the figure is a memory cell array of SDRAM. It can have multiple groups, and each group is an array of memory cells, positioned according to row and column addresses. There are two access modes of SDRAM: burst and full page. In burst mode, one operation accesses several consecutive data of the same row in one group of SDRAM. In full page mode, one operation accesses all the data in one row of SDRAM. In the above two modes, the operation of SDRAM can be interrupted by the precharge command. A typical SDRAM read and write method is as follows, the controller first sends an activation command, and when SDRAM receives the command, it locks the row address to be operated. After waiting for two to three clock cycles, send a read or write command. When SDRAM receives this command, it locks the column address to be operated. This determines the address of the data to be manipulated. For the read operation, the controller waits for two to three clock cycles after sending the read command to sample the read data on the bus. For a write operation, the controller starts presenting data on the bus at the same time as it sends the write command. After the data is read and written, a precharge command must be sent to end the operation. In this way, during one operation, there will be no data for 6 to 7 beats on the bus. When the amount of data read and written at one time is relatively small, the efficiency of the bus is very low.

In order to improve the efficiency of the bus, the operation of SDRAM can adopt the way of ping-pong operation. The so-called ping-pong operation means that in the process of operating a group, you can operate another group without waiting for the group to be released. As long as the commands for operating these two groups do not conflict with the data on the data bus and certain timing constraints are met. In this way, the empty beat in the process of reading and writing above is effectively utilized, and the efficiency of the data bus is greatly improved.

In the multimedia decoding system, video data has the largest amount of data, accounting for most of the SDRAM bus. In the decoding process, it is necessary to read the reference data stored in SDRAM into the decoder, and write the decoded data into the decoder. To display the decoded data on the display device, the data needs to be read into the display module in the decoding system. Thus video data is moved in and out of SDRAM multiple times. The load on the SDRAM bus is high. In the traditional implementation method, the video data is stored by row or by macroblock (stored row by row or interlaced row), and it cannot be guaranteed that the data read or written at one time is distributed in different banks (banks) of SDRAM, so the ping-pong operation cannot be used. The efficiency of the bus is very low.

Therefore, in the traditional implementation method, in order to ensure the normal operation of the decoder, a higher SDRAM bus frequency or a larger SDRAM data bit width is required, but this will inevitably increase the cost. Therefore, it is necessary to find a method to improve the efficiency of the SDRAM bus in the video decoder, and reduce the SDRAM bus frequency and data bit width as much as possible under the premise of ensuring the normal operation of the decoder, thereby reducing the system cost.

Contents of the invention

The object of the present invention is to provide a method for improving the efficiency of the SDRAM bus in the video decoder aiming at the deficiencies in the prior art.

In order to achieve the above object, the method for improving the efficiency of the SDRAM bus in the video decoder of the present invention includes two parts. First, a new storage structure is adopted to alternately store the video data in different groups of the SDRAM in row units, and then according to a The new access sequence alternately accesses each row of the image to read reference data and write back decoded data, realizing ping-pong operation and improving bus efficiency.

The new storage structure is specifically: the 4*N (N is an integer, the same below) row and the 4*N+3 row of the image exist in a group, and the 4*N+1 row and the 4*N row +2 row exists in another group.

The new access sequence is divided into three cases according to the format of the request data and the access start line i (i is an integer, the same below):

Case 1: The requested image data is progressive and i is an even number

The access sequence is as follows: i, i+1, i+3, i+2, i+4, i+5, i+7, i+6, i+8...

Case 2: The requested image data is progressive and i is an odd number

The access sequence is as follows: i, i+2, i+1, i+3, i+4, i+6, i+5, i+7, i+8...

Case 3: The requested image data is interlaced

The access sequence is as follows: i, i+2, i+4, i+6, i+8...

The video decoder is a decoding system that uses motion compensation technology for decoding.

The new access sequence described applies to two cases: reading reference data and writing back decoded data. The access sequence takes the first several numbers of the sequence as the actual access sequence according to the number of data rows to be read and written back. The number of data lines includes at least four cases of 4, 5, 8, and 9 when reading reference data, and at least includes two cases of 4 and 8 when writing back decoded data.

The ping-pong operation is an operation mode for continuously and alternately accessing different groups in the SDRAM supported by standard SDRAM chips.

When reading reference data, considering the half-pixel prediction of motion compensation, the number of image lines read by one visit to SDRAM may be 4, 5, 8, or 9. At this time, read 4, 5, 8, or 9 lines in the above order That's it. When writing back the decoded data, the number of image lines written back by one visit to SDRAM may be 4 or 8, and at this time, 4 or 8 lines can be written in the above order.

In the present invention, no matter whether the decoder requests SDRAM to read reference data or the decoded data is written back to SDRAM, no matter how many rows of data are accessed at a time, no matter whether the requested data format is progressive or interlaced, the order of accessing SDRAM is different groups alternately can realize the ping-pong operation of SDRAM, thus greatly improving the efficiency of the bus.

Description of drawings

Figure 1 is a typical structural diagram of SDRAM memory;

Fig. 2 is a schematic diagram of image data composition of a macroblock according to an embodiment of the present invention;

Fig. 3 is a schematic diagram of the video data storage structure in this embodiment.

Detailed ways

The method for improving SDRAM bus efficiency in the video decoder of the present invention will be described in detail below in conjunction with a specific embodiment.

In this example, the scanning format of the image data is 4:2:0, and the Y, Cr, and Cb data of one pixel are each represented by 8 bits, and the data bit width of SDRAM is 16 bits, and one storage unit of SDRAM can store the data of two pixels. Luminance or color difference data. According to Figure 2, a schematic diagram of the image data composition of a macroblock in the 4:2:0 mode, where 0, 1, 2, and 3 represent four 8×8 pixel brightness blocks, and 4 represents a 8×8 pixel Cr Block, 5 represents a Cb block of 8×8 pixels. When the decoder reads the reference data, two luminance blocks of 0 and 1, two luminance blocks of 2 and 3, and two color difference blocks of 4 and 5 are combined together to read from SDRAM. Two brightness blocks 0 and 1, two brightness blocks 2 and 3, and two color difference blocks 4 and 5 are combined and written into SDRAM.

Fig. 3 is a schematic diagram of video data storage structure in an embodiment of the present invention. The SDRAM memory contains two banks, called bank 0 and bank 1. The image data of the 0th, 4th, 8th...4*N lines and the 3rd, 7th, 11th...4*N+3 lines of the image are stored in group 0, and the 1st, 5th, 9th...4*N+1 lines of the image And the 2nd, 6th, 10th... 4*N+2 rows of image data are stored in group 1.

Below, the access order of the present invention is divided into three cases according to the format of the request data and the access start row i for example, assuming that the image data of each access is 9 rows:

Case 1: The requested image data is progressive and i is an even number

The access sequence is as follows: i, i+1, i+3, i+2, i+4, i+5, i+7, i+6, i+8...

Taking i=4 as an example, the actual access sequence is 4, 5, 7, 6, 8, 9, 11, 10, 12. As shown in Figure 3, the requirements of the ping-pong operation are met.

Case 2: The requested image data is progressive and i is an odd number

The access sequence is as follows: i, i+2, i+1, i+3, i+4, i+6, i+5, i+7, i+8...

Taking i=5 as an example, the actual access sequence is 5, 7, 6, 8, 9, 11, 10, 12, 13. As shown in Figure 3, the requirements of the ping-pong operation are met.

Case 3: The requested image data is interlaced

The access sequence is as follows: i, i+2, i+4, i+6, i+8...

Taking i=1 as an example, the actual access sequence is 1, 3, 5, 7, 9, 11, 13, 15, 17. As shown in Figure 3, the requirements of the ping-pong operation are met.

As long as a simple analysis is performed, it can be proved that no matter whether the decoder requests SDRAM to read reference data or decoded data is written back to SDRAM, no matter how many lines of data are accessed at a time, no matter whether the requested data format is progressive or interlaced, the order of accessing SDRAM Different groups are performed alternately, and all meet the requirements of ping-pong operation.

When the ping-pong operation is not used, the number of clock cycles occupied by reading and writing SDRAM valid data in this example is 8, and the number of clock cycles occupied by the empty beat is 6 or 7 (calculated as 7 here), so the SDRAM bus efficiency is about 8 /(8+7)≈53.3%. When using the ping-pong operation, in this example, the number of clock cycles occupied by reading and writing SDRAM effective data once is expanded to 72 (9 lines of image data are connected in series for one access), so the SDRAM bus efficiency is about 72/(72+7)≈ 91.1%.

Actual SDRAM bus efficiency is related to the performance parameters of the SDRAM chip with the number of pixels and the number of rows of one visit, but as long as a simple analysis can be proved, the SDRAM bus efficiency can be clearly obtained in the video decoder by adopting the method of the present invention. improve.

As mentioned above, the present invention first uses a new storage structure to alternately store video data in different groups of SDRAM in row units, and then alternately accesses each row of the image according to a new access sequence to read reference data and write back decoding Data, realize the ping-pong operation, and obviously improve the efficiency of the SDRAM bus in the video decoder without increasing the resources of the decoder.

Although the present invention has been particularly described with reference to preferred embodiments thereof, it will be understood by those skilled in the art that changes may be made in form and detail without departing from the spirit and scope of the invention as defined in the appended claims. various modifications.

Claims (3)

1, improve the method for SDRAM bus efficiency in the video decoder, it is characterized in that this method adopts a kind of new storage structure that video data is alternately stored in the different groups of SDRAM with row unit, according to a kind of new access sequence alternate access image Each row is used to read reference data and write back decoded data to realize ping-pong operation and improve bus efficiency; The new storage structure is specifically: the 4*N line and the 4*N+3 line of the image are stored in one group, and the 4*N+1 line and the 4*N+2 line are stored in another group , where N is an integer; The new access sequence is divided into three cases according to the format of the requested data and the access start row i, where i is an integer, specifically: Case 1: The requested image data is progressive and i is an even number The access sequence is as follows: i, i+1, i+3, i+2, i+4, i+5, i+7, i+6, i+8... Case 2: The requested image data is progressive and i is an odd number The access sequence is as follows: i, i+2, i+1, i+3, i+4, i+6, i+5, i+7, i+8... Case 3: The requested image data is interlaced The access sequence is as follows: i, i+2, i+4, i+6, i+8.... 2. The method for improving SDRAM bus efficiency in a video decoder as claimed in claim 1, characterized in that said video decoder is a decoding system that uses motion compensation technology for decoding. 3, the method for improving SDRAM bus efficiency in the video decoder as claimed in claim 1 is characterized in that described new access sequence is applied to two kinds of situations: read reference data and write back decoded data; This access sequence according to The number of data rows that need to be read and written back takes the first few numbers of the sequence as the actual access sequence; the number of data rows includes at least four cases of 4, 5, 8, and 9 when reading reference data. When writing decoded data, include at least 4 and 8 cases.

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