CN100426252C - Device and method to regulate automatically data sampling dot of output interface of testing data - Google Patents

Abstract

The invention relates to a device for automatically adjusting the data sampling point of a test data output port, including: a scanning unit, which is used to scan the scanning link with test data, and judge whether the sampling point is reliable according to the scanning result, and output when the sampling point is reliable Test success information; the adjustment unit is used to set the initial sampling point of the scanning unit, and when the scanning unit determines that the sampling point is unreliable, the set sampling point is delayed for a predetermined time; the first judging unit is used to judge whether the sampling point time value is lower than the lower limit and sends the set sampling point to the scanning unit when it is determined that the time value of the sampling point is not lower than the predetermined lower limit, and when it is determined that the time value of the sampling point after a predetermined delay is lower than the predetermined lower limit of the sampling point, output Information about test failures. The invention also provides a corresponding method. The invention avoids manual intervention in the process of adjusting the data sampling point of the test data output port, and improves the application efficiency.

Description

A device and method for automatically adjusting data sampling points of test data output ports

technical field

The invention relates to the field of testing, more specifically, to a device and method for automatically adjusting data sampling points of test data output ports.

Background technique

The boundary scan technology improves the controllability and observability of the device by placing a boundary scan unit between the input and output pins of the device and the core circuit, and revolutionizes the testing method of the device and its peripheral circuits. It was proposed to solve the problem of interconnection testing on circuit boards, and later developed to be applied to various occasions such as on-board programming of logic chips and on-board programming of FLASH. Currently, most chips support boundary-scan testing.

For ease of description, the relevant abbreviations and terms related to the boundary scan of the present invention are listed as follows:

JTAG: Joint Test Action Group, Joint Test Action Group;

BS: Boundary Scan, boundary scan;

BSC: Boundary Scan Cell, boundary scan unit;

TCK: Test Clock, test clock;

TAP: Test Access Port, test access port;

TDI: Test Data Input, test data input;

TDO: Test Data Output, test data output;

TMS: Test Mode Select, test mode selection;

TRST: Test Reset, test reset;

BSDL: Boundary-Scan Description Language, Boundary-Scan Description Language.

As shown in FIG. 1 , a boundary scan test system usually consists of three parts: a computer 11 , a boundary scan test controller 12 and a circuit board under test 13 . The computer 11 may be a personal computer, a portable computer, a workstation, and the like. Boundary scan test controller 12 communicates with computer 11 through interfaces such as PCI, ISA, USB, converts the data sent by computer 11 into the required data format of boundary scan, and produces TCK signal; Simultaneously, boundary scan test controller 12 passes the test The access port (TAP) is connected with the circuit board under test 13 to carry out data transmission related to the boundary scan test, and the transmitted data includes test mode selection (TMS), test clock (TCK), test data input (TDI), test reset (TRST ), test data output (TDO) data, etc.

In the boundary scan test system, when testing multiple boundary scan chips, they are usually connected into a boundary scan chain, as shown in Figure 2. The test stimulus data is input through the TDI port, and the test response data is retrieved through the test data output port. Since there is a relatively large transmission delay between the test signal from the output terminal of the circuit board under test 13 to the boundary scan test controller 12, the boundary scan test controller 12 will perform an appropriate delay when sampling the recovered data, to obtain data synchronous sampling points of the test data output port corresponding to the test data input. Generally speaking, the test controller delays sampling by at least half a TCK cycle. The data timing of the test data output port at this time is shown in FIG. 3 , and the boundary scan test controller 12 starts sampling at the falling edge of the first clock cycle.

However, when the transmission distance between the test data output port of the last device on the board to be tested and the boundary scan test controller 12 is relatively long, the transmission delay will increase. If there is a driver chip in the above-mentioned transmission link, further delay will be generated. In this case, continuing to use delayed half TCK cycle sampling will result in sampling data errors. In order to avoid errors, the sampling point should be adjusted and delayed by the corresponding time. Fig. 4 and Fig. 5 respectively show the positions of data sampling points of the test data output port required to ensure correct acquisition of output data when the data of the test data output port is delayed by half a cycle and one half cycle. It can be seen from Figure 4 and Figure 5 that if the sampling point is selected incorrectly, the correct test data output port data will not be obtained.

The above-mentioned Fig. 3 , Fig. 4 , and Fig. 5 are all for the case where the sampling clock is TCK. In practical applications, other clock signals can also be used for sampling, as long as the sampling clock and the test clock TCK are multiplied. The higher the frequency of the sampling clock, the more precise the adjustment of the sampling point.

At present, the adjustment of the data sampling point of the test data output port is done manually. The process is usually: the sampling point delayed by half a TCK cycle is used as the initial sampling point, and when the test or programming fails, the data of the test data output port is manually synchronized. The sampling point is delayed for a certain time, and if it fails, it will be delayed again until it succeeds. The disadvantages of this manual intervention method in the prior art are obvious: low efficiency, high cost of use, and not conducive to the realization of large-scale automatic testing.

Contents of the invention

In order to avoid manual intervention in the boundary scan test process, improve efficiency, reduce test manpower and time costs, and realize automatic testing, the embodiment of the present invention creatively proposes a device for automatically adjusting the data sampling point of the test data output port, including:

The scanning unit is used to scan the scanning link using the test data, and judge whether the sampling point is reliable according to the scanning result, and output the test success information when the sampling point is reliable;

An adjustment unit, configured to set the initial sampling point of the scanning unit, and delay the set sampling point for a predetermined time when the scanning unit determines that the sampling point is unreliable;

A first judging unit, configured to judge whether the sampling point time value set by the adjustment unit is lower than a predetermined lower limit and send the set sampling point to the scanning unit when it is determined that the sampling point time value is not lower than the predetermined lower limit, And when it is determined that the time value of the sampling point delayed by the predetermined time is lower than the lower limit of the predetermined sampling point, the information of the test failure is output.

Embodiments of the present invention also provide a method for automatically adjusting the data sampling point of the test data output port, comprising the following steps:

(a) The sampling point is set as the test data output synchronous sampling point;

(b) Input test data to the link under test, execute the test operation and judge whether the current sampling point is reliable under the current sampling point, if the current sampling point is reliable, then perform step (c); if the current sampling point is unreliable, then perform step (d);

(c) output a test success message;

(d) Delay the current sampling point for a predetermined time, and judge whether the current sampling point after the delay predetermined time is lower than the predetermined lower limit, if the current sampling point is lower than the lower limit, then perform step (e); if the current sampling point is not lower than Lower limit, go to step (b);

(e) Output a test failure message.

By using this method, the manual intervention in the process of adjusting the data synchronization sampling point of the test data output port is avoided, the application efficiency is improved, and the automation degree of the chip test is increased; the production efficiency can be improved in production, and the cost of manpower input and manual intervention can be reduced. Time costs.

Description of drawings

Embodiments of the present invention will be further described below in conjunction with the accompanying drawings. In the accompanying drawings:

FIG. 1 is a schematic diagram of the composition of an existing boundary-scan test system;

FIG. 2 is a schematic diagram of an existing boundary-scan link composed of three boundary-scan chips;

Fig. 3 is a schematic diagram of sampling the link test data output port data in Fig. 2 at the TCK falling edge of the first clock cycle;

Fig. 4 is a schematic diagram of sampling the link test data output port data in Fig. 2 on the rising edge of TCK in the second clock cycle;

Fig. 5 is a schematic diagram of sampling the link test data output port data in Fig. 2 on the falling edge of TCK in the third clock cycle;

FIG. 6 is a schematic structural diagram of a conventional boundary scan chip.

Fig. 7 is the structural block diagram of the embodiment of the device for automatically adjusting the data sampling point of the test data output port of the present invention;

Fig. 8 is a structural block diagram of the first embodiment of the scanning unit in Fig. 7;

Fig. 9 is a structural block diagram of the second embodiment of the scanning unit in Fig. 7;

Fig. 10 is a structural block diagram of a third embodiment of the scanning unit in Fig. 7;

Fig. 11 is a flow chart of the first embodiment of the method for automatically adjusting the data sampling point of the test data output port in the present invention.

Detailed ways

The scanning link formed by the boundary scan chips involved in the test is shown in Figure 2. There are only three chips in Figure 2. The scanning link with one or more chips is similar to this. The test data output signal of each chip is used as the link The test data input of the adjacent next chip (if the next chip exists). A schematic diagram of the structure of each chip is shown in FIG. 6 .

It can be seen from the chip structure in Figure 6 that there are two paths for test data from input to output:

A path passes through the instruction register, that is, the test data input port→the instruction register→the test data output port. The link formed by each chip using this path is called the instruction register link;

The other path passes through the Boundary Scan Cell (BSC), that is, the test data input port→BSC→...→BSC→test data output port. The link formed by each chip using this path is called the Boundary Scan Cell link.

The length of these two paths, that is, the length of the instruction register and the number of BSCs, can be automatically obtained from the BSDL (Boundary-Scan Description Language, Boundary-Scan Description Language) file.

As shown in FIG. 7 , it is a structural block diagram of an embodiment of the device for automatically adjusting the data sampling point of the test data output port in the present invention. In this embodiment, the device for automatically adjusting test data output sampling points includes: a scanning unit 73 , a setting unit 74 , and a first judging unit 76 .

The scanning unit 73 is configured to scan the scanning link, judge whether the sampling point is reliable according to the scanning result, and output test success information when the sampling point is reliable. In this embodiment, the scanning unit 73 uses the test data to scan the scanning link multiple times at the same sampling point. If the scanning unit 73 is scanning multiple times, the data output by each test data output port equals the input test data under the same sampling point, then it means that the current sampling point is reliable; if the data output by any test data output port is not equal to the input test data, it means that the sampling point is unreliable. The number of judgments at the same sampling point can be selected according to the reliability requirements of the system and the test time, for example, 10 times, or other natural numbers. Generally, the higher the reliability requirement, the more scan times; the longer the test time, the more scan times can be performed.

In this embodiment, the scanning unit 73 is connected to a test access port (Test Access Port, TAP) on the scanning link through a connecting device, thereby inputting test data and TCK frequency to the test data input port and the scanning link. Test clock and get output data through this test data output port. In practical applications, the connecting device may be a JTAG controller.

The adjustment unit 74 is configured to set an initial sampling point of the scanning unit 73, and delay the set sampling point for a predetermined time when the scanning unit 73 determines that the current sampling point is unreliable. The adjustment unit 74 sets the initial value of the sampling point of the scanning unit 73 as the test data input port data delay of half a clock period Ts, and when the scanning unit 73 determines that the sampling point is unreliable, the sampling point is delayed by a predetermined time to generate a new sampling point. point, and send the new sampling point to the first judging unit 76.

The amplitude of each delay time of the sampling point by the adjustment unit 74, that is, the above-mentioned predetermined time value, can be adjusted according to the needs of the test, for example, each delay is half a TCK cycle or 1/4 TCK cycle, or any corresponding value. Generally, the higher the reliability requirement, the smaller the range of each delay time.

The first judging unit 76 is used for judging whether the time value of the sampling point set by the adjustment unit 74 is lower than a predetermined lower limit and sending the set sampling point to the The scanning unit 73 outputs the information that the test fails when it is determined that the time value of the sampling point delayed by the predetermined time is lower than the lower limit of the predetermined sampling point. The predetermined lower limit is an acceptable lower limit of sampling point time for the predetermined boundary scan test. The predetermined lower limit mentioned above is an acceptable delay range jointly determined according to the scan link length, signal transmission distance, chip type and performance, etc., and can be preset. When there is no reliable test data output port data later than this time point When sampling points, it is meaningless to continue searching.

As shown in FIG. 8 , it is a detailed structural diagram of the first embodiment of the scanning unit 73 in FIG. 7 . In this embodiment, the scanning unit 73 is used to scan the instruction register link, which specifically includes a first instruction unit 81 , a second judging unit 82 and a third judging unit 83 .

The first command unit 81 is used to scan the link of the command register, that is, to input data through the test data input port, pass through the command register, and output it through the test data output port. The second judging unit 82 is used to judge whether the current sampling point is reliable according to the output data of the test data output port under the sampling point provided by the adjustment unit 74, that is, judge whether the data output by the test data output port is the same as the input test data ( In this embodiment, the initial sampling point of the fourth judgment unit 92 is T _s ), if not the same, a signal is sent to the adjustment unit 74, and the adjustment unit 74 delays the current sampling point by a predetermined time, and makes the first instruction unit 81 continues to scan the command register link, and the second judging unit 82 judges whether the sampling point after the predetermined time delay is reliable; If the predetermined number of times is reached, the test success information will be output; otherwise, the second judging unit 82 will continue to judge whether the current sampling point is reliable under the current sampling point.

As shown in FIG. 9 , it is a detailed structural diagram of the second embodiment of the scanning unit 73 in FIG. 7 . In this embodiment, the scanning unit 73 specifically includes a first data unit 91 , a fourth judging unit 92 and a fifth judging unit 93 .

The first data unit 91 is used for boundary scan link scan, that is, data is input through the test data input port, passes through each boundary scan unit in turn, and is output through the test data output port. The fourth judging unit 92 is used for judging whether the sampling point is reliable according to the scanning result of the first data unit 91 under the sampling point set by the adjustment unit 74, that is, judging whether the data output by the test data output port under the current sampling point is equal to The input test data (in this embodiment, the initial sampling point of the fourth judging unit 92 is T _s ), if not equal to, then send a signal to the adjustment unit 74, the current sampling point is delayed by the adjustment unit 74 for a predetermined time, and Make the first data unit 91 continue to scan the instruction register link, and the fourth judging unit 92 judges whether the sampling point after the predetermined time delay is reliable; if it is equal, the fifth judging unit 93 further judges that the first data unit 91 scans under the current sampling point Whether the number of times reaches the predetermined number of times, if reached, the test success information is output, otherwise, the fourth judging unit 92 continues to judge whether the current sampling point is reliable under the current sampling point.

As shown in FIG. 10 , it is a detailed structural diagram of the third embodiment of the scanning unit 73 in FIG. 7 . In this embodiment, the scanning unit 73 is used to scan the instruction register link and the boundary scan unit link, which specifically includes the second instruction unit 101, the sixth judging unit 102, the seventh judging unit 103, the second data unit 105, The eighth judging unit 104 and the ninth judging unit 106 .

The second command unit 101 is used to scan the link of the command register, that is, to input the test data through the test data input port, pass through the command register, and output it through the test data output port. The sixth judging unit 62 is used to judge whether the current sampling point is reliable according to the scanning result of the second command unit 101 under the sampling point provided by the adjustment unit 74, that is, judge whether the data output by the test data output port is equal to the input test data (in this In the embodiment, the initial sampling point of the fourth judging unit 92 is T _s ), if it is not equal, a signal is sent to the adjusting unit 74, and the adjusting unit 74 delays the current sampling point by a predetermined time, and the second instruction unit 101 continues Scan the command register link, the sixth judging unit 102 judges whether the sampling point after the predetermined time delay is reliable; if equal, the seventh judging unit 103 further judges whether the number of times the second instruction unit 101 scans at the current sampling point reaches the predetermined number of times , if reached, the second data unit 105 performs boundary scan unit link scanning; otherwise, sends a signal to the second instruction unit 101, and the second instruction unit 101 continues to scan the instruction register link.

The second data unit 105 is used to scan the boundary scan cell link. The second data unit 105 inputs the test data through the test data input port, passes through each boundary scan unit, and outputs the test data output port after the seventh judging unit 103 judges that the instruction scan reaches a predetermined number of times. The eighth judging unit 104 judges whether the sampling point determined by the seventh judging unit 103 to reach a predetermined number of command scans is reliable according to the scan result of the second data unit 105, that is, judges whether the data output by the test data output port is the same as the input test data, If not the same, the adjustment unit 74 delays the sampling point for a predetermined time, and the second instruction unit 101 scans the instruction register link; if the same, the ninth judging unit 106 further judges that the second data unit 105 is under the current sampling point Whether the number of scans reaches the predetermined number of times, if so, output the test success information, otherwise send a signal to the second data unit 105, and the second data unit 105 continues to scan the boundary scan cell link at the current sampling point.

Likewise, the number of scans at the same sampling point in the above embodiment can be selected according to the reliability requirements of the system and the test time.

As shown in FIG. 7 , it is a flow chart of the first embodiment of the method for automatically adjusting the test clock frequency of the present invention. In this embodiment, the combination of command scanning and data scanning is used to judge whether the sampling point is reliable, which specifically includes the following steps:

Step 701, acquire the total instruction link length and the total boundary scan unit length of the boundary scan link. In this step, it can be realized by analyzing the BSDL file of each boundary scan chip on the boundary scan link or similar files describing the performance parameters of each boundary scan chip, wherein the total instruction link length is the length of the instruction register of each boundary scan chip The total length of the boundary scan unit is the sum of the number of BSCs of each boundary scan chip.

Step 702, set the sampling point as half a clock period Ts of the data delay of the test data input port.

Step 703, use the test data to execute m command scans at the set sampling point, and judge whether the current sampling point is reliable, that is, judge whether the data output by the test data output interface is consistent with the data input by the test data input interface, wherein the input scan The data used can be specific data such as 0x55AA, etc., or random data. If any of the results are inconsistent, it is determined that the current sampling point is unreliable, and step 707 is performed; if the m results are all consistent, then step 704 is performed.

The above-mentioned m instruction scans can be realized through the following steps:

(b11) input the test data from the test data input interface, and output from the test data output interface through the instruction register link;

(b12) judging whether the output data is consistent with the input data at the current sampling point, if the output data is inconsistent with the input data, then determine that the current sampling point is unreliable, and perform step 707; otherwise, perform step (b13);

(b13) Add 1 to the number of scans using test data under the current sampling point, and judge whether the number of scans under the current sampling point reaches m times, if the number of scans under the current sampling point reaches m times, then determine that the current sampling point is reliable, Execute step 704; otherwise, execute step (b11).

Step 704, use the test data to perform n times of data scanning operations at the current sampling point, and judge whether the data output from the test data output interface is consistent with the data from the test data input interface, wherein the input test data can be specific data Such as 0x55AA, etc., can also be random data. If the n times of results are consistent, execute step 705; if any of the results are inconsistent, then determine that the current sampling point is unreliable, and execute step 707.

The above n times of data scanning can be realized through the following steps:

(b21) Input the test data from the test data input interface, and output it from the test data output interface through the boundary scan unit link;

(b22) judging whether the output data is consistent with the input data at the current sampling point, if the output data is inconsistent with the input data, then determine that the current sampling point is unreliable, and perform step 707; otherwise, perform step (b23);

(b23) Add 1 to the number of times of using test data scanning under the current sampling point, and judge whether the number of times of scanning reaches n times, if the number of times of scanning under the current sampling point reaches n times, then determine that the current sampling point is reliable, and execute step 705; Otherwise execute step (b21).

Step 705, determine that the current sampling point is reliable, and report that the adjustment is successful;

Step 707, delaying the current sampling point for a predetermined time, and then performing step 708;

Step 708, judge whether the sampling point after the predetermined time delay has been lower than the predetermined lower limit, if it is lower, it means that there is no reliable sampling point within the set range, report failure and end the adjustment process; if the sampling point after the predetermined time delay If it is not lower than the predetermined lower limit, step 703 is executed.

The aforementioned m and n are preset cycle numbers, which are selected according to reliability requirements and test time, for example, m=n=10, or other natural numbers. Generally, the higher the reliability requirement, the larger the values of m and n; the longer the test time, the larger the values of m and n.

In the second embodiment of the method for automatically adjusting test data output sampling points of the present invention, only instruction scanning is used to judge whether the sampling points are reliable. Similar to the above-mentioned embodiment, in this embodiment, the command scan is performed after the total command link length of the boundary scan link is obtained, and whether the current sampling point is reliable is judged. If the current sampling point is reliable, that is, the data output by each test data output interface in m command scans is consistent with the data input by the test data input interface, the report is successful; otherwise, the current sampling point is delayed for a predetermined time in turn, and the delay reservation is used. The sampling point after the time is scanned for instructions until the sampling point after the reduction is lower than the lower limit, and a failure is reported.

In the third embodiment of the method for automatically adjusting test data output sampling points of the present invention, only data scanning is used to determine whether the sampling points are reliable. Similar to the foregoing embodiments, in this embodiment, data scanning is performed after obtaining the total boundary scan unit length, and it is judged whether the current sampling point is reliable. If the current sampling point is reliable, that is, the data output by each test data output interface is consistent with the data input by the test data input interface in n data scans, then the report is successful; otherwise, the current sampling point is delayed for a predetermined time in turn, and the delay reservation is used. Data scanning is performed at the sampling point after the time delay until the sampling point is lower than the lower limit after a predetermined time delay, and a failure is reported.

Instruction scan and data scan in the above-mentioned embodiment are the operation that all chips that support boundary scan all support, so have versatility, have realized automatic adjustment test data output sampling point, thereby improved test efficiency, and reduced test process. Human input.

The above is only a preferred embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any person skilled in the art within the technical scope disclosed in the present invention can easily think of changes or Replacement should be covered within the protection scope of the present invention. Therefore, the protection scope of the present invention should be determined by the protection scope of the claims.

Claims (8)

1, a kind of device of automatic adjustment test data output port data sampled point is characterized in that, includes:

Scanning element is used for the use test data scan chain circuit is scanned, and judges according to scanning result whether sampled point is reliable, and successful information is tested in output when sampled point is reliable;

Adjustment unit is used to be provided with the initial sampled point of scanning element, and makes set sampled point delay scheduled time when scanning element determines that sampled point is unreliable;

First judging unit, whether the sampled point time value that is used to judge described adjustment unit setting is lower than predetermined lower limit and when determining that the sampled point time value is not less than predetermined lower limit the sampled point of described setting is sent to scanning element, and the sampled point time value after determining delay scheduled time is when being lower than predetermined lower limit, the information of output test crash.

2, the device of automatic adjustment test data output port data sampled point according to claim 1 is characterized in that described scanning element comprises

First command unit is used for the scan instruction chain of registers;

Second judging unit is used for judging according to the output data of test data output port whether current sampling point is reliable, and make the current sampling point delay scheduled time by adjustment unit when definite current sampling point being unreliable under the sampled point that adjustment unit is provided with;

The 3rd judging unit, be used to judge whether the number of times that first command unit scans reaches pre-determined number under current sampling point, and when reaching pre-determined number output test successful information, when reaching pre-determined number, whether reliably do not continue at the current sampling point current sampling point that judges by second judging unit.

3, the device of automatic adjustment test data output port data sampled point according to claim 1 is characterized in that described scanning element comprises

First data cell is used to carry out the scanning of boundary scan cell link;

The 4th judging unit is used for judging according to the scanning result of described first data cell whether current sampling point is reliable under the sampled point that adjustment unit is provided with, and makes the current sampling point delay scheduled time by adjustment unit when definite current sampling point is unreliable;

The 5th judging unit, be used to judge whether the number of times that first data cell scans reaches pre-determined number under current sampling point, and when reaching pre-determined number output test successful information, when reaching pre-determined number, whether reliably do not continue at the current sampling point current sampling point that judges by the 4th judging unit.

4, the device of automatic adjustment test data output port data sampled point according to claim 1 is characterized in that described scanning element comprises

Second command unit is used for the scan instruction chain of registers;

The 6th judging unit is used for judging according to the output data of test data output port whether current sampling point is reliable, and make the current sampling point delay scheduled time by adjustment unit when definite current sampling point being unreliable under the sampled point that adjustment unit is provided with;

Whether the 7th judging unit is used to judge whether the number of times that second command unit scans reaches pre-determined number under current sampling point, and continue at the current sampling point current sampling point that judges reliable by the 6th judging unit when not reaching pre-determined number;

Second data cell is used for scanning boundary scanning element link when the 7th judging unit determines that instruction scan reaches pre-determined number;

The 8th judging unit, be used under the sampled point when the 7th judging unit determines that instruction scan reaches pre-determined number, judge according to the output data of test data output port whether current sampling point is reliable, and when definite current sampling point is unreliable, make the current sampling point delay scheduled time by adjustment unit;

The 9th judging unit, be used to judge whether the number of times that second data cell scans reaches pre-determined number under current sampling point, and when reaching pre-determined number output test successful information, when reaching pre-determined number, whether reliably do not continue at the current sampling point current sampling point that judges by the 8th judging unit.

5, according to the device of each described automatic adjustment test data output port data sampled point among the claim 1-4, it is characterized in that described scanning element includes coupling arrangement, described coupling arrangement is connected to the test access interface on the scan chain circuit.

6, a kind of method of automatic adjustment test data output port data sampled point is characterized in that, may further comprise the steps:

(a) sampled point is set to test data output synchronous sampling point;

(b) to tested link input test data, carry out test operation and whether reliable at the current sampling point current sampling point that judges, if current sampling point is reliable, execution in step (c) then; If current sampling point is unreliable, then execution in step (d);

(c) output test success message;

(d) make the current sampling point delay scheduled time, and judge whether the current sampling point behind the delay scheduled time is lower than predetermined lower limit, if current sampling point is lower than then execution in step (e) of predetermined lower limit; If current sampling point is not less than predetermined lower limit, execution in step (b);

(e) output test crash message.

7, the method for automatic adjustment test data output port data sampled point according to claim 6 is characterized in that, described step (b) comprises step:

(b11) test data is imported from the test data input interface, exported from the test data output interface through the order register link;

Whether (b12) consistent with the input data in the current sampling point output data that judges, if output data is inconsistent with the input data, then definite current sampling point is unreliable, execution in step (d); Otherwise execution in step (b13);

(b13) judge whether the number of times that scans under the current sampling point reaches pre-determined number,, determine that then current sampling point is reliable, execution in step (c) if the scanning times under the current sampling point reaches pre-determined number; Otherwise execution in step (b11).

8, the method for automatic adjustment test data output port data sampled point according to claim 6 is characterized in that, described step (b) comprises step:

(b21) test data is imported from the test data input interface, exported from the test data output interface through the boundary scan cell link;

Whether (b22) consistent with the input data in the current sampling point output data that judges, if output data is inconsistent with the input data, then definite current sampling point is unreliable, execution in step (d); Otherwise execution in step (b23);

(b23) judge whether the number of times that scans under the current sampling point reaches pre-determined number,, determine that then current sampling point is reliable, execution in step (c) if reach pre-determined number at the scanning times of current sampling point; Otherwise execution in step (b21).

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