CN100418221C - Electro-optical devices and electronic instruments - Google Patents

Abstract

The invention provides an electrooptical device and electronic apparatus. The electro-optical apparatus are capable of narrowing the frame region. A light-emitting power source wiring lines and second electrode wiring lines disposed around a first electrode region where first electrodes are arranged in a matrix on a substrate, the light-emitting power source wiring lines being connected to the first electrodes, the second electrode wiring lines being connected to a second electrode, a functional layer being interposed between the first electrodes and the second electrode, wherein the light-emitting power source wiring lines and the second electrode wiring lines are arranged such that at least some of the wiring lines overlap each other in plan view. In addition, the electronic apparatus has the electrooptical device.

Description

Electro-optical devices and electronic instruments

This application is a divisional application of the application number: 03140936.9, the name of the invention: electro-optic device and electronic instrument, and the application date: 2003.6.4.

technical field

The present invention relates to electro-optical devices and electronic instruments.

Background technique

In recent years, an organic EL (Electroluminescence) display device having a light-emitting element using an organic light-emitting material between a substrate on which a pixel electrode is formed and a common electrode (for example, refer to JP-A-5-3080) has attracted attention. .

In an organic EL display device, a light-emitting element emits light by supplying a current to the light-emitting element. At this time, the luminance of the light emitting element is basically determined by the amount of current supplied.

As described above, the luminance of the light-emitting element is basically determined by the current amount of the supplied current, so it is necessary to set it correctly so that the current amount becomes a desired value.

In addition, if a sufficient amount of current is to be ensured, the width of wiring for supplying current increases, and the frame area increases, which may cause trouble when mounting it in various electronic devices.

Contents of the invention

The present invention has been made in view of the above facts, and its first object is to secure a sufficient amount of current or to suppress fluctuations in luminance of light-emitting elements caused by fluctuations in power supply voltage. Another object of the present invention is to provide a light-emitting device and an electronic device that satisfy the above-mentioned requirements and enable frame narrowing.

In order to achieve the object, the present invention employs the following structures.

In an electro-optic device according to one aspect of the present invention, a plurality of light-emitting power supply wirings are arranged in the first layer on the substrate, and a plurality of connecting wirings connecting the light-emitting power supply wirings to corresponding electrodes are arranged in the first layer connected to the first layer. In the electrically insulating second layer, the power supply wiring for light emission located on the outermost side among the plurality of power supply wirings for light emission is provided on both the first layer and the second layer.

Since the light-emitting power supply wiring located on the outermost side does not overlap the connection wiring in plan, it can also be provided in the second layer. Therefore, in the present invention, if the light-emitting power supply wirings provided in the first layer and the second layer are electrically connected, the number of light-emitting power supply wirings in each layer can be reduced compared with the case where only one layer is provided. width. Therefore, in the present invention, it is possible to reduce the frame of the panel corresponding to the reduction in the width of the power supply wiring for light emission.

In the electro-optic device, preferably, among the plurality of light-emitting power supply wirings, a connection wiring connected to at least the light-emitting power supply wiring located on the innermost side is provided in the first layer.

Since the wiring for connection connected to the power supply wiring for light emission positioned on the innermost side does not overlap with wiring other than the power supply wiring for light emission, it can be provided in the first layer.

Therefore, in the present invention, the width portion of the connection wiring can make the other connection wiring provided in the second layer thicker, and the manufacture of the connection wiring can be facilitated. In addition, contact points between the outermost and inner light-emitting power supply lines and connection lines are unnecessary, and the dependence of contact resistance can be reduced.

A structure in which a hole injection/transport layer and a light emitting layer made of an organic electroluminescent material formed adjacent to the hole injection/transport layer are provided on the electrode can be employed.

Therefore, in the present invention, a small-sized panel with little dependency on contact resistance is obtained in which driving current is applied to the electrodes to emit light through the light-emitting power supply wiring and the connection wiring.

In the electro-optical device according to the second aspect of the present invention, a light-emitting power supply wiring connected to the first electrode and a power supply wiring connected to the first electrode are arranged around the first electrode region in which the first electrodes are arranged in a matrix on the substrate. The second electrode wiring on the second electrode sandwiching the functional layer between the first electrodes is characterized in that the light emitting power supply wiring and the second electrode wiring are arranged so as to at least partially overlap each other in plan view.

In the above-mentioned electro-optical device, it is preferable that an interlayer insulating layer is disposed between the light-emitting power supply wiring and the second electrode wiring. Accordingly, in the electro-optic device, the portion where the power supply wiring for light emission and the wiring for the second electrode overlap in plan view can reduce the area dedicated to these wirings, and narrow the frame of the panel. In addition, by overlapping at least a part of the light-emitting power supply wiring and the second electrode wiring, an electrostatic capacitance is formed, so that the potential fluctuation of the driving current is reduced, and image display can be stably performed.

In the electro-optic device described above, it is desirable that an interlayer insulating film is disposed between the light-emitting power source wiring and the second electrode wiring. Thereby, the power source wiring for light emission and the wiring for 2nd electrode can be insulated.

In the electro-optical device described above, either one of the light-emitting power supply wiring and the second electrode wiring can be arranged in a region occupied by the other.

Therefore, in the present invention, it is not necessary to provide additionally in a plan view, and it is possible to further contribute to frame narrowing by arranging an area of either one of the power supply wiring for light emission and the wiring for the second electrode.

As the functional layer, a structure in which a hole injection/transport layer and a light emitting layer made of an organic electroluminescent material formed adjacent to the hole injection/transport layer can be employed.

Therefore, in the present invention, it is possible to obtain a small panel that emits light by applying a drive current to the first electrode through the power source wiring for light emission.

The electro-optic device of the present invention 3 is characterized in that it includes: a plurality of pixels including an electro-optic element having a functional layer sandwiched between a first electrode and a second electrode provided in an active area on a substrate; The electrode wiring connected to the second electrode outside the effective area; the connecting wiring provided at least on the effective area to connect to the first electrode through an active element; outside the effective area A power supply line connected to the connection wiring; and at least a part of the power supply line is formed of a plurality of conductive films separated by an interlayer insulating film and a conductive material electrically connecting the plurality of conductive films to each other.

The electro-optic device of the fourth aspect of the present invention is characterized in that it includes: a plurality of pixels including an electro-optic element having a functional layer sandwiched between a first electrode and a second electrode provided in an active area on a substrate; The wiring for electrodes connected to the second electrode on the outside of the effective area; the wiring for connecting to the first electrode through an active element and provided at least on the effective area; The outer side of the power line connected to the connection wiring; and a plurality of the power lines are provided outside the effective area, and among the power lines, the power line that is arranged at the position farthest from the effective area At least a part is formed of a plurality of conductive films separated by an interlayer insulating film and a conductive material electrically connecting the plurality of conductive films to each other.

By making the power supply lines multilayered as in the electro-optical device described above, the line width of one layer can be reduced compared to the case where the power supply lines are formed by only one wiring layer. Accordingly, not only sufficient current can be ensured, but also frame narrowing can be achieved.

The electro-optic device of the fifth aspect of the present invention is characterized in that it includes: a plurality of pixels including an electro-optic element having a functional layer sandwiched between a first electrode and a second electrode, provided in an active area on a substrate; The wiring for electrodes connected to the second electrode on the outside of the effective area; the wiring for connecting to the first electrode through an active element and provided at least on the effective area; The outer side is connected to the power line connected with the wiring for connection; and a plurality of the power lines are arranged outside the effective area, and among the power lines, the power line arranged at the position closest to the effective area is composed of A conductive film provided only in one wiring layer is formed.

The electro-optical device of the sixth aspect of the present invention is characterized in that it includes: a plurality of pixels including an electro-optical element having a functional layer sandwiched between a first electrode and a second electrode provided in an active area on a substrate; The wiring for electrodes connected to the second electrode on the outside of the effective area; the wiring for connecting to the first electrode through an active element and provided at least on the effective area; A power supply line connected to the connection wiring on the outside; and the line width of the connection wiring is different from that of the power supply line connected to the connection wiring.

In the active area, it is sometimes necessary to narrow the line width of the connection wiring for every pixel interval, but it is necessary to ensure a sufficient amount of current supplied to the pixels through the connection wiring. Therefore, in the electro-optical device, by making the line width of the power supply line larger than the line width of the connection wiring, it is possible to correspond to the pixel interval and ensure the amount of current.

The electro-optical device of the seventh aspect of the present invention is characterized in that it includes: a plurality of pixels including an electro-optical element having a functional layer sandwiched between a first electrode and a second electrode, provided in an active area on a substrate; The wiring for electrodes connected to the second electrode on the outside of the effective area; the wiring for connecting to the first electrode through an active element and provided at least on the effective area; A power supply line externally connected to the wiring for connection; and a line width of a first portion of the wiring for connection and a line width of a second portion of the wiring for connection are different from each other.

In the electro-optic device, the first part refers to, for example, the vicinity of a contact point where the connection wiring and the power supply line are connected among the connection wiring; the second part refers to, for example, the The first part is closer to the active area, or is located in a part of the active area. In this case, the line width of the first portion is preferably larger than the line width of the second portion. In this way, by providing portions having different line widths on the same wiring such as the above-mentioned connection wiring, it is possible to alleviate the electromotive force caused by the voltage drop or the resistance increase caused by the difference in the line width or material of the contact portion or the like. and destabilization.

The eighth electro-optical device of the present invention is characterized in that it includes: a plurality of pixels including an electro-optical element having a functional layer sandwiched between a first electrode and a second electrode, provided in an active area on a substrate; The wiring for electrodes connected to the second electrode on the outside of the effective area; the wiring for connecting connected to the first electrode through an active element and provided at least on the effective area; in the active area The outer side of the power line connected to the wiring for connection; and a plurality of wiring for connecting is provided, at least one of the wiring for connecting is made of a conductive wire provided in a plurality of different wiring layers. The film and the conductive material that connects the conductive films to each other.

In the effective area, it is preferable that the connection wirings are basically all provided on the same layer. In the vicinity of the contact portion of the connection wiring with the power line, there are a plurality of contact portions, so at least in the vicinity of the contact portion of the connection wiring with the power line, all of the connection wiring Wiring is arranged in the same layer, which is not good for efficient use of the limited space. Therefore, by configuring at least one of the connection wirings with different wiring layers like the electro-optical device, the above-mentioned two requirements can be satisfied.

The electro-optical device according to the ninth aspect of the present invention is characterized in that it includes: a plurality of pixels including an electro-optical element having a functional layer sandwiched between a first electrode and a second electrode provided in an active area on a substrate; The wiring for electrodes connected to the second electrode outside the effective area; the wiring for connecting connected to the first electrode through an active element and provided at least on the active area; in the active area and a first conductive film constituting at least a part of the electrode wiring is formed between the first conductive film constituting at least a part of the electrode wiring and the substrate. Two conductive films; the first conductive film and the second conductive film are separated from each other by an interlayer insulating film; at least a part of the first conductive film and at least a part of the second conductive film are overlapped and arranged part.

Like the above-mentioned electro-optic device, by laminating the power supply line and the electrode wiring through an interlayer insulating film, the frame area can be reduced. Furthermore, since capacitance can be formed between the power supply line and the electrode wiring, there is an effect of alleviating voltage fluctuations.

In the electro-optical device, it is preferable that the second conductive film is connected to the connection wiring through a contact portion provided on the interlayer insulating film.

In the electro-optic device, the functional layer may be composed of an organic electroluminescent material.

An electronic device according to the present invention includes the electro-optical device.

Description of drawings

The accompanying drawings are briefly described below.

FIG. 1 is a schematic plan view showing an embodiment of the present invention, that is, a wiring structure of a display device.

FIG. 2 is a schematic plan view of the display device of Example 1. FIG.

Fig. 3 is a sectional view taken along line A-A' in Fig. 2 .

FIG. 4 is an enlarged view of the cross-sectional view shown in FIG. 3 .

FIG. 5 is an enlarged view of the power supply lines and connection wiring to which the respective power supply lines are connected according to the first embodiment.

6( a ) to ( d ) are process diagrams illustrating a method of manufacturing a display device according to an embodiment of the present invention.

7( a ) to ( c ) are process diagrams illustrating a method of manufacturing a display device according to an embodiment of the present invention.

8( a ) to ( c ) are process diagrams illustrating a method of manufacturing a display device according to an embodiment of the present invention.

9( a ) to ( c ) are process diagrams illustrating a method of manufacturing a display device according to an embodiment of the present invention.

FIG. 10 is a schematic plan view of a display device of Example 2. FIG.

Fig. 11 is a sectional view taken along line A-A' of Fig. 10 .

FIG. 12 is an enlarged view of the power supply lines and the connection wiring to which the respective power supply lines are connected according to the second embodiment.

13 is a diagram showing an example of an electronic device having an organic EL display device, (a) is a perspective view of a mobile phone, (b) is a perspective view of a watch-type electronic device, and (c) is a perspective view of a portable information processing device.

In the figure, 1-display device (organic EL display device, electro-optical device); 2-substrate; 2a-active area (display area); 99R, 99G, 99B-wiring for connection; 103, 103R, 103G, 103B-power supply 110a-hole injection/transport layer; 110b-light-emitting layer; 111-pixel electrode (electrode); 135-first wiring layer (first layer); 136-second wiring layer ( second layer); 144a—first interlayer insulating film (insulating layer).

Detailed ways

Next, embodiments of the electro-optic device and electronic equipment of the present invention will be described with reference to FIGS. 1 to 10 . In each of the drawings shown below, the scales of the layers and members are different in order to make the layers and members recognizable in the drawings.

FIG. 1 is a schematic plan view showing the wiring structure of the electro-optical device of the present invention.

As shown in FIG. 1 , the display device (electro-optic device) 1 of this embodiment has a plurality of scanning lines 101 arranged respectively, a plurality of data lines 102 extending in a direction intersecting with the scanning lines 101, and a plurality of data lines 102 extending in parallel with the data lines 102. A plurality of connecting wires 99 are formed, and pixel regions A are provided corresponding to divisions formed by intersections of scanning lines 101 and data lines 102 .

A data-side drive circuit 104 including a shift register, a level shifter, a video line, an analog switch, and the like is connected to the data line 102 . Also, a scanning-side driver circuit 105 including a shift register and a level shifter is connected to the scanning line 101 . In each pixel area A, there is provided: a thin film transistor 112 for switching that supplies a scanning signal to the gate through the scanning line 101 and the like; ; The pixel signal held by the storage capacitor cap is provided as a voltage to the driving thin film transistor 123 of the gate; When electrically connected to the power supply wiring for light emission) 103, the pixel electrode (electrode) 111 that the driving current flows from the power supply wiring 103; the functional layer 110 sandwiched between the pixel electrode 111 and the common electrode (cathode 12). A light emitting element is formed by the pixel electrode 111, the common electrode 12 and the functional layer 110.

According to the relevant structure, when the scanning line 101 is driven and the switching thin film transistor 112 is turned on, the potential of the data line 102 is held at the storage capacitor cap at this time, and the driving thin film transistor 123 is determined according to the state of the storage capacitor cap. conduction state. And, through the channel of the thin film transistor 123 for driving, the current flows from the power supply line 103 to the pixel electrode 111 through the connection wiring 99 and the thin film transistor 123 , and then flows to the common electrode 12 through the functional layer 110 . The functional layer 110 emits light according to the amount of current flowing through it.

FIG. 2 shows a schematic plan view of the electro-optical device of this embodiment.

The substrate 2 is a transparent substrate such as glass, and is divided into a display area (electrode area) 2a located in the center of the substrate 2 and an inactive area 2b located around the substrate 2 outside the active area 2a. The active area 2a is an area formed by pixels R, G, and B having light-emitting elements arranged in a matrix, and is a display area that actually contributes to display. Pixel R, pixel G, and pixel B correspond to red, green, and blue pixels, respectively.

The common electrode wiring 12a connected to the common electrode 12 forms a U-shaped shape surrounding three of the four sides constituting the outer periphery of the active region 2a.

The power supply line 103 is provided between the active region 2a and the common electrode wiring 12a. Power supply line 103R, power supply line 103G, and power supply line 103B supply power supply voltage to pixel R, pixel G, and pixel B through connection wiring lines 99R, 99G, and 99B shown in FIG. 1, respectively.

Among the power supply lines 103R, 103G, and 103B, the power supply line 103B located farthest from the active area 2a has a double-wiring structure, and a contact hole 103B ₃ is provided for vertical conduction.

An inspection circuit 106 is provided between the power supply line 103R closest to the active area 2 a among the power supply lines 103 and the active area 2 a. The inspection circuit 106 is used to inspect the quality, defects, and the like of the display device during the manufacturing process and shipment.

A flexible substrate 5 having a driver IC 6 is mounted on one side of the substrate 2 opposite to the inspection circuit 106 with respect to the active region 2 a. The above-mentioned wiring 12a for common electrodes and the power supply line 103 are both connected to the driver IC 6 via the wiring 5a.

Starting from the side of the substrate 2 on which the flexible substrate 5 is mounted, in the direction opposite to the side of the substrate 2, between the active region 2a and the power supply line 103R, between the active region 2a and the power supply line 103G Scanning line driving circuits 105 are respectively provided in the areas between them. In the area between the scanning line driving circuit 105 and the power supply line 103R, and in the area between the scanning line driving circuit 105 and the power supply line 103G, a control driving circuit for supplying a control signal and a power supply voltage to the scanning line driving circuit 105 is provided. Control signal wiring 105a and drive circuit power supply wiring 105b.

Fig. 3 is a schematic cross-sectional view taken along line A-A' in Fig. 2 . As shown in FIG. 3 , an active element layer 14 is provided between a light-emitting element portion 11 composed of a light-emitting element and a bank portion provided corresponding to the active region 2a, and the substrate 2. 14 is provided with the aforementioned scanning lines, data lines, storage capacitors, switching thin film transistors 112, driving thin film transistors 123, and the like.

In addition, the power supply line 103 ( 103R, 103G, 103B) is arranged corresponding to the non-active region 2 b of the active element layer 14 . A part of the non-effective area 2b is used as a dummy area 2d. The dummy region 2d is mainly a region for stabilizing the ejection amount of the material forming the light emitting element before forming the light emitting element 110 by the inkjet process, and it can be said to be a region for trial spraying.

In the active element layer 14 below the dummy region 2d, the scanning-side driver circuit 105, the control signal wiring 105a for the driver circuit, and the power supply wiring 105b for the driver circuit are provided. Although not shown in FIG. 3 , a dummy region 2 d may be provided above the inspection circuit 106 .

The power supply line 103R is formed using a conductive film provided in the first wiring layer 135 . Also, the power supply line 103G is formed using a conductive film provided in the first wiring layer 135 . On the other hand, as described above, the power supply line 103B has a double wiring structure. Specifically, it is composed of a conductive film provided in the first wiring layer 135 and a conductive film provided in the second wiring layer 136 . Between the two conductive films, a first interlayer insulating film 144a is provided, and through a contact hole (corresponding to the contact hole _103B3 shown in FIG. 2 ) provided on the first interlayer insulating film 144a, the electrical The two conductive films are connected.

Specifically, the common electrode wiring 12 a is composed of a conductive film provided in the first wiring layer 135 and a conductive film provided in the second wiring layer 136 .

The upper part of the light emitting element part 11 is covered by the sealing part 3 . The sealing portion 3 is composed of a sealing resin 603 and a sealing substrate 604 provided on the active element layer 14 . The sealing resin 603 is composed of a thermosetting resin, an ultraviolet curable resin, or the like, and is particularly preferably composed of an epoxy resin that is one type of thermosetting resin. The sealing resin 603 is arranged along the outer periphery of the substrate, and is formed of, for example, a micro-dispenser or the like. The sealing resin 603 joins the active element layer 14 and the sealing substrate 604, so that water or oxygen is prevented from entering the space formed by the light emitting element portion 11 from between the active element layer 14 and the sealing substrate 604, and the common electrode 12 is prevented from Or deterioration of the light-emitting layer (not shown) formed in the light-emitting element portion 11 .

The sealing substrate 604 is made of, for example, glass, plastic, metal, or the like, and has a concave portion 604 a for accommodating the light emitting element portion 11 inside. In addition, a getter 605 for absorbing oxygen or the like is disposed in the concave portion 604 a, and can absorb water or oxygen entering the space formed by the sealing substrate 604 and the light emitting element portion 11 . It should be noted that the getter 605 can also be omitted.

Aluminum forming the common electrode 12 reflects light emitted from the light-emitting layer 110b to the substrate 2 side, and is preferably composed of an Ag film, a laminated film of Al and Ag, or the like in addition to the Al film. In addition, its thickness is preferably in the range of, for example, 100 to 1000 nm, and particularly preferably about 200 nm.

On the aluminum, a protective layer 15 made of SiO, SiO ₂ , SiN, etc. for protecting the common electrode 12 may also be provided.

The protective layer 15 covers the common electrode 12 and protects the connecting portion between the common electrode wiring 12 a and the common electrode 12 . In addition, the protective layer 15 extends below the sealing resin 603 and exists between the sealing resin 603 and the active element layer 14 .

FIG. 4 shows an enlarged view of a cross-sectional structure of a display region of a display device. In this FIG. 4 , three pixel regions A are illustrated. The display device 1 has a structure in which an active element layer 14 in which circuits such as TFTs are formed and a light emitting element portion 11 in which a functional layer 110 is formed are laminated in this order on a substrate 2 .

In this display device 1, the light emitted from the functional layer 110 to the substrate 2 side passes through the active element layer 14 and the substrate 2, and is emitted to the lower side of the substrate 2 (on the observer's side). The light emitted from the layer 110 to the opposite side of the substrate 2 is reflected by the common electrode 12 , passes through the active element layer 14 and the substrate 2 , and exits to the bottom of the substrate 2 (observer side). It should be noted that by using a transparent material as the common electrode 12, light emitted from the common electrode side can be emitted. As a transparent material, for example, ITO, Pt, Ir, Ni or Pd can be used. The film thickness is preferably about 75 nm, and more preferably thinner than the film thickness.

In the active element layer 14, an underlying protective film 2c made of a silicon oxide thin film or the like is formed on the substrate 2, and an island-shaped semiconductor film 141 made of polysilicon is formed on the underlying protective film 2c. It should be noted that the drain region 141 a and the source region 141 b are formed on the semiconductor film 141 by implanting high-concentration B ions. It should be noted that the portion where B is not introduced becomes the channel region 141c.

In the active element layer 14, a transparent gate insulating film 142 covering the underlying protective film 2c and the semiconductor film 141 is formed, and a gate electrode composed of Al, Mo, Ta, Ti, W, etc. is formed on the gate insulating film 142. 143 (scanning line 101 ), a transparent first interlayer insulating film 144 a and a second interlayer insulating film 144 b are formed on the gate electrode 143 and the gate insulating film 142 . The gate electrode 143 is provided at a position corresponding to the channel region 141c of the semiconductor film 141 .

In addition, contact holes 145 and 146 are formed through the first and second interlayer insulating films 144a and 144b to connect the drain and source regions 141a and 141b of the semiconductor film 141, respectively. Furthermore, on the second interlayer insulating film 144b, a transparent pixel electrode 111 made of ITO or the like is patterned into a predetermined shape, and the drain region 141a is connected to the pixel electrode 111 through a contact hole 145 . In addition, the source region 141b is connected to the connection wiring 99 through the contact hole 146 . Thus, in the active element layer 14, the driving thin film transistor 123 connected to each pixel electrode 111 is formed. It should be noted that the aforementioned storage capacitor cap and the switching thin film transistor 112 are formed in the active element layer 14 , but their illustration is omitted in FIG. 4 .

Next, as shown in FIG. 4 , the light-emitting element portion 11 is mainly composed of a functional layer 110 stacked on a plurality of pixel electrodes 111, a partition wall portion 112 dividing each functional layer 110, and a common electrode 12 formed on the functional layer 110. constitute. These pixel electrodes 111, functional layer 110, and common electrode 12 constitute a light emitting element. Here, the pixel electrode 111 is formed of, for example, ITO, and its pattern is substantially rectangular in plan view. The thickness of the pixel electrode 111 is preferably in the range of 50 to 200 nm, particularly preferably about 150 nm. The barrier rib portion 112 is formed by laminating an inorganic barrier rib layer 112 a on the substrate 2 side and an organic barrier rib layer 112 b away from the substrate 2 .

The inorganic barrier rib layer 112a and the organic barrier rib layer 112b are formed so as to be located on the peripheral portion of the pixel electrode 111 . Planarly, the periphery of the pixel electrode 111 and the inorganic barrier rib layer 112a are arranged so as to overlap in a plane. In addition, the organic partition wall layer 112b is similarly arranged so as to overlap a part of the pixel electrode 111 in plan. In addition, the inorganic barrier rib layer 112a is formed closer to the center side of the pixel electrode 111 than the organic barrier rib layer 112b. In this way, by forming each first lamination portion 112e of the inorganic barrier rib layer 112a inside the pixel electrode 111, the lower opening 112c corresponding to the formation position of the pixel electrode 111 is provided.

In addition, an upper opening 112d is formed in the organic barrier rib layer 112b.

The upper opening 112d is provided so as to correspond to the formation position of the pixel electrode 111 and the lower opening 112c. As shown in FIG. 4 , the upper opening 112 d is formed wider than the lower opening 112 c and narrower than the pixel electrode 111 . In addition, the upper position of the upper opening 112 d may be formed at substantially the same position as the end of the pixel electrode 111 . At this time, as shown in FIG. 4 , the cross section of the upper opening 112 d of the organic barrier rib layer 112 b becomes inclined.

In addition, the inorganic barrier rib layer 112a is preferably formed of an inorganic material such as SiO ₂ or TiO ₂ . The film thickness of the inorganic barrier rib layer 112a is preferably 50 to 200 nm, particularly preferably 150 nm.

The organic barrier rib layer 112b is formed of a material having heat resistance and solvent resistance, such as acrylic resin and polyimide resin. The thickness of the organic barrier layer 112b is desirably in the range of 0.1 to 3.5 μm. If the thickness of the organic barrier rib layer 112b is more than 2 μm, the signal wiring for supplying signals, such as the data line 102 or the scanning line 101, can be sufficiently separated from the common electrode 12, so the friction generated between the signal wiring and the common electrode 12 can be reduced. Parasitic capacitance, which can alleviate problems such as signal delay and passivation.

In addition, a lyophilic region and a lyophobic region are formed in the partition wall portion 112 . The regions exhibiting lyophilicity are the first laminated portion 112e of the inorganic barrier rib layer 112a and the electrode surface 111a of the pixel electrode 111, and the surfaces of these regions are treated to be lyophilic by plasma treatment using oxygen as a processing gas. The region exhibiting lyophobicity is the wall surface of the upper opening 112d and the upper surface 112f of the organic partition wall layer 112, and these regions are subjected to fluorination treatment (treated to be lyophobic) by plasma treatment using tetrafluoromethane as a precursor. ). It should be noted that the organic barrier layer may be formed of a material containing fluoropolymer.

The functional layer 110 is composed of a hole injection/transport layer 110a stacked on the pixel electrode 111 and a light emitting layer 110b made of an organic electroluminescent material formed adjacent to the hole injection/transport layer 110a. It should be noted that other functional layers having functions such as an electron injection and transport layer may also be formed adjacent to the light emitting layer 110b.

The hole injection/transport layer 110a has a function of injecting holes into the light emitting layer 110b, and has a function of transporting holes inside the hole injection/transport layer 110a. By providing such a hole injection/transport layer 110a between the pixel electrode 111 and the light-emitting layer 110b, device characteristics such as luminous efficiency and lifetime of the light-emitting layer 110b are improved. In addition, in the light emitting layer 110b, holes injected from the hole injection/transport layer 110a and electrons injected from the common electrode 12 are recombined in the light emitting layer to realize light emission.

The hole injection/transport layer 110a consists of a flat portion 110a1 located in the lower opening 112c and formed on the pixel electrode surface 111a, and a flat portion 112e formed in the upper opening 112d and formed on the inorganic barrier rib layer 112. Peripheral portion 110a2 constitutes. In addition, depending on the structure, the hole injection/transport layer 110a is formed only on the pixel electrode 111, and between the inorganic barrier rib layers 110a (the lower opening 110c) (there is also a form in which it is formed only on the above-mentioned flat portion). . The flat portion 110a1 has a constant thickness, for example, formed in a range of 50 to 70 nm.

When the peripheral portion 110a2 is formed, the peripheral portion 110a2 is located on the first laminated portion 112e and is in close contact with the organic barrier layer 112b which is the wall surface of the upper opening 112d. In addition, the thickness of the peripheral portion 110a2 is thinner near the electrode surface 111a, increases in the direction away from the electrode surface 111a, and becomes thickest near the wall surface of the upper opening 112d.

The reason why the peripheral portion 110a2 exhibits the above-mentioned shape is because the hole injection/transport layer 110a is removed after ejecting the first composition including the material for forming the hole injection/transport layer and a polar solvent into the opening 112. formed by a polar solvent, and the volatilization of the polar solvent mainly occurs on the first laminated part 112e of the inorganic barrier layer, and the forming material of the hole injection/transport layer is intensively concentrated and precipitated on the first laminated part 112e. .

In addition, the light emitting layer 110b is formed across the flat portion 110a1 and the peripheral portion 110a2 of the hole injection/transport layer 110a, and the thickness on the flat portion 110a1 is in the range of 50 to 80 nm. The light emitting layer 110b has three types: a red light emitting layer 110b1 that emits red light (R), a green light emitting layer 110b2 that emits green light (G), and a blue light emitting layer 110b3 that emits blue light (B). The light emitting layers 110b1 to 110b3 are stripes. configuration. It should be noted that, as a material for forming the hole injection/transport layer, for example, a mixture of polythiophene derivatives such as polyethylenedioxythiophene and polystyrenesulfonic acid can be used. In addition, as the material of the light-emitting layer 110b, polyfluorene derivatives, polyphenylene derivatives, polyvinylcarbazole, polythiophene derivatives can be used, or these polymer materials can be doped with perylene dyes, Coumarin pigments, rhodamine pigments, such as rubrene, perylene, 9, 10-biphenylanthracene, tetraphenylbutadiene, Nile red, coumarin 6, quinacridone, etc. And use.

The common electrode 12 is formed on the entire surface of the light-emitting element portion 11 , is paired with the pixel electrode 111 , and fulfills the role of allowing current to flow through the functional layer 110 . When the common electrode 12 is a cathode, for example, it may be formed by stacking metal layers such as calcium layers or aluminum layers. At this time, it is better to provide a cathode with a low work function on the side close to the light-emitting layer, especially in this embodiment, directly adjacent to the light-emitting layer 110b to complete the task of injecting electrons into the light-emitting layer 110b. In addition, since lithium fluoride can emit light efficiently depending on the material of the light emitting layer, LiF may be formed between the light emitting layer 110 and the common electrode 12 .

It should be noted that the red and green light emitting layers 110b1, 110b2 are not limited to lithium fluoride, other materials can also be used. Therefore, at this time, a layer made of lithium fluoride is formed only for the blue (B) light emitting layer 110b3, and materials other than lithium fluoride may be laminated for the other red and green light emitting layers 110b1 and 110b2. In addition, lithium fluoride is not formed on the red and green light-emitting layers 110b1 and 110b2, and only calcium may be formed. It should be noted that the thickness of lithium fluoride is, for example, preferably in the range of 2 to 5 nm, particularly preferably about 2 nm. In addition, the thickness of calcium is, for example, preferably in the range of 2 to 50 nm, particularly preferably about 20 nm.

FIG. 5 is an enlarged view of power supply lines 103R, 103G, and 103B and connection wirings 99R, 99G, and 99B connected to the respective power supply lines in the upper region of the active area 2 a. The connection wirings 99R, 99G, and 99B are formed by conductive films formed in the first wiring layer 135 and the second wiring layer 136. The connection wiring 99R is made of a conductive film provided on the first wiring layer 135 , and the connection wiring 99B connected to the power supply line 103B located farthest from the active region 2 a is made of a conductive film provided on the second wiring layer 136 . conductive film formation. The connection wiring 99G connected to the power supply line 103G sandwiched between the power supply line 103R and the power supply line 103B is connected to the power supply line 103G at a contact 100G penetrating through the first interlayer insulating film 114 a. At this contact 100G, conduction between the conductive film provided in the first wiring layer 135 and the conductive film provided in the second wiring layer 136 is ensured.

In this embodiment, since the connection wirings 99R, 99G, and 99B are formed by the first wiring layer 135 and the second wiring layer 136 , it is possible to eliminate as much as possible a contact portion such as 100G. In this way, by reducing the number of contact points, problems such as disconnection can be reduced.

The connection wirings 99R, 99G, and 99B extend substantially parallel to the active region 2 a, and at least some of the connection wirings 99R, 99G, and 99B have different widths. This is because in order to stably supply the power supply voltage, while ensuring a sufficient line width of the connection wiring 99R, 99G, 99B, and the power supply line 103R, 103G, 103B, the connection wiring is adapted to the pixel interval of the effective area 2a. The respective line widths of 99R, 99G, and 99B are narrowed.

It should be noted that, as shown in FIG. 3, it is desirable that in the effective region 2a, the connection wirings 99R, 99G, and 99B are basically formed using a conductive film located in the same wiring layer. In this embodiment, using A conductive film provided in the second wiring layer 136 is formed. On the other hand, the connection wiring 99R is formed by the first wiring layer 135 near the contact portion with the power supply line 103R as shown in FIG. In the region, it is necessary to perform connection from the conductive film provided on the first wiring layer 135 to the conductive film provided on the second wiring layer 136 .

Next, a method of manufacturing the display device of this embodiment will be described with reference to the drawings.

First, a method for forming the active element layer 14 on the substrate 2 will be described with reference to FIGS. 6 to 8 . It should be noted that each cross-sectional view shown in FIGS. 6 to 8 corresponds to a cross-section along line A-A' in FIG. 2 . It should be noted that in the following description, the impurity concentration is expressed as the impurity after the activation annealing.

First, as shown in FIG. 6(a), an underlying protective film 2c made of a silicon oxide film or the like is formed on a substrate 2. As shown in FIG. Next, after forming an amorphous silicon layer using ICVD, plasma CVD, or the like, crystal grains are grown by laser annealing or rapid heating to form polycrystalline silicon layer 501 .

Next, as shown in FIG. 6(b), the polysilicon layer 501 is patterned by photolithography to form island-shaped silicon layers 241, 251, and 261, and then a gate insulating film 142 made of silicon oxide film is formed.

The silicon layer 241 is formed at a position corresponding to the active region 2a, and constitutes the thin film transistor 123 (hereinafter, sometimes referred to as "pixel TFT") connected to the pixel electrode 111, and the silicon layers 251 and 261 constitute the scanning line driving circuit 105, respectively. P-channel type and N-channel type thin film transistors (hereinafter sometimes referred to as "driver circuit TFT").

The gate insulating layer 142 is formed by forming a silicon oxide thin film with a thickness of about 30 nm to 200 nm covering each of the silicon layers 241 , 251 , 261 and the underlying protective film 2 c by plasma CVD, thermal oxidation, or the like. Here, when the gate insulating layer 142 is formed by the thermal oxidation method, the crystallization of the silicon layers 241, 251, and 261 also proceeds, and these silicon layers can be made into polysilicon layers. When channel doping is performed, for example at this time, boron ions are implanted at a dose of about 1×10 12 cm ⁻² . As a result, the silicon layers 241, 251, and 261 are low-concentration P-type silicon layers having an impurity concentration of approximately 1×10 17 cm ⁻³ .

Next, as shown in FIG. 6(c), an ion implantation selection mask M1 is formed on a part of the silicon layers 241, 261, and in this state, phosphorus ions are ion-implanted at a dose of about 1×1015 cm ⁻² . As a result, high-concentration impurities are self-aligned into ion implantation selective mask M1, and high-concentration source regions 241S and 261S and high-concentration drain regions 241D and 261D are formed in silicon layers 241 and 261 .

Next, as shown in FIG. 6(d), after the ion implantation selection mask M1 is removed, doped silicon, a silicide film, or an aluminum film and a chromium film are formed on the gate insulating film 142 as the first wiring layer 135. A metal film with a thickness of about 500nm such as a tantalum film is patterned to form the gate 252 of the P-channel drive circuit TFT, the gate 242 of the pixel TFT, and the N-channel drive circuit. The gate 262 of the TFT is used. In addition, through the patterning described above, the control signal wiring 105a for scanning line driving circuit, the power supply lines 103R, 103G, and 103B, the wiring for connection 99R, and a part of the wiring for common electrodes 12a are simultaneously formed.

Using the gate electrodes 242, 252, 262 as masks, the silicon layers 241, 251, 261 are implanted with ions at a doping amount of about 4×1013 cm ⁻² . As a result, low-concentration impurities are automatically adjusted and introduced into the gates 242, 252, and 262, and low-concentration source regions 241b and 261b and low-concentration drain regions 241c are formed in silicon layers 241 and 261 and 261c. In addition, low-concentration impurity regions 251S and 251D are formed in the silicon layer 251 .

Next, as shown in FIG. 7( a ), an ion implantation selective mask M2 is formed on the entire surface except the periphery of the gate electrode 252 . Using this ion implantation selective mask M2, the silicon layer 251 is implanted with ions at a doping amount of 1.5×10 15 cm ⁻² . As a result, the gate electrode 252 also functions as a mask, and the silicon layer 252 is automatically doped with a high concentration of impurities. As a result, 251S and 251D are counter-doped, and become the source region and the drain region of the P-channel type driving electrologging TFT.

Next, as shown in FIG. 7(b), after removing the ion implantation selective mask M2, a first interlayer insulating film 144a is formed on the entire surface of the substrate 2, and then the first interlayer insulating film 144a is formed by photolithography. The film 144a is patterned, and holes H1 for forming contact holes are provided at positions corresponding to the source and drain electrodes of each TFT and the common electrode wiring 12a.

As shown in FIG. 7( c), by covering the first interlayer insulating film 144a, a conductive layer 504 made of metals such as aluminum, chromium, and tantalum with a thickness of about 200nm to 800nm is formed, and these metals are embedded in the previously formed hole H1, Form contact holes. In addition, a patterning mask M3 is formed on the conductive layer 504 .

Next, as shown in FIG. 8( a), the conductive layer 504 is patterned by the patterning mask M3 to form the source electrodes 243, 253, 263 of each TFT, the drain electrodes 244 and 254, the power supply line 103B, the connection wiring 99G, 99B, the power supply wiring 105b for the scanning line circuit and the wiring 12a for the common electrode serve as the second wiring layer 136 .

Next, as shown in FIG. 8( b ), a second interlayer insulating film 144 b covering the first interlayer insulating film 144 a is formed of a resin material such as acrylic. The second interlayer insulating film 144b is preferably formed to have a thickness of about 1 to 2 μm.

Next, as shown in FIG. 8(c), a portion of the second interlayer insulating film 144b corresponding to the drain electrode 244 of the pixel TFT is removed by etching to form a hole H2 for forming a contact hole. At this time, the second interlayer insulating film 144b on the common electrode wiring 12a is also removed at the same time. Thus, the active element layer 14 is formed on the substrate 2 .

Next, the procedure for obtaining the display device 1 by forming the light emitting element portion 11 on the active element layer 14 will be described with reference to FIG. 9 . The sectional view shown in FIG. 9 corresponds to a section taken along line A-A' in FIG. 2 .

First, as shown in FIG. 9(a), a thin film made of a transparent electrode material such as ITO is formed covering the entire surface of the substrate 2. By patterning the thin film, holes H2 provided in the second interlayer insulating film 144b are embedded. A contact hole 111a is formed, and a pixel electrode 111 and a dummy pixel electrode 111' are formed. The pixel electrode 111 is formed only on the portion where the thin film transistor 123 is formed, and is connected to the current thin film transistor 123 (switching element) through the contact hole 111a. It should be noted that the dummy electrodes 111' are configured in an island shape.

Then, as shown in FIG. 9(b), an inorganic bank layer 112a and a dummy inorganic bank layer 212a are formed on the second interlayer insulating film 144b, the pixel electrode 111, and the dummy electrode 111'. The inorganic barrier rib layer 112a is formed in a form in which a part of the pixel electrode 111 is opened, and completely covers the dummy pixel electrode 111' to form a dummy inorganic barrier rib layer 212a. For example, by CVD method, TEOS method, sputtering method, vapor deposition method, etc., after forming an inorganic material film such as SiO ₂ , TiO ₂ , SiN, etc. on the entire surface of the second interlayer insulating film 144b and the pixel electrode 111, by This inorganic material film is patterned to form the inorganic material barrier rib layer 112a and the dummy inorganic material barrier rib layer 212a.

As shown in FIG. 9( b ), the organic barrier rib layer 112 b and the dummy organic barrier rib layer 212 b are formed on the inorganic barrier rib layer 112 a and the dummy inorganic barrier rib layer 212 a. The organic barrier rib layer 112b is formed so that part of the pixel electrode 111 is opened through the inorganic barrier rib layer 112a, and the dummy organic barrier rib layer 212b is formed so that a part of the dummy inorganic barrier rib layer 212a is opened. In this way, partition walls 112 are formed on second interlayer insulating film 144b.

Next, a lyophilic region and a lyophobic region are formed on the surface of the partition wall 112 . In this embodiment, each region is formed by a plasma processing step. Specifically, this plasma treatment process includes at least a lyophilic step of making the pixel electrode 111, the inorganic barrier rib layer 112a, and the dummy inorganic barrier rib layer 212a lyophilic, and making the organic barrier rib layer 112b and the dummy organic barrier rib layer 212b A lyophobic step that becomes lyophobic.

That is, the partition wall 112 is heated to a predetermined temperature (for example, about 70 to 80° C.), and then, as a lyophilic step, plasma treatment (O ₂ plasma treatment) using oxygen as a reactive gas is performed in an air environment. Then, as a lyophobic step, plasma treatment ( _CF4 plasma treatment) using tetrafluoromethane as a reactive gas is carried out in the air environment, and the partition wall 112 heated for the plasma treatment is cooled to room temperature, so that the given Positioning imparts lyophilicity and lyophobicity.

The functional layer 110 and the dummy functional layer 210 are respectively formed on the pixel electrode 111 and the inorganic partition wall layer 212a by an inkjet method. The functional layer 110 and the dummy functional layer 210 are formed by ejecting and drying the composition ink containing the material for the hole injection/transporting layer, and then discharging and drying the composition ink containing the material for the light emitting layer. It should be noted that, after the formation process of the functional layer 110 and the dummy functional layer 210, in order to prevent oxidation of the hole injection/transport layer and the light emitting layer, it is desirable to carry out in an inert gas atmosphere such as a nitrogen atmosphere or an argon atmosphere. .

Next, as shown in FIG. 9( c ), the common electrode 12 covering the partition wall 112 , the functional layer 110 and the dummy function 210 is formed. After forming the first common electrode layer 12b on the partition wall 112, the functional layer 110 and the dummy function 210, the second common electrode layer 12c connected to the common electrode wiring 12a on the substrate 2 is formed by covering the first common electrode layer 12b. , so as to obtain the common electrode 12 .

Finally, a sealing resin 603 such as epoxy resin is applied on the substrate 2 , and a sealing substrate 604 is bonded to the substrate 2 through the sealing resin 603 . In this way, the display device 1 shown in FIGS. 1 to 3 is obtained.

In this way, since the power supply line 103B on the outermost side of the active area 2a does not overlap with the connection wiring 99R, 99G connecting the other power supply lines 103R, 103G on a plane, it is possible to connect the first wiring layer 135 and the second wiring layer. 136 set on both sides. Therefore, in this embodiment, compared with the case where the power supply line 103B is provided in any one of the first wiring layer 135 and the second wiring layer 136, it can be formed with a width nearly half, and the width of the power supply line 103B The reduced portion can reduce the frame of the panel.

In addition, the connection wiring 99R connected to the innermost power supply line 103R with respect to the active region 2 a can be formed on the first wiring layer 135 because it does not planarly overlap the other power supply lines 103G and 103B. Therefore, in this embodiment, the width of the connection wiring 99G, 99B provided on the second wiring layer 136 can be increased by a portion corresponding to the width of the connection wiring 99R. Manufacturing made easy. In this embodiment, the contact point for electrically connecting the power supply line and the connection wiring is only one 100G, so that the dependence of the contact resistance can be reduced.

[Example 2]

Next, Example 2 will be described. The main difference between the layout of the display device of Example 2 shown in FIG. 10 and the layout of Example 1 shown in FIG. At least some of , 103G, 103B overlap in plan view. The common electrode wiring 12a extends from the side on which the flexible substrate 5 is mounted to the side opposite to the side, and is respectively provided between two sides facing each other among the four sides constituting the outer periphery of the substrate 2 and the active region 2a, One common electrode wiring 12a is arranged to overlap the power supply line 103R, and the other common electrode wiring 12a is arranged to overlap at least a part of 103G and 103B.

FIG. 11 shows a sectional view corresponding to this. The common electrode wiring 12 a is made of a conductive film provided on the second wiring layer 136 and is connected to the common electrode 12 .

The power supply lines 103R, 103G, 103B are formed by a conductive film provided on the first wiring layer 135 below the second wiring layer 136 . The common electrode wiring 12a and the power supply lines 103R, 103G, and 103B are separated and electrically insulated by the first interlayer insulating film 144a. A conductive layer 12d made of ITO or the like is interposed between the common electrode wiring 12a and the common electrode 12 .

As described above, the common electrode wiring 12a is formed so as to overlap at least a part of the power supply lines 103R, 103G, and 103B, whereby capacitance is formed between the common electrode wiring 12a and the power supply lines 103R, 103G, and 103B, thereby relaxing the power supply voltage. The change of the electro-optic element makes it possible to drive stably.

The power supply lines 103R, 103G, 103B are in the area between the active area 2a and the side opposite to the side on which the flexible substrate is mounted, as shown in FIG. 99G, 99B. In the contacts 100R, 100G, and 100B, the conductive film provided on the first wiring layer 135 and the conductive film provided on the second wiring layer 136 are connected. The connection wirings 99R, 99G, and 99B are formed using a conductive film provided on the second wiring layer 136 . The line widths of the connection wiring lines 99R, 99G, and 99B are smaller than those of the corresponding power supply lines 103R, 103G, and 103B.

It should be noted that, as described above, ideally, in the effective region 2a, the connection wirings 99R, 99G, and 99B are basically formed using a conductive film that is all located in the same wiring layer. A conductive film is formed on the second wiring layer 136 . On the other hand, the connection wirings 99R, 99G, and 99B are formed using a conductive film provided on the second wiring layer 136 . Therefore, unlike the case shown in FIG. 5 , in the region between the contact portion and the active region 2a, the connection wirings 99R, 99G, and 99B do not need to be formed from the conductive film provided on the first wiring layer 135 to the one provided on the first wiring layer 135. Connection of the conductive film on the second wiring layer 136 .

Next, an example of electronic equipment including the display device 1 of the embodiment will be described.

Fig. 13(a) is a perspective view showing an example of a mobile phone. In FIG. 10( a ), reference numeral 1000 denotes a mobile phone main body, and reference numeral 1001 denotes a display portion using the organic EL device 1 .

Fig. 13(b) is a perspective view showing an example of a watch-type electronic device. In FIG. 10( b ), reference numeral 1100 denotes a watch main body, and reference numeral 1101 denotes a display portion using the organic EL device 1 .

Fig. 13(c) is a perspective view showing an example of a portable information processing device such as a word processor and a personal computer. In FIG. 13( c ), reference numeral 1200 denotes an information processing device, reference numeral 1202 denotes an input unit such as a keyboard, reference numeral 1204 denotes a main body of an information processing device, and reference numeral 1206 denotes a display unit using the organic EL device 1 .

It should be noted that the technical scope of the present invention is not limited to the above-described examples, and various changes can be made within the scope not departing from the gist of the present invention.

For example, in the above-mentioned embodiment, the power supply line 103B has a two-layer structure, but if it is the power supply line arranged on the outermost side with respect to the active area 2a, it may be another power supply line. In addition, the arrangement of the power supply line, connection wiring, and the like provided on the first wiring layer 135 and the second wiring layer 136 may be reversed.

In addition, in the above-described embodiment, as the structure of the light-emitting element portion 11, the pixel electrode 111, the hole injection/transport layer 110a, the light-emitting layer 110b, and the common electrode 12 are formed in order from the substrate 2 side, However, it is not limited to this, and a structure arranged in the reverse order may also be employed. In the above-described embodiment, an example in which light emitted from the light emitting element portion 11 passes through the transparent substrate 2 and is emitted to the outside side has been described. One side, in the form of injection through the sealing part 3. In this case, it is sufficient to provide a common electrode and a sealing layer having the above-mentioned excellent light transmission properties (transparency).

In addition, in the above-mentioned embodiments, the case where the light-emitting layers of R, G, and B are arranged in stripes has been described, but the present invention is not limited thereto, and various arrangement structures can be adopted. For example, in addition to the striped configuration, mosaic and triangular configurations are also possible.

As described above, in the present invention, it is possible to obtain a compact and easy-to-manufacture high-quality electro-optical device and electronic equipment that achieve a narrow frame.

It should be noted that the present embodiment described above shows one form of the present invention, and does not limit the present invention, and can be changed arbitrarily within the scope of the technical idea of the present invention.

Claims (4)

1. An electro-optical device, the first electrode has a first electrode area arranged in a matrix on the substrate, and a power supply wiring for light emission connected to the first electrode is arranged around the first electrode area, and a wiring for a second electrode connected to a second electrode with a functional layer sandwiched between the first electrode and the functional layer having at least a light emitting layer, and the electro-optic device is characterized in that the power supply wiring for light emission and The wiring for the second electrodes is arranged such that at least a part thereof overlaps with each other in plan view. 2. The electro-optic device according to claim 1, wherein an interlayer insulating film is disposed between the light-emitting power supply wiring and the second electrode wiring. 3. The electro-optical device according to claim 1 or 2, wherein any one of the light-emitting power supply wiring and the second electrode wiring is arranged in an area occupied by the other. 4. An electronic instrument, characterized in that it has the electro-optic device according to any one of claims 1 to 3.

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