CN100353274C - A device for encrypting and protecting a program with a protection bit code - Google Patents

Abstract

The invention provides a device for encrypting and protecting a program by using a protection bit code, wherein the program comprises a plurality of instructions P (P is a positive integer), and the device comprises a protection bit code generating device, a first protection bit code position generating device and a protection bit code inserting device. The protection bit code generating device generates a plurality of protection bit codes according to a plurality of instructions of the program, wherein the plurality of instructions have a plurality of bits I (I is a positive integer); the first protection bit code position generating device generates a plurality of inserting positions N (N is a positive integer) of the plurality of protection bit codes according to the processor state when the program is executed; the protection bit code inserting device inserts the plurality of protection bit codes into the N-1 th bit and the N-th bit of the plurality of instructions of the program respectively according to the inserting position N generated by the first protection bit code position generating device to generate an encrypted program.

Description

A device for encrypting and protecting a program with a protected bit code

technical field

The invention relates to processor data protection technology, in particular to a device for encrypting and protecting a program with protection bit codes.

Background technique

In this era where intellectual property rights are valued, in order to protect the intellectual property related to the programs and data developed by the manufacturers, they will first encrypt the data and programs when they are offline (off-line), and then encrypt them. The encrypted data is stored in a non-volatile storage or other storage media. Even if others get the non-volatile storage or other storage media with the encrypted data, since they cannot know the encryption process and processing method, It is also impossible to restore the data and programs correctly, so as to achieve the purpose of protection.

For this kind of data protection method, in; USP6,408,073 patent announcement, use a virtual random number generator (Pseudo Random Generator) and according to an initial value (seed1/seed2), come to read-only memory (Read Only Memory) , ROM) to encode the data (ROMdata) to generate encoded data (Encoded data), but this data protection method requires a synchronous random number generator for decoding due to the use of random numbers as encryption parameters. A lot of random number patterns are needed to effectively prevent others from restoring the data and programs, which means that the virtual random number generator for encoding and decoding requires a rather complicated circuit, which will increase a lot of cost. If a virtual random number generator with simpler encoding and decoding is used, although it can save costs, it is easy to restore the data and programs by others. Therefore, the design of the conditional instruction processing method of the known processor still has many deficiencies and has been improved. necessary.

Contents of the invention

The purpose of the present invention is to provide a device for encrypting and protecting a program with a protection bit code, so as to avoid the use of a complicated virtual random number generator in the known technology and achieve the purpose of saving costs. At the same time, since the generation and removal of the protection bit code is relatively simple, the encryption processing time is reduced and the overall system efficiency is improved.

According to a feature of the present invention, a device for encrypting and protecting a program with a protection bit code is proposed. The program has a plurality of instructions, and each instruction has I bits, and the I is a positive integer. The device includes:

A protection bit code generating device, according to the plurality of instructions of the program to generate a corresponding plurality of protection bit codes, each protection bit code has P bits, and the P is a positive integer;

A first protected bit code position generating device, which generates the insertion position N of each protected bit code according to the state of the processor when executing the program, where N is a positive integer, wherein the first protected bit code position is generated The device contains:

a location status register, used to instruct the processor to access data segments or access program segments;

a program state register, used to indicate the state of the processor;

a plurality of insertion position generating devices to generate insertion positions according to their predetermined functions; and

A multiplexer, which has a plurality of input terminals to be coupled to the output terminals of the plurality of insertion position generating devices, and selects one of the plurality of input terminals according to the position state register and the program state register insert position as output; and

A protection bit code insertion device, according to the insertion position N generated by the first protection bit code position generating device, respectively inserts each protection bit code into the N-1th bit and the Nth bit of the corresponding instruction of the program Among them, an encryption program is generated.

According to another feature of the present invention, a device for decrypting an encrypted program is proposed. The encrypted program is encrypted by inserting a protection bit code into the original program. The encrypted program has multiple instructions. The device includes:

A second protection bit code position generation device, which generates the insertion positions of the plurality of protection bit codes according to the state of the processor when executing the program, wherein the second protection bit code position generation device includes:

a location status register, used to instruct the processor to access data segments or access program segments;

a program status register, used to indicate the status of the processor;

a plurality of insertion position generating devices to generate insertion positions according to their predetermined functions; and

A multiplexer, which has a plurality of input terminals to be coupled to the output terminals of the plurality of insertion position generating devices, and selects one of the plurality of input terminals according to the position state register and the program state register insert position as output; and

A protection bit code removal device inputs the program, and removes the Nth bit of the corresponding instruction of the program according to the insertion position N generated by the second protection bit code position generation device.

According to another feature of the present invention, a device for decrypting an encrypted program is proposed. The encrypted program inserts two sets of protection bit codes into the original program for encryption. The encrypted program has multiple instructions, one of which is Can contain two encryption instructions, the device contains:

A third protected bit code position generating device, which generates the third insertion position of the plurality of protected bit codes according to the state of the processor when executing the program, wherein the third protected bit code position generating device includes:

a location status register, used to instruct the processor to access data segments or access program segments;

a program status register, used to indicate the status of the processor;

a plurality of insertion position generating devices to generate insertion positions according to their predetermined functions; and

A multiplexer, which has a plurality of input terminals to be coupled to the output terminals of the plurality of insertion position generating devices, and selects one of the plurality of input terminals according to the position state register and the program state register insert position as output;

A fourth protection bit code position generation device, which generates the fourth insertion position of the plurality of protection bit codes according to the state of the processor when executing the program, wherein the fourth protection bit code position generation device includes:

a location status register, used to instruct the processor to access data segments or access program segments;

a program status register, used to indicate the status of the processor;

a plurality of insertion position generating devices to generate insertion positions according to their predetermined functions; and

A multiplexer, which has a plurality of input terminals to be coupled to the output terminals of the plurality of insertion position generating devices, and selects one of the plurality of input terminals according to the position state register and the program state register insert position as output; and

A third protection bit code removing device, input the low half word group of the encryption program, and according to the third insertion position N1 generated by the third protection bit code position generating device, to correspond the program to the first bit of the instruction the removal of the N1-th bit from bit 0 to bit K-1; and

A fourth protection bit code removal device, input the upper half word group of the encrypted program, and according to the fourth insertion position N2 produced by the fourth protection bit code position generating device, to correspond the program to the Kth instruction The N2th bit of bits to 2K-1 bits is removed.

According to another characteristic of the present invention, a method for encrypting and protecting a program with a protection bit code is proposed, the program has a plurality of instructions, each instruction has I bits, and the I is a positive integer, the method includes the following step:

A protection bit code generating step, generating a plurality of corresponding protection bit codes according to the plurality of instructions of the program, each protection bit code has P bits, and the P is a positive integer;

A first protection bit code position generating step, which generates the insertion position N of each protection bit code according to the state of the processor when executing the program, where N is a positive integer, wherein a position status flag is used to indicate the processing The device accesses the data segment or accesses the program segment, and a program status flag is used to indicate the status of the processor. The step of generating the first protection bit code position also includes the following steps:

a plurality of insertion position generating steps to generate insertion positions according to their predetermined functions; and

a multiplexing step, according to the position state flag and the program state flag, the output of the step is generated from a plurality of insertion positions, and an insertion position is selected as the output; and

A protection bit code insertion step, according to the insertion position N generated by the first protection bit code position generation step, respectively inserting each protection bit code into the N-1th bit and the Nth bit of the corresponding instruction of the program Among the elements, an encryption program is generated.

According to another characteristic of the present invention, a method for decrypting an encrypted program is proposed. The encrypted program is encrypted by inserting the protection bit code into the original program. The encrypted program has a plurality of instructions, and each instruction has 1 bit Yuan, each protection bit code has P bits, and this method comprises the following steps:

A second protection bit code position generation step, which generates the insertion positions of the plurality of protection bit codes according to the state of the processor when executing the program, wherein a position status flag is used to instruct the processor to access the data area A segment or an access program segment, a program state flag is used to indicate the state of the processor, and the step of generating the second protection bit code position also includes the following steps:

a plurality of insertion position generating steps to generate insertion positions according to their predetermined functions; and

a multiplexing step, according to the position state flag and the program state flag, the output of the step is generated from a plurality of insertion positions, and an insertion position is selected as the output; and

A protection bit code removal step, inputting the program, and removing the Nth bit of the corresponding instruction of the program according to the insertion position N generated by the second protection bit code position generation step.

According to yet another feature of the present invention, a method for decrypting an encrypted program is proposed. The encrypted program inserts two sets of protection bit codes into the original program for encryption. The encrypted program has a plurality of instructions, one of which is A group may contain two encryption instructions, the method includes the following steps:

A third protection bit code position generation step, which generates the third insertion position of the plurality of protection bit codes according to the state of the processor when executing the program, wherein a position status flag is used to indicate the processor access In the data segment or the access program segment, a program status flag is used to indicate the status of the processor, and the step of generating the third protection bit code position also includes the following steps:

a plurality of insertion position generating steps to generate insertion positions according to their predetermined functions; and

A multiplexing step, according to the position state flag and the program state flag, the output of the step is generated from a plurality of insertion positions, and an insertion position is selected as the output;

A fourth protection bit code position generation step, which generates the fourth insertion position of the plurality of protection bit codes according to the state of the processor when executing the program, wherein a position status flag is used to indicate the processor access In the data section or the access program section, a program state flag is used to indicate the state of the processor, and the step of generating the fourth protection bit code position also includes the following steps:

a plurality of insertion position generating steps to generate insertion positions according to their predetermined functions; and

a multiplexing step, according to the position state flag and the program state flag, the output of the step is generated from a plurality of insertion positions, and an insertion position is selected as the output; and

A third protection bit code removal step, inputting the low half word group of the encryption program, and according to the third insertion position N1 generated by the third protection bit code position generation step, to correspond the program to the 0th of the instruction N1 bit removal of bits to K-1 bits; and

A fourth protection bit code removal step, inputting the upper half word group of the encryption program, and according to the fourth insertion position N2 produced by the fourth protection bit code position generation step, to correspond the program to the Kth instruction Bits N2 to 2K-1 bits are removed.

Description of drawings

Fig. 1: A block diagram of a device for encrypting and protecting a program with a protected bit code according to the present invention.

Fig. 2: The circuit diagram of the second protection bit code position generating device of the present invention.

FIG. 3-FIG. 4: Schematic diagrams of insertion positions generated by the second protection bit code position generating device of the present invention.

Fig. 5: The circuit diagram of the protection bit code removing device of the present invention.

Fig. 6: The block diagram of another embodiment of the device for encrypting and protecting a program with the protection bit code of the present invention

Detailed ways

Fig. 1 shows the block diagram that the present invention carries out encryption protection device to a program with protection bit code, and it comprises a protection bit code generation device 110, a first protection bit code position generation device 120, a protection bit code insertion The device 130 , a second protection bit code position generation device 210 and a protection bit code removal device 220 . And the encrypted program has complex instructions, each instruction has I bit (I is a positive integer), and the protection bit code has P bits (P positive integer), in the present embodiment, I is 31 Bit, P is 1 bit, that is, I+P is 32 bits, or I is 32 bits, and P is 1 bit.

The protection bit code generator 110 generates a corresponding protection bit code according to each instruction of the program, and the protection bit code can be a parity check bit (Parity bit), an error correction code (Error Correction Code, ECC) or an indication bit of the processor mode when the instruction is executed.

The first protected bitcode position generator 120 generates the insertion position N (N is a positive integer) of each protected bitcode according to the state of the processor when the program is executed. The protection bit code inserting device 130 is based on the insertion position N generated by the first protection bit code position generating device 120, respectively inserting each protection bit code into the N-1th and Nth bits of the corresponding instruction of the program Among the elements, an encryption program is generated.

The second protection bit code position generating device 210 generates the insertion position of each protection bit code according to the state of the processor when the program is executed. This protection bit code removing device 220 inputs an encryption program, and this encryption program is to insert the protection bit code into the original program and be encrypted, and according to each position generated by the second protection bit code position generation device 210 Insert position N to remove the protection bit code in each instruction of the encrypted program.

The first protected bitcode position generating device 120 and the second protected bitcode position generating device 210 generate insertion positions according to the state of the processor when the program is executed. FIG. 2 is a circuit diagram thereof. Each first and second protection bit code position generating device includes an access status register (AccessStatus Register, ASR) 310, a program status register (Program Status Register, PSR) 320, a multiplexer 330 And a plurality of insertion position generating devices 340-380.

The access status register (ASR) 310 is 1 bit. When the value is 1, it means the processor accesses the data segment, and when the value is 0, it means the processor accesses the program segment. The program state temporary register (PSR) 320 is 3 bits, and when its value is 1xx, it means that the processor enters the state of automatically booting to execute the BIOS program after being reset; when its value is 01x, it means that the processor is in the core of the operating system ( OS Kernel) state; when its value is 001, it represents that the processor is in a special authentication program state; when its value is 000, it represents that the processor is in a general user program state.

The PPG_Mode signal in FIG. 2 is used to select the relationship between the output signal PBP and the input signal of the multiplexer 330 . The PPG_Mode signal is composed of the access status register (ASR) 310 and the program status register (PSR) 320 , that is, PPG_Mode={ASR,PSR[2:0]). When the processor accesses the data segment, the value of the access status register (ASR) 310 is 1, PPG_Mode=1xxx, and the multiplexer 330 will select the output of the insertion position generating device 380 as the multiplexer 330 The output signal PBP. And after the processor is reset, when entering the state of automatically booting to execute the BIOS program, the value of the access status register (ASR) 310 is 0, the value of the program status register (PSR) 320 is 1xx, the number of The multiplexer 330 will select the output of the insertion position generator 340 as the output signal PBP of the multiplexer 330 .

The plurality of insertion position generating devices 340-380 generate insertion positions according to their predetermined functions. Wherein, the insertion position generating device 380 can be an empty device, which means there is no insertion position, and its output signal is 000000b. The insertion position generating device 340 generates the insertion position through a modulus operation of a given value x, that is, F1(x)=(x mod 32). The inserting position generating device 350 subtracts a second given value through a modulus operation from a first given value to generate the inserting position, that is, F2(x)=31−(x mod 32).

The insertion position generation device 360 combines a first given value with the partial address line value of the processor, and then undergoes a modulus operation to generate an insertion position, that is, F3(x, a)=[(x+ {a[0], a[1], a[2], a[3], a[4]}) mod 32]. The insertion position generator 370 inverts a given value x[4:0] to generate the insertion position, that is, F4(x)={x[0], x[1], x[2], x [3],x[4]}. The insertion position generator can also combine the access status register (ASR) 310 with the program status register (PSR) 320 to generate the insertion position, or combine the position status register with the program After the state registers are combined, the insertion position is generated through a modulus operation.

K1, K2, K3 and K4 among Fig. 2 provide a given value respectively to this plurality of insertion position generating devices 340-380, and it can burn into a hardware circuit earlier, also can be register, and by the system Go to settings. In this way, different protection bit code insertion positions can be generated for different programs and states of the processor.

FIG. 3 shows that when K1=K2=K3=K4=3, the multiple insertion position generators 340, 350 and 380 generate different protection bit code insertion positions. Among them, F1(x)=(x mod 32)=3, which means that after the processor is reset and enters the state of automatically booting to execute the BIOS program, the protection bit code insertion position is bit 3. F2(x)=[31-(x mod 32)]=28, which means that when the processor is in the operating system kernel (OS Kernel) state, its protection bit code insertion position is bit 28. F4(x)={x[0], x[1], x[2], x[3], x[4]}={11000b}=24, which means that the processor is in a general user program state , the insertion position of the protection bit code is bit 24.

FIG. 4 shows that when K3=3, the insertion position generation device 360 generates different protection bit code insertion positions. F3(x,a)=(x+{a[0],a[1],a[2],a[3],a[4]}) mod 32=(3+{a[0],a[ 1], a[2], a[3], a[4]}) mod 32. It means that when the processor is in an authentication program, the insertion position of the protection bit code will change as shown in FIG. 4 , making the authentication program code difficult to steal or decipher.

The output signal PBP (P-bit Bit Position) of the multiplexer 330 is composed of 6 bits, wherein the Bollinger value of PBP[5] represents whether PBP[4:0] is the protection bit code insertion position . When PBP[5:0]=0xxxxxb, it indicates the insertion position of PBP[4:0] unprotected bit code. When PBP[5:0]=100101b, it means that PBP[4:0] is the protection bit code insertion position, and the protection bit code insertion position is at the position of 00101b=5. Since the plurality of insertion position generating devices 340-370 all generate protection bit code insertion positions, their output signals will be combined with a high potential to form the output signal PBP[5:0] of the multiplexer 330, wherein , the high potential forms PBP[5] (that is, PBP[5]=1), to indicate that PBP[4:0] is the insertion position of the protection bit code. The plurality of insertion position generators 380 is an empty device, indicating that there is no insertion position, so its output signal is 000000b, indicating that PBP[4:0] has no protection bit code insertion position.

FIG. 5 is a circuit diagram of the protection bit code removing device 220 , which mainly includes multiplexers 510 , 520 and 530 . Its input terminal 540 inputs a 32-bit encryption program, the encryption program inserts the protection bit code into the original program to be encrypted, and according to the plurality of insertions generated by the second protection bit code position generating device 210 Position PBP[4:0] to remove the protection bit code in the complex instruction of the encrypted program. When PBP[5]=0, it means that PBP[4:0] has no protection bit code insertion position, so the multiplexer 510 directly outputs the input terminal 540 . When PBP[5]=1, it means PBP[4:0] is the insertion position of the protection bit code, the multiplexer 520 outputs the protection bit code according to the PBP[4:0] signal, the multiplexer The device 530 outputs the command without the protection bit code according to the PBP[4:0] signal, and the protection bit code and the command without the protection bit code are combined into a 32-byte word group, and the Since PBP[5]=1, the multiplexer 510 connects it to output.

In this embodiment, the protection bit code generation device 110, the first protection bit code position generation device 120, and the protection bit code insertion device 130 can be implemented using hardware, or can be processed offline using software to generate a encryption program. The protection bit code removal device 220 and the second protection bit code position generation device 210 can be combined with a processor core, the protection bit code removal device 220 inputs the encryption program, and according to the second protection bit code The plurality of insertion positions N generated by the position generating device 210 is used to remove the protection bit codes in the plurality of instructions of the encrypted program. In this way, the processor core can correctly execute the decrypted program, and the encrypted program does not need to worry about being easily cracked by others, thus achieving the purpose of protection.

Fig. 6 is another embodiment of the present invention, which is a device for decrypting an encrypted program that inserts two groups of protection bit codes into the original program. The encrypted program has multiple instructions, and one word group can contain two Encrypted instructions, each encrypted instruction is 16 bits. The device includes a third protected bit code position generating device 610 , a fourth protected bit code position generating device 620 , a third protected bit code removing device 630 and a fourth protected bit code removing device 640 .

The third protected bit code position generating device 610 and the fourth protected bit code position generating device 620 respectively generate the third insertion position PBP1[4:0 of each protected bit code according to the state of the processor when the program is executed. ] and the fourth insertion position PBP2[4:0].

The third protection bit code removing device 630 inputs the low half word group (low halfword) of the encryption program, and according to each third insertion position PBP1[4: 0] to remove the PBP1[4:0] bits of the 0 to 15 bits of the complex instruction of the program. The fourth protection bit code removal device 640 inputs the high half word group (high half word) of the encryption program, and according to each fourth insertion position PBP2 [4: 0] to remove the PBP2[4:0] bits of the 16th to 31st bits of the instruction corresponding to the program.

It can be seen from the above description that the technology of the present invention can achieve the functions of encryption and decryption only with simple hardware, and does not need to use a complicated virtual random number generator like the known technology, which can save costs, and at the same time, protect the generation and removal of bit codes. The hardware is quite simple, and does not increase the processing time of encryption and decryption as in the known technology, but is far less than the time spent in the processing of encryption and decryption in the known technology, so its execution performance is much better than that of the known technology.

It should be noted that the above-mentioned embodiments are only examples for convenience of description, and the scope of rights claimed by the present invention should be determined by the scope of the patent application, rather than limited to the above-mentioned embodiments.

Claims (48)

1. A device for encrypting and protecting a program with a protection bit code, the program has a plurality of instructions, each instruction has I bits, and the I is a positive integer, the device includes: A protection bit code generating device, according to the plurality of instructions of the program to generate a corresponding plurality of protection bit codes, each protection bit code has P bits, and the P is a positive integer; A first protected bit code position generating device, which generates the insertion position N of each protected bit code according to the state of the processor when executing the program, where N is a positive integer, wherein the first protected bit code position is generated The device contains: a location status register, used to instruct the processor to access data segments or access program segments; a program state register, used to indicate the state of the processor; a plurality of insertion position generating devices to generate insertion positions according to their predetermined functions; and A multiplexer, which has a plurality of input terminals to be coupled to the output terminals of the plurality of insertion position generating devices, and selects one of the plurality of input terminals according to the position state register and the program state register insert position as output; and A protection bit code insertion device, according to the insertion position N generated by the first protection bit code position generating device, respectively inserts each protection bit code into the N-1th bit and the Nth bit of the corresponding instruction of the program Among them, an encryption program is generated. 2. The device for encrypting and protecting a program with a protection bit code as claimed in claim 1, further comprising: A second protection bit code position generating device, which generates the aforementioned insertion position N of each protection bit code according to the state of the processor when executing the program, wherein the second protection bit code position generating device includes: a location status register, used to instruct the processor to access data segments or access program segments; a program state register, used to indicate the state of the processor; a plurality of insertion position generating devices to generate insertion positions according to their predetermined functions; and A multiplexer, which has a plurality of input terminals to be coupled to the output terminals of the plurality of insertion position generating devices, and selects one of the plurality of input terminals according to the position state register and the program state register insert position as output; and A protection bit code removal device inputs the program, and removes the Nth bit of the corresponding instruction of the program according to the insertion position N generated by the second protection bit code position generation device. 3. The device for encrypting and protecting a program with a protection bit code as claimed in claim 2, wherein the plurality of insertion position generating devices of the first protection bit code position generating device and the second protection The plurality of inserting position generating means of the bit code position generating means may be an empty device to indicate that there is no aforementioned inserting position. 4. The device for encrypting and protecting a program with a protection bit code as claimed in claim 2, wherein the plurality of insertion position generating devices of the first protection bit code position generating device and the second protection The plurality of insertion position generating devices of the bit code position generating device can generate the insertion position by performing a function operation on a given value. 5. The device for encrypting and protecting a program with a protection bit code as claimed in claim 2, wherein the plurality of insertion position generating devices of the first protection bit code position generating device and the second protection The plurality of inserting position generating devices of the bit code position generating device can subtract a second given value through function operation from a first given value to generate the inserting position. 6. The device for encrypting and protecting a program with a protection bit code as claimed in claim 2, wherein the plurality of insertion position generating devices of the first protection bit code position generating device and the second protection The plurality of inserting position generating devices of the bit code position generating device can combine a first given value with the address value of the processor part, and then perform a function operation to generate the inserting position. 7. The device for encrypting and protecting a program with a protection bit code as claimed in claim 2, wherein the plurality of insertion position generating devices of the first protection bit code position generating device can use the first After the position status register of the protected bit code position generating device is combined with the program status register of the first protected bit code position generating device, to generate the insertion position, the second protected bit code position generating device A plurality of insertion position generators can combine the position status register of the second protected bit code position generator with the program status register of the second protected bit code position generator to generate the insertion position. 8. The device for encrypting and protecting a program with a protection bit code as claimed in claim 2, wherein the plurality of insertion position generating devices of the first protection bit code position generating device can use the first After combining the position status register of the protected bit code position generating device with the program status register of the first protected bit code position generating device, the insertion position and the second protected bit are generated through function operations. A plurality of insertion position generating devices of the code position generating device can combine the position status register of the second protected bit code position generating device with the program state register of the second protected bit code position generating device, and then Through the function operation, to generate the insertion position. 9. The device for encrypting and protecting a program with a protection bit code as claimed in claim 2, wherein the protection bit code removal device can also be generated according to the second protection bit code position generation device The aforementioned insertion position N, and the Nth bit of the corresponding instruction of the program is moved to the highest bit. 10. The device for encrypting and protecting a program with a protection bit code as claimed in claim 2, wherein the protection bit code removal device can also be generated according to the second protection bit code position generation device The insertion position N of the program, and the Nth bit of the corresponding instruction of the program is moved to the lowest bit. 11. The device for encrypting and protecting a program with a protection bit code as claimed in claim 2, wherein the protection bit code removal device can also be generated according to the second protection bit code position generation device The insertion position N of the program, and the corresponding instruction of the program is output directly. 12. The device for encrypting and protecting a program with a protection bit code as claimed in claim 2, wherein I+P=32. 13. The device for encrypting and protecting a program with a protection bit code as claimed in claim 3, wherein I=32. 14. A device for decrypting an encrypted program, the encrypted program is encrypted by inserting a protection bit code into the original program, the encrypted program has a plurality of instructions, each instruction has 1 bit, and each protection bit The code has P bits, which means contains: A second protection bit code position generation device, which generates the insertion positions of the plurality of protection bit codes according to the state of the processor when executing the program, wherein the second protection bit code position generation device includes: a location status register, used to instruct the processor to access data segments or access program segments; a program status register, used to indicate the status of the processor; a plurality of insertion position generating devices to generate insertion positions according to their predetermined functions; and A multiplexer, which has a plurality of input terminals to be coupled to the output terminals of the plurality of insertion position generating devices, and selects one of the plurality of input terminals according to the position state register and the program state register insert position as output; and A protection bit code removal device inputs the program, and removes the Nth bit of the corresponding instruction of the program according to the insertion position N generated by the second protection bit code position generation device. 15. The device for decrypting an encrypted program as claimed in claim 14, wherein the plurality of inserting position generating means can be a null device to indicate that there is no inserting position. 16 . The device for decrypting an encrypted program as claimed in claim 14 , wherein the plurality of insertion position generators can generate the insertion position by performing a function operation on a given value. 17. The device for decrypting an encrypted program as claimed in claim 14, wherein the plurality of insertion position generators can subtract a first given value from a second given value through function operation , to generate the insertion position. 18. The device for decrypting an encrypted program as claimed in claim 14, wherein the plurality of insertion position generating devices can combine a first given value with a partial address value of the processor, The insertion position is then generated through function operation. 19. The device for decrypting an encrypted program as claimed in claim 14, wherein the plurality of insertion position generating devices can combine the position status register with the program status register to generate The insertion position. 20. The device for decrypting an encrypted program as claimed in claim 14, wherein the plurality of insertion position generating devices can combine the position state register with the program state register, and then pass Function operation to produce the insertion position. 21. The device for decrypting an encrypted program as claimed in claim 14, wherein I+P=32. 22. The device for decrypting an encrypted program as claimed in claim 14, wherein I=32. 23. A device for decrypting an encrypted program. The encrypted program encrypts two sets of protection bit codes by inserting them into the original program. The encrypted program has multiple instructions, wherein one block can contain two encrypted instructions, The unit contains: A third protected bit code position generating device, which generates the third insertion position of the plurality of protected bit codes according to the state of the processor when executing the program, wherein the third protected bit code position generating device includes: a location status register, used to instruct the processor to access data segments or access program segments; a program status register, used to indicate the status of the processor; a plurality of insertion position generating devices to generate insertion positions according to their predetermined functions; and A multiplexer, which has a plurality of input terminals to be coupled to the output terminals of the plurality of insertion position generating devices, and selects one of the plurality of input terminals according to the position state register and the program state register insert position as output; A fourth protection bit code position generation device, which generates the fourth insertion position of the plurality of protection bit codes according to the state of the processor when executing the program, wherein the fourth protection bit code position generation device includes: a location status register, used to instruct the processor to access data segments or access program segments; a program status register, used to indicate the status of the processor; a plurality of insertion position generating devices to generate insertion positions according to their predetermined functions; and A multiplexer, which has a plurality of input terminals to be coupled to the output terminals of the plurality of insertion position generating devices, and selects one of the plurality of input terminals according to the position state register and the program state register insert position as output; and A third protection bit code removing device, input the low half word group of the encryption program, and according to the third insertion position N1 generated by the third protection bit code position generating device, to correspond the program to the first bit of the instruction the removal of the N1-th bit from bit 0 to bit K-1; and A fourth protection bit code removal device, input the upper half word group of the encrypted program, and according to the fourth insertion position N2 produced by the fourth protection bit code position generating device, to correspond the program to the Kth instruction The N2th bit of bits to 2K-1 bits is removed. 24. The device for decrypting an encrypted program according to claim 23, wherein K=16. 25. A method for encrypting and protecting a program with a protection bit code, the program has a plurality of instructions, each instruction has I bits, and the I is a positive integer, the method comprises the following steps: A protection bit code generating step, generating a plurality of corresponding protection bit codes according to the plurality of instructions of the program, each protection bit code has P bits, and the P is a positive integer; A first protection bit code position generating step, which generates the insertion position N of each protection bit code according to the state of the processor when executing the program, where N is a positive integer, wherein a position status flag is used to indicate the processing The device accesses the data segment or accesses the program segment, and a program status flag is used to indicate the status of the processor. The step of generating the first protection bit code position also includes the following steps: a plurality of insertion position generating steps to generate insertion positions according to their predetermined functions; and a multiplexing step, according to the position state flag and the program state flag, the output of the step is generated from a plurality of insertion positions, and an insertion position is selected as the output; and A protection bit code insertion step, according to the insertion position N generated by the first protection bit code position generation step, respectively inserting each protection bit code into the N-1th bit and the Nth bit of the corresponding instruction of the program Among the elements, an encryption program is generated. 26. The method for encrypting and protecting a program with a protection bit code as claimed in claim 25, further comprising the following steps: A second protection bit code position generation step, which generates the insertion position N of each protection bit code according to the state of the processor when executing the program, wherein a position status flag is used to indicate that the processor accesses the data segment Or for accessing the program segment, a program state flag is used to indicate the state of the processor, and the step of generating the second protection bit code position also includes the following steps: a plurality of insertion position generating steps to generate insertion positions according to their predetermined functions; and a multiplexing step, according to the position state flag and the program state flag, the output of the step is generated from a plurality of insertion positions, and an insertion position is selected as the output; and A protection bit code removal step, inputting the program, and removing the Nth bit of the corresponding instruction of the program according to the insertion position N generated by the second protection bit code position generation step. 27. The method for encrypting and protecting a program with a protection bit code as claimed in claim 26, wherein the plurality of insertion position generation steps of the first protection bit code position generation step and the second protection The plurality of insertion position generation steps of the bit code position generation step may be an empty step to indicate that there is no aforementioned insertion position. 28. The method for encrypting and protecting a program with a protection bit code as claimed in claim 26, wherein the plurality of insertion position generation steps of the first protection bit code position generation step and the second protection The plurality of insertion position generation steps of the bit code position generation step can generate the insertion position by performing a function operation on a given value. 29. The method for encrypting and protecting a program with a protection bit code as claimed in claim 26, wherein the plurality of insertion position generation steps of the first protection bit code position generation step and the second protection The plurality of inserting position generating steps of the bit code position generating step can subtract a second given value through function operation from a first given value to generate the inserting position. 30. The method for encrypting and protecting a program with a protection bit code as claimed in claim 26, wherein the plurality of insertion position generation steps of the first protection bit code position generation step and the second protection The plurality of inserting position generating steps of the bit code position generating step can combine a first given value with a part of the address value of the processor, and then perform function operation to generate the inserting position. 31. The method for encrypting and protecting a program with a protection bit code as claimed in claim 26, wherein the plurality of insertion position generation steps of the first protection bit code position generation step can use the first After the position status flag of the protection bit code position generation step is combined with the program status flag of the first protection bit code position generation step to generate the insertion position, the plurality of the second protection bit code position generation steps The insertion position generating step can combine the position status flag of the second protection bit code position generation step with the program status flag of the second protection bit code position generation step to generate the insertion position. 32. The method for encrypting and protecting a program with a protection bit code as claimed in claim 26, wherein the plurality of insertion position generation steps of the first protection bit code position generation step can use the first After the position status flag of the protection bit code position generation step is combined with the program status flag of the first protection bit code position generation step, the insertion position and the second protection bit code position are generated through function operation. The plurality of insertion position generating steps in the generating step can be combined with the position status flag of the second protected bit code position generating step and the program status flag of the second protected bit code position generating step, through function operation, to Generate the insertion position. 33. The method for encrypting and protecting a program with a protection bit code as claimed in claim 26, wherein the step of removing the protection bit code can also be generated according to the second position generation step of the protection bit code The aforementioned insertion position N, and the Nth bit of the corresponding instruction of the program is moved to the highest bit. 34. The method for encrypting and protecting a program with a protection bit code as claimed in claim 26, wherein the step of removing the protection bit code can also be generated according to the second position generation step of the protection bit code The aforementioned insertion position N of the program, and the Nth bit of the corresponding instruction of the program is moved to the lowest bit. 35. The method for encrypting and protecting a program with a protection bit code as claimed in claim 26, wherein the step of removing the protection bit code can also be generated according to the second position generation step of the protection bit code The aforementioned insertion position N, and the corresponding instructions of the program are directly output. 36. The method for encrypting and protecting a program with a protection bit code as claimed in claim 26, wherein I+P=32. 37. The method for encrypting and protecting a program with a protection bit code as claimed in claim 26, wherein I=32. 38. A method of decrypting an encrypted program encrypted by inserting a protection bit code into an original program, the encrypted program having a plurality of instructions, each instruction having 1 bit, each protection bit The code has P bits, and the method comprises the following steps: A second protection bit code position generation step, which generates the insertion positions of the plurality of protection bit codes according to the state of the processor when executing the program, wherein a position status flag is used to indicate that the processor accesses the data area A segment or an access program segment, a program state flag is used to indicate the state of the processor, and the step of generating the second protection bit code position also includes the following steps: a plurality of insertion position generating steps to generate insertion positions according to their predetermined functions; and a multiplexing step, according to the position state flag and the program state flag, the output of the step is generated from a plurality of insertion positions, and an insertion position is selected as the output; and A protection bit code removal step, inputting the program, and removing the Nth bit of the corresponding instruction of the program according to the insertion position N generated by the second protection bit code position generation step. 39. The method for decrypting an encrypted program as claimed in claim 38, wherein the step of generating the plurality of inserting positions can be an empty step to indicate that there is no aforementioned inserting position. 40. The method for decrypting an encrypted program as claimed in claim 38, wherein the step of generating the plurality of insertion positions can generate the insertion positions by performing a function operation on a given value. 41. The method for decrypting an encrypted program as claimed in claim 38, wherein the plurality of insertion position generation steps can be a first given value minus a second given value via function operation , to generate the insertion position. 42. The method for decrypting an encrypted program as claimed in claim 38, wherein the step of generating the plurality of insertion positions can combine a first given value with a partial address value of the processor , and then through function operations to generate the insertion position. 43. The method for decrypting an encrypted program as claimed in claim 38, wherein the plurality of insertion position generation steps can combine the position state flag with the program state flag to generate the insertion position Location. 44. The method for decrypting an encrypted program as claimed in claim 38, wherein the step of generating the plurality of insertion positions can combine the position state flag with the program state flag, and then perform a function operation , to generate the insertion position. 45. The method for decrypting an encrypted program as claimed in claim 38, wherein I+P=32. 46. The method for decrypting an encrypted program as claimed in claim 38, wherein I=32. 47. A method for decrypting an encrypted program. The encrypted program is encrypted by inserting two sets of protection bit codes into the original program. The encrypted program has a plurality of instructions, wherein one block can contain two encrypted instructions , the method includes the following steps: A third protection bit code position generation step, which generates the third insertion position of the plurality of protection bit codes according to the state of the processor when executing the program, wherein a position status flag is used to indicate the processor access In the data segment or the access program segment, a program status flag is used to indicate the status of the processor, and the step of generating the third protection bit code position also includes the following steps: a plurality of insertion position generating steps to generate insertion positions according to their predetermined functions; and A multiplexing step, according to the position state flag and the program state flag, the output of the step is generated from a plurality of insertion positions, and an insertion position is selected as the output; A fourth protection bit code position generation step, which generates the fourth insertion position of the plurality of protection bit codes according to the state of the processor when executing the program, wherein a position status flag is used to indicate the processor access In the data section or the access program section, a program state flag is used to indicate the state of the processor, and the step of generating the fourth protection bit code position also includes the following steps: a plurality of insertion position generating steps to generate insertion positions according to their predetermined functions; and a multiplexing step, according to the position state flag and the program state flag, the output of the step is generated from a plurality of insertion positions, and an insertion position is selected as the output; and A third protection bit code removal step, inputting the low half word group of the encryption program, and according to the third insertion position N1 generated by the third protection bit code position generation step, to correspond the program to the 0th of the instruction N1 bit removal of bits to K-1 bits; and A fourth protection bit code removal step, inputting the upper half word group of the encryption program, and according to the fourth insertion position N2 produced by the fourth protection bit code position generation step, to correspond the program to the Kth instruction Bits N2 to 2K-1 bits are removed. 48. The method for decrypting an encrypted program as claimed in claim 47, wherein K=16.

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