CN100356567C - Phase transformation micro, nano electronic memory device and manufacturing method - Google Patents

Abstract

The invention designs a novel phase-change micro- and nano-electronic storage device and a preparation method thereof. The design principle of the present invention is based on the tip effect, that is, after the voltage is applied, the resistance or current at the tip of the pattern will be very large, which is the trigger point for the phase change of the phase change layer in the device unit. Each layer of thin film of the device is prepared on the substrate by using a thin film preparation process, and then a device unit containing a tip is prepared by a microfabrication process. The size of the phase transition region in the device unit is approximately in the range of 2 to 200nm. The repeated arrangement of device units constitutes micro- and nano-electronic memory devices. This micro-nanoelectronic memory device has a simple structure, is convenient to prepare, and is well compatible with the current semiconductor technology, and can also easily realize the small size of the device unit, which is conducive to improving the integration of integrated circuits and realizing memory-oriented A change in direction for nanoelectronic devices.

Description

A phase-change micro- and nano-electronic memory device and its manufacturing method

technical field

The invention relates to a phase-change micro- and nano-electronic storage device and a preparation method thereof. More precisely, it relates to a phase-change memory device prepared by microfabrication technology, and the size of the phase-change region in the phase-change memory device unit is about in the range of 2 to 200nm. The invention belongs to the technical field of microelectronics.

Background technique

Phase Change Random Access Memory (PC-RAM, Phase Change-Random Access Memory) technology is based on S.R. Ovshinsky in the late 1960s (Phys. Rev. Lett., 21, 1450-1453, 1968) and early 1970s (Appl. Phys . Lett., 18, 254-257, 1971) put forward the idea that the phase-change thin film can be applied to the phase-change storage medium, and it is a storage device with low price and stable performance. PC-RAM memory can be made on a silicon wafer substrate, and its key material is a recordable phase-change film. The key feature of phase change alloy material is that when it is given an electric pulse or laser heating method, it can make the material undergo reversible phase transition between amorphous state and polycrystalline state. It exhibits high resistance (low reflectivity) in the amorphous state, and low resistance (high reflectivity) in the polycrystalline state, and the variation range can reach several orders of magnitude, so that it can be used as a non-volatile memory. The reversible change characteristics of the optical performance of the phase change film have been successfully used in CD-RW, DVD±RW, DVD-RAM and HD-DVD series of erasable and rewritable phase change discs (Jpn.J.Appl.Phys., 39,770 ~774, 2000; Jpn. J. Appl. Phys., 42, 1044-1051, 2003). Although the PC-RAM memory technology using its resistance properties was proposed very early, due to the limitation of preparation technology and process, the phase change material can only undergo phase change under a strong electric field, which limits its practical development. process. With the development of nano-fabrication technology and process, the size of the material in the device can be reduced to the nanometer level, the voltage required for the phase transition of the material is greatly reduced, the power consumption is reduced, and the performance of the material has also undergone tremendous changes. In 1999, ECD (Energy Conversion Devices, Inc) invented a sulfide film, which can undergo phase transition at a very low voltage, and has excellent electrical properties after phase transition, especially suitable for manufacturing memory (SPIE, 3891, 2 ~9, 1999). In the same year, ECD jointly established Ovonyx, which is dedicated to the development of this phase change memory. Since then, PC-RAM memory has been developed rapidly.

PC-RAM memory is considered by the International Semiconductor Industry Association to be the most likely to replace the current Flash memory has become the mainstream product of future memory and the first device to become a commercial product.

At present, companies such as Ovonyx, Intel, Sansung, Hitachi, STMicroelectronics and British Aerospace are conducting research on PC-RAM memory in the world, and are currently conducting research and development on technology improvement and manufacturability. The key to the commercialization of PC-RAM memory lies in the design and preparation of memory devices. For this reason, the present invention designs a novel PC-RAM memory device and its preparation method, which are characterized by simple structure, convenient preparation, and good compatibility with current semiconductor technology.

Contents of the invention

The object of the present invention is to provide a novel micro-nano electronic memory device structure and a preparation method thereof.

The purpose of the present invention is based on the following principles:

If the two graphics are embedded with each other and the overlapping parts are removed, a small graphic with a tip will be divided. According to the tip effect, after a voltage is applied to the small graphic, the resistance or current at the tip of the small graphic will be very large, which is micro, The trigger point for the phase change of the phase change layer in the nanoelectronic memory device unit, so as to realize the reversible transition between the amorphous state and the polycrystalline state of the phase change film, wherein the amorphous state is high resistance, and the polycrystalline state for low resistance.

Therefore, thin films such as thermal insulation layer, phase change layer, transition layer and electrode layer are prepared on the substrate by using thin film preparation technology, and then micro-fabrication technology is used to prepare cutting-edge micro and nano electronic memory device units, multiple micro and nano Electronic memory device units are arranged repeatedly and each device unit is well integrated with the complementary metal-oxide-semiconductor structure and addressing selection circuit in the substrate to form a micro-nano electronic memory device.

This micro-nanoelectronic memory device has a simple structure, is convenient to prepare, and is well compatible with the current semiconductor technology, and can also easily realize the small size of the device unit, which is conducive to improving the integration of integrated circuits and realizing memory-oriented A change in direction for nanoelectronic devices.

The specific preparation process of the present invention is divided into two steps: the first step is cleaning of the substrate; the second step is to combine microfabrication technology to prepare micro-nano electronic memory device units.

The cleaning process of the substrate is as follows: Taking the cleaning of the silicon substrate as an example, first immerse the silicon wafer in the acetone cleaning solution and use an ultrasonic generator to ultrasonically clean it for 5-10 minutes; after ultrasonic cleaning, take out the silicon wafer and rinse it with pure water for 3-4 times ; Then hydrogen peroxide (H ₂ O ₂ ), ammonia water and purified water are prepared into a cleaning solution at a volume ratio of 1:1.5:5, and the silicon wafer is immersed in the cleaning solution and heated until the cleaning solution is boiled; after cooling, the sample is taken out Rinse 3-4 times with pure water; then prepare a cleaning solution with hydrogen peroxide (H ₂ O ₂ ), hydrochloric acid (40% concentration) and pure water at a volume ratio of 1:1.5:5, and immerse the silicon wafer in this cleaning solution After heating, until the cleaning solution is boiled; after cooling, take out the sample and rinse it with pure water for 3-4 times; finally soak it in hydrofluoric acid solution for 5-10min, and use 40% hydrofluoric acid and pure water to press 1 : 10 volume ratio preparation. After the silicon wafer is taken out and oxidized, it can be used for the preparation of related thin films.

Taking a special example shown in Figure 1 as the object of illustration, the preparation process of micro- and nanoelectronic memory device units is introduced. The part indicated by the dotted box in the figure is a device unit. Sectional view of the site. The specific preparation process of the device unit is:

(1). Using one of the thin film preparation techniques, such as sputtering, evaporation, plasma-assisted deposition, chemical vapor deposition, laser-assisted deposition, etc., after cleaning the substrate (as shown in Figure 6) Prepare the first heat-insulating layer, such as SiO ₂ , Si ₃ N ₄ , etc., with a thickness of 5-200 nm, as shown in FIG. 7 .

(2). On the first heat insulating layer, use any one of sputtering method, evaporation method, plasma-assisted deposition method, chemical vapor deposition method, and laser-assisted deposition method film preparation process to prepare a phase change layer (as shown in Figure 8 Shown), the thickness of the phase change layer is 2-200nm.

(3). Using one of the microfabrication techniques, such as electron beam lithography, electron beam exposure, extreme ultraviolet lithography, focused ion beam etching, ion etching, nanoimprint lithography, etc., the phase change film It is prepared into a figure with a certain shape, or a polygon, a square, a rectangle, a circle or a ring, etc. The graph shown in Figure 9 is a square.

(4). Using one of the microfabrication techniques, such as electron beam lithography, electron beam exposure, extreme ultraviolet lithography, focused ion beam etching, ion etching, nanoimprint lithography, etc., in the prepared Another figure with a certain shape is prepared in the phase change figure, such as one of circle, polygon, ring, etc., and the two figures are embedded in each other, and at the same time, the phase change of the overlapping parts of the two figures is removed until it is exposed. The first insulating layer, thus producing small figures with pointed ends. As shown in FIG. 10 , the embedded figure of the square is a circle, and the diameter of the circle is larger than the side length of the square.

(5). Then use one of the microfabrication techniques, such as electron beam lithography, extreme ultraviolet lithography, focused ion beam etching, electron beam exposure, ion etching, nanoimprint lithography, etc., to process small graphics to control the size of the tip of the gizmo. For example, adopt the method shown in Figure 11 to process a concave groove (its shape as shown in Figure 4 or 5) in the center of the square, the opening width of the concave groove is greater than or equal to the width of the bottom of the groove, and the opening width of the groove is 10 -3000nm, the inclination angle of the side wall of the groove is 45-90°, and the height of the groove is the same as the thickness of the phase change layer. By changing the width of the groove to adjust the size of the tip, the width is controlled in the range of 2-100nm, and the thickness is the thickness of the phase change layer.

(6). Using thin film preparation technology, such as one of sputtering method, evaporation method, plasma-assisted deposition method, chemical vapor deposition method, laser-assisted deposition method, etc., to prepare the second layer of heat insulating layer, such as SiO ₂ , Si ₃ N ₄ , gas, etc., the thickness of the heat insulating layer is 5-100nm. Mask plate technology can be used to cover the concave groove area in Figure 11, and then prepare the second layer of heat insulating layer to obtain the pattern shown in Figure 12; or cover the entire surface of Figure 11 with the second layer of heat insulating layer (as shown in Figure 13), and then adopt a microfabrication process, such as one of electron beam lithography, extreme ultraviolet lithography, focused ion beam etching, electron beam exposure, ion etching, etc., to cover the concave shape in Figure 11 The heat insulating layer in the groove area is removed until the phase change layer on the two side walls of the groove is exposed, and the pattern shown in FIG. 12 can also be obtained.

(7). The area for preparing electrodes is processed by micro-processing technology. As shown in Figure 14, holes are drilled in the second heat insulation layer and the first heat insulation layer. The shape of the holes is one of annular holes or polygonal holes. Greater than the sum of the thicknesses of the first heat insulation layer and the second heat insulation layer. The hole shown in Fig. 4 or 5 is a trapezoidal hole, the opening width of the hole is 10-500nm, the length is 50-1000nm, and the inclination angle of the side wall of the hole is 45-90°.

(8). Using a thin film preparation process, such as sputtering, evaporation, plasma-assisted deposition, chemical vapor deposition, laser-assisted deposition, etc., using mask technology to form the concave groove in Figure 12 A transition layer is prepared inside, and the thickness of the transition layer is 2-50 nm, as shown in FIG. 15 .

(9). Using a film preparation process, such as sputtering, evaporation, plasma-assisted deposition, chemical vapor deposition, laser-assisted deposition, etc., to prepare an electrode film, the electrode is a conductive material, and the film thickness is 5-500nm, as shown in Figure 16.

(10). Using a microfabrication process, such as a chemical mechanical polishing process (CMP), polish to the second heat insulating layer to obtain an independent electrode, as shown in FIG. 17 . If the second heat insulating layer is a gaseous medium such as air, it needs to be polished to the phase change layer by CMP to obtain an independent electrode, as shown in Figure 18. The electrodes at the four corners in Figure 17 and Figure 18 are lower electrodes with a height of 10-700nm, and the rectangular electrodes in the center of the figure are upper electrodes with a height of 5-500nm.

After the above preparation process, a simple micro-nano electronic memory device unit is obtained. Taking the preparation process in Fig. 6 to Fig. 18 as an example, the finally obtained device unit contains four memory cells, and each memory cell is connected Complementary metal-oxide-semiconductor structures in the substrate and address selection circuits are well integrated. If this device unit is used as a repeating unit, micro and nano electronic memory devices can be obtained according to the array arrangement, and the lower electrodes of adjacent device units in the device can be separated from each other, or two device units share a lower electrode, as shown in Figure 1 The device shown is one of the cases where two device cells share a bottom electrode.

To sum up, the micro-nano electronic memory device of the present invention contains at least one device unit, and the device unit is reversibly switched between at least two different resistance states;

The substrate of the present invention is any one of silicon wafer, glass, GaAs, SiO ₂ , plastic, metal material or crystal material;

The first heat insulating layer in the present invention is one of oxide or nitride;

The second heat insulating layer in the present invention is one of oxide, nitride or gas;

The phase change layer described in the present invention is a chalcogenide compound;

The transition layer of the present invention is one of nitrides or metal alloys;

The upper and lower electrodes in the present invention are made of a single metal material, such as one of W, Pt, Au, Ti, Al, Ag, Cu or Ni, or a combination of alloy materials.

In a word, the present invention provides a brand-new phase-change micro- and nano-electronic memory device structure and a preparation method thereof. Based on the tip effect theory, the invention adopts thin film preparation technology and microfabrication technology to prepare micro-nano electronic memory devices. The characteristics of this device structure are that the structure is simple, the preparation is convenient, the size of the device unit is easy to control, and the miniaturization of the device unit is easy to realize, making it possible for the memory to realize a nanoelectronic device. The invention has high practical value for promoting the practicality of the phase change memory and improving the integration degree of the device.

Description of drawings

Figure 1 Schematic diagram of the structure of phase-change micro- and nano-electronic memory devices (top-view sectional view, the section position is marked E in Figure 2)

Figure 2 Sectional view of the micro- and nanoelectronic memory device unit (marked A in Figure 1)

Fig. 3 cross-sectional view of micro- and nanoelectronic memory device unit (marked B in Fig. 1)

Fig. 4 cross-sectional view of micro- and nanoelectronic memory device unit (marked C in Fig. 1)

Fig. 5 cross-sectional view of micro- and nanoelectronic memory device unit (mark D in Fig. 1)

Figure 6 The substrate after cleaning

Figure 7 Preparation of the first thermal insulation layer film

Figure 8 Preparation of phase change layer film

Figure 9 Preparation of Phase Change Layer Graphics

Fig. 10 Preparation of a phase change layer containing a small figure with a tip

Figure 11 Adjusting the size of the tip

Figure 12 first cover the concave groove in Figure 11, and then prepare the second heat insulating layer film

Figure 13 First prepare the second heat insulating layer film, and then process the concave groove

Figure 14 Drilling holes in the first and second insulation layers

Figure 15 Preparation of transition layer in the concave groove of the second insulation layer

Figure 16 Preparation of electrode layer film

Figure 17 CMP polishing to prepare upper and lower electrodes

Figure 18 When the second heat insulating layer is air and other gases, the top view of the device unit after CMP polishing to prepare the upper and lower electrodes

Figure 19 Device cell with only one memory cell

Figure 20 is a cross-sectional view of a device unit containing only one memory cell, and the cross-sectional position is the same as that in Figure 4

Schematic diagram of the specific meanings represented by different color graphics in Figure 1 to Figure 20

100下电极            500第一绝热层

100 electrodes 500 first insulation layer

200相变层           

600衬底

200 phase change layer

600 substrates

300 second insulation layer 700 transition layer

400上电极

400 upper electrode

Detailed ways

Example 1

The substrate is made of silicon material. After the substrate is cleaned (Fig. 6), the first heat-insulating layer-SiO ₂ thin film is prepared by thermal oxidation (Fig. 7). The preparation process is as follows: the background pressure is 3×10 ^-4 Pa, and The Ar gas pressure was 0.3Pa, the sputtering power was 150W, the substrate temperature was 25°C, and the film thickness was 40nm; the Ge ₂ Sb ₂ Te ₅ chalcogenide phase transition was prepared on the SiO ₂ film by magnetron sputtering thin film (Fig. 8), the process parameters are: the background pressure is 3×10 ^-4 Pa, the Ar gas pressure is 0.15Pa during sputtering, the sputtering power is 100W, the substrate temperature is 25°C, and the film thickness is 20nm; A square Ge ₂ Sb ₂ Te ₅ chalcogenide film was prepared by electron beam exposure method (Figure 9), and the side length of the square was 300nm; the center of the Ge ₂ Sb ₂ Te ₅ chalcogenide compound film was etched by electron beam exposure method. A circle (Figure 10), the diameter of the circle is 310nm, the etching depth is 20nm, the center of the circle coincides with the center of the square; a groove is etched in the middle of the square by electron beam exposure (Figure 11), To adjust the size of the tip, the length of the groove is 300nm, the opening width is 180nm, the slope of the groove side wall is 70 °, and the depth of the groove is 20nm; adopt the magnetron sputtering method to prepare the second thermal insulation layer- _SiO2 thin film (Figure 13 ), the preparation process is the same as above, and the thickness of the film is 15nm; four rectangular holes (Fig. 200nm, the depth is 75nm, the side wall of the hole is inclined outward, and the inclination angle is 70°; use the mask plate technology to deposit a layer of TiW transition layer by sputtering only in the rectangular area (Figure 15), and the preparation process is as follows: The base pressure is 3×10 ^-4 Pa, the Ar gas pressure is 0.12Pa during sputtering, the sputtering power is 80W, the substrate temperature is 25°C, and the film thickness is 5nm; a layer of W film is deposited by magnetron sputtering ( Figure 16), the preparation process is as follows: the background pressure is 3×10 ^-4 Pa, the Ar gas pressure is 0.2Pa during sputtering, the sputtering power is 200W, the substrate temperature is 25°C, and the film thickness is 90nm; finally, CMP The polishing method polished the surface of the sample to the SiO ₂ film of the second heat insulating layer ( FIG. 17 ), the polishing thickness was 95nm, and prepared four independent lower electrodes and one rectangular upper electrode. Through the above preparation process, a micro-nanoelectronic memory device unit has been prepared. The size of the chalcogenide phase-change film in the device unit is: the width of the tip (the trigger point for the phase transition of the chalcogenide compound) is 24nm, and the thickness is 24nm. 20nm, the width of the lower electrode terminal is 100nm, the thickness is 20nm, and the length between the above two terminals is 60nm, forming a nanoelectronic storage unit. The device unit is formed by integrating the memory unit with CMOS, and then connecting it with the readout circuit, and a complete device can be prepared by arranging multiple device units in rows and columns.

Example 2

If the substrate in Example 1 is changed to W, and only one of the four lower electrodes in the device unit is retained, and the side length of the square is lengthened, a single device memory unit with a tip can be easily prepared in a large scale. , this device unit can be used to study the electrical properties of phase transitions at the nanoscale, as shown in Figure 19. Fig. 20 is a sectional view at the same position as Fig. 4 . The side length of the square in Fig. 19 is 10.00 μm; the diameter of the circle is 14.00 μm. The dimensions of the Ge ₂ Sb ₂ Te ₅ chalcogenide phase change film in the obtained device unit are: the thickness is 20nm, the width of the tip (the trigger point where the chalcogenide phase transition occurs) is 41nm, and the width of the terminal connected to the lower electrode is 101nm, the distance between the tip and the lower electrode is 60nm. The width of the upper electrode was 9.88 μm. Other relevant preparation processes and parameters are the same as those in Example 1.

Example 3

One or all of the first and second heat insulating layers in Embodiment 1 are changed to Si ₃ N ₄ thin films, and the rest are the same as Embodiment 1.

Example 4

One or all of the first and second heat insulating layers in Embodiment 2 are changed to Si ₃ N ₄ thin films, and the rest are the same as Embodiment 2.

Example 5

Change the electron beam exposure method in embodiment 1, embodiment 2, embodiment 3, embodiment 4 into focused ion beam etching method, and the rest are respectively the same as embodiment 1, embodiment 2, embodiment 3, embodiment 4 same.

Example 6

Change Ge ₂ Sb ₂ Te ₅ chalcogenides in embodiment 1, embodiment 2, embodiment 3, embodiment 4, embodiment 5 into Sb ₂ Te ₃ chalcogenides, and the rest are respectively the same as embodiment 1, implementation Example 2, embodiment 3, embodiment 4, embodiment 5 are the same.

Example 7

Change the TiW transition layer in embodiment 1, embodiment 2, embodiment 3, embodiment 4, embodiment 5, embodiment 6 into a TiN thin film, and the rest are respectively the same as embodiment 1, embodiment 2, embodiment 3, Embodiment 4, embodiment 5, embodiment 6 are identical.

Claims (14)

1, a kind of phase transformation is little, the nano-electron storage component part, it is by little, nano-electron memory device unit repeated arrangement, and the integrated formation of circuit is selected in complementary metal monoxide semiconductor structure in each device cell and the substrate and addressing, it is characterized in that described phase transformation is little, the nano-electron memory device unit is by the ground floor heat insulation layer that covers on the substrate, cover phase change layer and transition zone on the ground floor heat insulation layer, cover second heat insulation layer on the phase change layer, connect the bottom electrode of substrate and phase change layer and cover top electrode on the described transition zone, top electrode is connected with phase change layer and is constituted; Two figures embed mutually on phase change layer, are partitioned into the little figure of phase change layer, and each little figure contains a tip at least, and most advanced and sophisticated and upper and lower electrode is connected; The described transition zone of deposition in the Baltimore groove of second heat insulation layer.

2, little, the nano-electron storage component part of the described phase transformation of claim 1 is characterized in that:

(1) described substrate is glass, plastics, metal material or crystalline material;

(2) described first heat insulation layer is a kind of in oxide and the nitride;

(3) described second heat insulation layer is oxide or nitride;

(4) described phase change layer is a chalcogenide compound;

(5) described transition zone is a kind of in nitride and the metal alloy;

(6) described upper and lower electrode is a kind of among W, Pt, Au, Ti, Al, Ag, Cu and the Ni, or the alloy material of its combination.

3, by claim 1 or little, the nano-electron storage component part of 2 described phase transformations, it is characterized in that described substrate is silicon chip, GaAs or SiO ₂

4, by claim 1 or little, the nano-electron storage component part of 2 described phase transformations, it is characterized in that the first heat insulation layer thickness is 5-200nm; The second heat insulation layer thickness is 5-100nm; Phase change layer thickness is 2-200nm; Transition region thickness is 2-50nm.

5, by described little, the nano-electron storage component part of claim 1, it is characterized in that each self-separation of bottom electrode of adjacent devices unit in the device, or two shared bottom electrodes of device cell; Described little, nano-electron storage component part contains a device cell at least, but and device cell inverse conversion takes place between two kinds of different resistance states.

6,, it is characterized in that the shape that is shaped as rule of described two figures that embed mutually by little, the nano-electron storage component part of the described phase transformation of claim 1.

7,, it is characterized in that described figure is square, circle, rectangle, polygon or annular by claim 1 or little, the nano-electron storage component part of 6 described phase transformations.

8, it is little to make phase transformation as claimed in claim 1, the method of nano-electron storage component part, it is characterized in that adopting thin film preparation process on substrate, to prepare heat insulation layer, phase change layer, transition zone and electrode layer, utilize fine process to prepare then and contain the little of tip, the nano-electron memory device unit, one or more little, nano-electron memory device unit repeated arrangement, and described each is little, it is little that complementary MOS structures in nano-electron memory device unit and the substrate and addressing selection circuit integrate formation, the nano-electron storage component part.

9, by the manufacture method of little, the nano-electron storage component part of the described phase transformation of claim 8, it is characterized in that concrete manufacturing process steps is:

(1) cleans substrate;

(2) preparation first heat insulation layer on substrate;

(3) on first heat insulation layer, prepare phase change layer;

(4) two groups of figures of preparation in phase change layer with regular shape, and this two block graphics is embedded mutually, prepare and contain most advanced and sophisticated figure;

(5) preparation second heat insulation layer on little figure;

(6) prepare the bottom electrode that is connected with phase change layer;

(7) prepare the top electrode that is connected with phase change layer;

(8) described each is little, the integrated of circuit selected in nano-electron memory device unit and complementary MOS structures and addressing.

10, by the manufacture method of little, the nano-electron storage component part of the described phase transformation of claim 9, it is characterized in that described cleaning substrate, at first silicon chip is immersed in the acetone cleaning fluid with supersonic generator ultrasonic cleaning 5-10min; Take out silicon chip after the ultrasonic cleaning, with pure water rinsing 3-4 time; Again hydrogen peroxide, ammoniacal liquor and pure water are mixed with cleaning fluid by 1: 1.5: 5 volume ratio, silicon chip is immersed back heating in this cleaning fluid, boiled until cleaning fluid; Sample pure water rinsing 3-4 time taken out in the cooling back; Being hydrogen peroxide, concentration 40% hydrochloric acid and pure water then is mixed with cleaning fluid by 1: 1.5: 5 volume ratio, and silicon chip is immersed back heating in this cleaning fluid, is boiled until cleaning fluid; Sample pure water rinsing 3-4 time taken out in the cooling back; Soak 5-10min with hydrofluoric acid solution at last, hydrofluoric acid solution is with the volume ratio preparation by 1: 10 of 40% hydrofluoric acid and pure water, carries out promptly can be used for after the oxidation processes preparation of relevant film after silicon chip takes out.

11, by the manufacture method of little, the nano-electron storage component part of the described phase transformation of claim 9, it is characterized in that concrete preparation process is:

(a). any one in employing sputtering method, evaporation, plasma ion assisted deposition method, chemical vapour deposition technique and the laser assistant depositing method thin film preparation process, on through the substrate after cleaning, prepare by SiO ₂Or Si ₃N ₄The ground floor heat insulation layer that layer constitutes;

(b). on first heat insulation layer of step (a) preparation, adopt in sputtering method, evaporation, plasma ion assisted deposition method, chemical vapour deposition technique and the laser assistant depositing method thin film preparation process a kind of arbitrarily, the preparation phase change layer;

(c). a kind of arbitrarily in employing electron beam lithography, electron beam exposure, extreme ultraviolet photolithographic, focused-ion-beam lithography, ion etching, the nano imprint lithography fine process, phase change layer is prepared into figure with regular shape;

(d). any one in employing electron beam lithography, electron beam exposure, extreme ultraviolet photolithographic, focused-ion-beam lithography, ion etching and the nano imprint lithography fine process, in the phase transformation figure that step (c) has prepared, prepare the figure that another has regular shape, and two figures are embedded mutually, simultaneously the phase change layer of two overlapped parts of figure is removed, has most advanced and sophisticated little figure until exposing first heat insulation layer, preparing;

(e). adopt in electron beam lithography, extreme ultraviolet photolithographic, focused-ion-beam lithography, electron beam exposure, ion etching and the nano imprint lithography fine process any one again, the tip of graphics processing, size in order to control figure tip, process a Baltimore groove in foursquare central authorities, the Baltimore groove A/F is more than or equal to the width of bottom land, the A/F of groove is 10-3000nm, and the sidewall draft angles of groove is 45-90 °, and the height of groove is identical with phase change layer thickness; By the most advanced and sophisticated size of locating of the width adjustment that changes Baltimore groove, its width is controlled at the 2-100nm scope, and thickness is the thickness of phase change layer;

(f). any one in employing sputtering method, evaporation, plasma ion assisted deposition method, chemical vapour deposition technique and the laser assistant depositing method thin film preparation process, preparation second layer heat insulation layer; Perhaps utilize the mask plate technology that the Baltimore groove zone in the step (e) is covered, prepare second layer heat insulation layer again, obtain required figure; Perhaps the whole surface in Baltimore groove zone is all covered second layer heat insulation layer, adopt in electron beam lithography, extreme ultraviolet photolithographic, focused-ion-beam lithography, electron beam exposure and the ion etching fine process any one then, the heat insulation layer that covers the Baltimore groove zone is removed, until the phase change layer that exposes the groove two side, obtain required figure equally;

(g). adopt fine process, process the zone of preparation electrode, in second heat insulation layer and first heat insulation layer, punch, the hole be shaped as looping pit, or polygonal hole, the radially full-size in hole is 50-5000nm, the height in hole is slightly larger than first heat insulation layer and the second heat insulation layer thickness sum; The A/F in hole is 10-500nm, and length is 50-1000nm, and the sidewall draft angles in hole is 45-90 °;

(h). adopt a kind of in sputtering method, evaporation, plasma ion assisted deposition method, chemical vapour deposition technique and the laser assistant depositing method thin film preparation process, utilize the mask plate technology in step (f) Baltimore groove, to prepare transition zone;

(i). any one in employing sputtering method, evaporation, plasma ion assisted deposition method, chemical vapour deposition technique and the laser assistant depositing method thin film preparation process, the preparation electrode film, electrode is an electric conducting material, film thickness is 5-500nm;

(j). adopt CMP (Chemical Mechanical Polishing) process, be polished to second heat insulation layer, obtain independently electrode; The electrode at four drift angle places is a bottom electrode, is 10-700nm highly, and scheming central rectangular electrode is top electrode, highly is 5-500nm;

(k). after 10 preparation process of above step (a)～(j), obtained simple little, nano-electron memory device unit, obtain at last comprising four memory cell in the device cell of described little, nano-electron memory, and each memory cell all with substrate in complementary MOS structures and addressing select circuit to integrate well; With this device cell is repetitive, can obtain little, nano-electron storage component part according to arrayed, and the bottom electrode of adjacent devices unit can be each self-separation in the device, or two shared bottom electrodes of device cell.

12. by claim 9 or 11 described phase transformations are little, the manufacture method of nano-electron storage component part, when it is characterized in that described second insulating barrier is air dielectric, need be chemically mechanically polished to phase change layer, obtain absolute electrode.

13,, it is characterized in that the figure of described regular shape is circle, square, rectangle, polygon or annular by the preparation manufacture method of little, the nano-electron storage component part of the described phase transformation of claim 11.

14, by the manufacture method of little, the nano-electron storage component part of the described phase transformation of claim 13, it is characterized in that foursquare embedded figure when circular, circular diameter is greater than the foursquare length of side.

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