CN100356527C - Method for making MOS transistor with source-drain on insulating layer - Google Patents
Method for making MOS transistor with source-drain on insulating layer Download PDFInfo
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- CN100356527C CN100356527C CNB2005100863238A CN200510086323A CN100356527C CN 100356527 C CN100356527 C CN 100356527C CN B2005100863238 A CNB2005100863238 A CN B2005100863238A CN 200510086323 A CN200510086323 A CN 200510086323A CN 100356527 C CN100356527 C CN 100356527C
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Abstract
The present invention discloses a method for preparing an MOSFET transistor with source drain on an insulating layer. A gate electrode pattern is formed on a substrate material according to the conventional MOSFET process, and then, the ion implantation doping is carried out by using the gate electrode pattern as a mask. A surface layer with the low doped surface, and a buried layer with the high doped inside are formed at a source drain, and then side walls are formed on both sides of the gate electrode. The side walls are used as masks, and grooves are respectively arranged on both sides of the source drain in order to expose the high doped buried layer. Then, a high doped layer under the source drain is etched off by utilizing a doped selective etching technology, and next, a hole left after the etching are filled with a medium to form an insulating layer under the source drain. Thus, the MOSFET transistor with the source drain on the insulating layer is realized.
Description
Technical field:
The invention belongs to semiconductor integrated circuit and manufacturing technology field thereof, relate in particular to a provenance and leak the manufacture method that is positioned at the mosfet transistor on the insulating barrier.
Background technology:
The mainstream technology of current integrated circuit is complementary metal oxide semiconductors (CMOS) (CMOS) technology.And Moore's Law and scaled theory are deferred in the development of CMOS technology always.Along with constantly dwindling of device size, the performance of MOS device and the integration density of integrated circuit improve constantly, and make the integrated circuit (IC) products function from strength to strength, and product price constantly reduce.At present, the characteristic size of MOS device has entered nanoscale.New physical effect produces increasing influence to the MOS device of nanoscale, and meanwhile traditional device preparation technology also runs into new challenge.In order to keep the validity of Moore's Law, when device size is scaled, improve the performance of device, new device architecture and preparation method are constantly proposed.Silicon on the insulator (SOI) technology is exactly wherein a kind of, and SOI especially UTB can be good at suppressing short channel effect, improves the performance of device.But, distinctive floater effect of SOI device and self-heating effect have been produced like this because the existence of insulating barrier makes not only electric isolation also heat isolation simultaneously between device service area and the substrate.One provenance is leaked and to be positioned on the insulating barrier and the mosfet transistor that raceway groove links to each other with substrate is suggested and is used to solve the buoyancy aid of SOI device and from heating problems.Because channel region directly links to each other with substrate, therefore no longer include the buoyancy aid problem that carrier accumulation exists, and heat can dissipate away also by substrate.
Summary of the invention:
The purpose of this invention is to provide a kind of source for preparing and leak the method that is positioned at the mosfet transistor on the insulating barrier.
Technical scheme of the present invention is as follows:
One provenance is leaked the manufacture method of the MOS transistor on insulating barrier, may further comprise the steps:
(1) on Semiconductor substrate, forms the shallow-trench isolation place;
(2) growth gate dielectric layer;
(3) deposit gate electrode layer and sacrificial dielectric layer, then the sacrificial dielectric layer of photoetching and the deposit of etching institute, gate electrode layer form gate electrode figure;
(4) be that mask carries out the ion injection with the gate electrode figure, high doping content distributes in the source leak forms the low body in surface;
(5) side wall medium layer is sacrificed in deposit, and Hui Kehou forms side wall in the gate electrode both sides, be that mask corrosion falls gate dielectric layer with gate electrode and the side wall figure that forms, and the both sides substrate surface is exposed;
(6) corrode the substrate that is exposed, stop corrosion during to heavily doped layer;
(7) selective etching high-doped zone, this corrosion stops when arriving low-doped channel region certainly;
(8) deposit dielectric to fill the cavity that etching forms, returns the dielectric of carving the removal surface;
(9) erode the sacrificial dielectric layer at gate electrode both sides and top, and then deposit or thermal oxide growth form another film dielectric layer;
(10) ion implantation doping source-drain area and gate electrode return then to engrave and state film dielectric layer to form new gate electrode side wall;
(11) enter the conventional cmos later process at last, comprise deposit passivation layer, opening contact hole and metallization etc., can make described MOS transistor.
In the above-mentioned manufacture method, the backing material in the described step (1) is selected from Si, Ge, SiGe, GaAs or other II-VI, the binary and the ternary semiconductor of III-V and IV-IV family.
Above-mentioned manufacture method, the gate dielectric layer material in the described step (2) is a silicon dioxide.
Above-mentioned manufacture method, the method for described step (2) growth gate dielectric layer is selected from one of following method: conventional thermal oxidation, nitrating thermal oxidation, chemical vapor deposition, physical vapor deposition.
The sacrificial dielectric layer material is a silicon nitride in the above-mentioned manufacture method, described step (3), and perhaps other all has high corrosion to select the thin-film material of ratio with silicon and silica.
Sacrificing the side wall medium layer material in the above-mentioned manufacture method, described step (5) is silicon nitride, and perhaps other all has high corrosion to select the thin-film material of ratio with silicon and silica.
Etchant solution is hydrofluoric acid and nitric acid system in the above-mentioned manufacture method, described step (7), and perhaps other has high corrosion to select the etchant solution prescription of ratio to semi-conducting materials such as doped silicons.
Above-mentioned manufacture method, the dielectric in the described step (8) is silicon dioxide or silicon nitride.
Above-mentioned manufacture method, the thickness of the gate dielectric layer of growing on the described substrate are 1-1.5nm; The thickness of gate electrode layer is 80-150nm; The thickness of sacrificial dielectric layer is 20-40nm; The thickness of sacrificing side wall medium layer is 30-150nm; The lateral wall width that the gate electrode both sides form is 25-150nm; The thickness of film dielectric layer is 5-20nm.
The manufacture method that is positioned at the mosfet transistor on the insulating barrier is leaked in source of the present invention, be after forming gate electrode figure according to conventional MOSFET technology on the backing material, with the gate electrode figure is that mask carries out ion implantation doping, forms low-doped superficial layer in surface and inner highly doped buried layer at the source leak.Form side wall again in the gate electrode both sides, and be that mask leaks the both sides fluting respectively to expose highly doped buried layer in the source with this side wall, utilize selective etching technology that the heavily doped layer under the leakage of source is eroded then to mixing, fill the hole that stays after the corrosion with medium afterwards, the insulating barrier that leaks down in the formation source, thus the mosfet transistor that is positioned on the insulating barrier is leaked in the realization source.
Advantage of the present invention and good effect: mosfet transistor its preparation process of the present invention is compatible mutually with traditional CMOS technology, utilizes from leakage two ends, source fluting doped silicon is carried out selective etching, and this technical process is self aligned.With respect to the manufacture method of annotating the oxygen isolation technology, prepared process of the present invention is utilized the selective etching technology, less heat budget is arranged, can not cause damage simultaneously to the silicon fiml that leak in the source, can guarantee that device has less source to omit living resistance and good short-channel properties, helps improving the performance of device.Simultaneously, it is highly doped that leak in the manufacture method of the present invention because source is mask with the gate figure, thereby selective etching can stop when arriving the low-doped grid area of coverage certainly, and technical process becomes simple and easy to control like this.
Mosfet transistor manufacture method of the present invention, technology is simple, is easy to control, has higher utility, is expected to be applied in the nanometer integrated circuit in future.
Description of drawings:
Fig. 1 has illustrated the processing step of shallow-trench isolation;
Fig. 2 has illustrated the processing step of growth gate dielectric layer;
Fig. 3 has illustrated the processing step that gate electrode forms;
Fig. 4 has illustrated that ion injects the processing step that doping is leaked in the formation source;
Fig. 5 has illustrated gate electrode to sacrifice the processing step that side wall forms;
Fig. 6 has illustrated bulk silicon etching to form the processing step of silicon groove;
Fig. 7 has illustrated the processing step of the highly doped silicon layer of selective etching;
Fig. 8 has illustrated the processing step that the silicon groove is filled;
Fig. 9 has illustrated gate electrode side wall formation for the second time and source to leak the processing step that injects;
Among the figure:
1-silicon substrate 2-shallow-trench isolation
3-gate oxide 4-polysilicon gate
5-silicon nitride 6-ion injects the formation source and leaks heavily doped layer
The 7-RIE etching forms silicon groove 8-selective etching and forms the silicon groove
9-fills the silica 1 0-silicon dioxide side wall of silicon groove
The source region of the drain region 12-device of 11-device
Embodiment:
One specific embodiment of manufacture method of the present invention comprises extremely processing step shown in Figure 9 of Fig. 1:
The crystal orientation of used monocrystalline substrate is (100), and the tagma is initially light dope, adopts conventional cmos shallow-trench isolation fabrication techniques active area isolation layer on silicon substrate, as shown in Figure 1.
The gate dielectric layer of then growing, gate dielectric layer is a silicon dioxide, its thickness is 1-1.5nm.The formation method of gate medium can also be one of following method: conventional thermal oxidation, nitrating thermal oxidation, chemical vapor deposition (CVD), physical vapor deposition (PVD), as shown in Figure 2.
Deposit gate electrode layer polysilicon layer and sacrificial dielectric layer silicon nitride, the thickness of polysilicon layer are 80-150nm, and the thickness of silicon nitride layer is 20-40nm.Then adopt the polysilicon layer and the sacrificial dielectric layer silicon nitride of the deposit of photoetching of conventional cmos technology and etching institute.The gate material of institute's deposit can also be the poly-SiGe alloy, as shown in Figure 3.
Gate electrode with formation is a mask, injects by ion to form the high low-doped double-layer structure of source, gate electrode both sides leakage, and ion implanted impurity is a phosphorus, and implantation dosage is 5e+14/cm
-2, the injection energy is 40KeV, as shown in Figure 4.
With the sacrifice side wall medium layer silicon nitride of LPCVD deposit 30-150nm, then use back quarter (etch-back) technology to form width in the gate electrode both sides be the silicon nitride side wall of 25-150nm.Be the exposed part that mask corrosion falls the grid silicon dioxide layer with gate electrode and the side wall figure that forms then, as shown in Figure 5.
With the sacrificial dielectric layer silicon nitride mask corrosion part that semiconductor body was appeared to form the silicon groove, as shown in Figure 6.The degree of depth of silicon groove is 20-50nm.Owing to the silicon groove makes the dielectric layer silicon nitride with the gate electrode both sides is that mask forms, so its structure and gate electrode are self aligned.
Adopt selective etching technology corroded high doping silicon layer, etchant solution is HF: HNO3: CH3COOH, volume ratio is 1 (40%): 3 (70%): 8 (100%), when arriving the grid boundary, because highly doped zone is mask with the gate electrode, corrode highly doped regional afterreaction and stop certainly, as shown in Figure 7.
Adopt CVD deposit layer of silicon dioxide, in order to fill the beneath silicon groove of source leakage that corrosion brings, the insulating barrier under leak in the formation source, the silicon dioxide that goes back to removal surface at quarter.As shown in Figure 8.Fall the sacrificial dielectric silicon nitride layer of all gate electrode tops and both sides with hot phosphoric acid corrosion, and another thickness of heat growth is the silica dioxide medium layer of 5-20nm, and as resilient coating, low energy ion injects the tagma part of dope gate electrode and gate electrode both sides, and dopant is an arsenic.
Then the described ion of anisotropic dry etch injects resilient coating to form the gate electrode side wall and the tagma is exposed on the surface of gate electrode both sides, as shown in Figure 9.
Enter the conventional cmos later process at last, comprise deposit passivation layer, opening contact hole and metallization etc., can make described source and leak the MOS transistor that is positioned on the insulating barrier.
Claims (10)
1. a provenance is leaked the manufacture method of the MOS transistor on insulating barrier, may further comprise the steps:
(1) on Semiconductor substrate, forms the shallow-trench isolation place;
(2) growth gate dielectric layer;
(3) deposit gate electrode layer and sacrificial dielectric layer, then photoetching and etching form gate electrode figure;
(4) be that mask carries out the ion injection with the gate electrode figure, high doping content distributes in the source leak forms the low body in surface;
(5) side wall medium layer is sacrificed in deposit, and Hui Kehou forms side wall in the gate electrode both sides, and the both sides substrate surface is exposed;
(6) corrode the substrate that is exposed, stop corrosion during to heavily doped layer;
(7) selective etching high-doped zone, this corrosion stops when arriving low-doped channel region certainly;
(8) the deposit dielectric returns the dielectric of carving the removal surface to fill the cavity that etching forms;
(9) erode the sacrificial dielectric layer at gate electrode both sides and top, and then deposit or thermal oxide growth form another film dielectric layer;
(10) ion implantation doping source-drain area and gate electrode return then to engrave and state film dielectric layer to form new gate electrode side wall;
(11) enter the CMOS later process at last, can make described MOS transistor.
2. manufacture method as claimed in claim 1 is characterized in that, the semiconductor substrate materials in the described step (1) is selected from Si, Ge, SiGe, GaAs, or other II-VI, III-V, a kind of in the binary of IV-IV family or the ternary compound.
3. manufacture method as claimed in claim 1 is characterized in that, the gate dielectric layer in the described step (2) is a silicon dioxide.
4. manufacture method as claimed in claim 1 is characterized in that, the method for described step (2) growth gate dielectric layer is selected from one of following method: conventional thermal oxidation, nitrating thermal oxidation, chemical vapor deposition, physical vapor deposition.
5. manufacture method as claimed in claim 1 is characterized in that, the gate electrode layer material in the described step (3) is a polysilicon.
6. manufacture method as claimed in claim 1 is characterized in that, the sacrificial dielectric layer material in the described step (3) is a silicon nitride.
7. manufacture method as claimed in claim 1 is characterized in that, the sacrifice side wall medium layer material in the described step (5) is a silicon nitride.
8. manufacture method as claimed in claim 1 is characterized in that, the etchant solution in the described step (7) is hydrofluoric acid and nitric acid system.
9. manufacture method as claimed in claim 1 is characterized in that, the dielectric of deposit is silicon dioxide or silicon nitride in the described step (8).
10. manufacture method as claimed in claim 1 is characterized in that, the thickness of the gate dielectric layer of growing on the described substrate is 1-1.5nm; The thickness of gate electrode layer is 80-150nm; The thickness of sacrificial dielectric layer is 20-40nm; The thickness of sacrificing side wall medium layer is 30-150nm; The lateral wall width that the gate electrode both sides form is 25-150nm; The thickness of film dielectric layer is 5-20nm.
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| Application Number | Priority Date | Filing Date | Title |
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| CNB2005100863238A CN100356527C (en) | 2005-08-31 | 2005-08-31 | Method for making MOS transistor with source-drain on insulating layer |
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| CNB2005100863238A CN100356527C (en) | 2005-08-31 | 2005-08-31 | Method for making MOS transistor with source-drain on insulating layer |
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| CN100356527C true CN100356527C (en) | 2007-12-19 |
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Families Citing this family (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100440537C (en) * | 2006-04-11 | 2008-12-03 | 北京大学深圳研究生院 | A partially depleted SOI MOS transistor and its manufacturing method |
| CN100414714C (en) * | 2006-07-21 | 2008-08-27 | 北京大学深圳研究生院 | A partially depleted SOI structure MOS transistor and its manufacturing method |
| CN101986435B (en) * | 2010-06-25 | 2012-12-19 | 中国科学院上海微系统与信息技术研究所 | Manufacturing method of metal oxide semiconductor (MOS) device structure for preventing floating body and self-heating effect |
| CN102468147B (en) * | 2010-11-01 | 2017-11-28 | 中芯国际集成电路制造(上海)有限公司 | A kind of method of forming gate of semiconductor devices |
| CN102820320B (en) * | 2011-06-09 | 2015-03-04 | 中芯国际集成电路制造(北京)有限公司 | Silicon-on-semiinsulator semiconductor device and method for manufacturing same |
| CN103035530B (en) * | 2012-06-08 | 2015-12-02 | 上海华虹宏力半导体制造有限公司 | The manufacture method of nmos switch device |
| CN103151269B (en) * | 2013-03-28 | 2015-08-12 | 北京大学 | Prepare the method for source and drain accurate SOI multi-gate structure device |
| CN104576377A (en) | 2013-10-13 | 2015-04-29 | 中国科学院微电子研究所 | Mosfet structure and manufacturing method thereof |
| CN105280697A (en) * | 2014-07-16 | 2016-01-27 | 中国科学院微电子研究所 | Semiconductor device and method for manufacturing the same |
| CN105322011A (en) * | 2014-07-16 | 2016-02-10 | 中国科学院微电子研究所 | Semiconductor device and method for manufacturing the same |
| CN105261647A (en) * | 2014-07-16 | 2016-01-20 | 中国科学院微电子研究所 | Semiconductor device and method for manufacturing the same |
| CN111081764A (en) * | 2019-12-30 | 2020-04-28 | 深圳第三代半导体研究院 | Transistor with embedded source and drain and preparation method thereof |
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| US20040029349A1 (en) * | 2002-07-25 | 2004-02-12 | Yongsoo Cho | Methods of fabricating a MOSFET |
| US20040094797A1 (en) * | 2002-11-18 | 2004-05-20 | Il-Yong Park | MOS transistor having short channel and manufacturing method thereof |
| US20050026379A1 (en) * | 2003-07-31 | 2005-02-03 | Thorsten Kammler | Polysilicon line having a metal silicide region enabling linewidth scaling |
| US20050095796A1 (en) * | 2003-10-31 | 2005-05-05 | Van Bentum Ralf | Technique for forming a transistor having raised drain and source regions with a reduced number of process steps |
| US20050139932A1 (en) * | 2003-12-31 | 2005-06-30 | Cho Yong S. | Transistors of semiconductor devices and methods of fabricating the same |
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2005
- 2005-08-31 CN CNB2005100863238A patent/CN100356527C/en not_active Expired - Fee Related
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20040029349A1 (en) * | 2002-07-25 | 2004-02-12 | Yongsoo Cho | Methods of fabricating a MOSFET |
| US20040094797A1 (en) * | 2002-11-18 | 2004-05-20 | Il-Yong Park | MOS transistor having short channel and manufacturing method thereof |
| US20050026379A1 (en) * | 2003-07-31 | 2005-02-03 | Thorsten Kammler | Polysilicon line having a metal silicide region enabling linewidth scaling |
| US20050095796A1 (en) * | 2003-10-31 | 2005-05-05 | Van Bentum Ralf | Technique for forming a transistor having raised drain and source regions with a reduced number of process steps |
| US20050139932A1 (en) * | 2003-12-31 | 2005-06-30 | Cho Yong S. | Transistors of semiconductor devices and methods of fabricating the same |
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Effective date of registration: 20101207 Address after: 100871 Beijing the Summer Palace Road, Haidian District, No. 5 Co-patentee after: Semiconductor Manufacturing International (Shanghai) Corporation Patentee after: Peking University Address before: 100871 Beijing the Summer Palace Road, Haidian District, No. 5 Patentee before: Peking University |
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