CN100347686C - Circular buffering address generating device and arithmetic device - Google Patents
Circular buffering address generating device and arithmetic device Download PDFInfo
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Abstract
The present invention provides an address generation device and an arithmetic device for the address generation device. The address generation device comprises a first logic circuit, a second logic circuit, a first control circuit, a second control circuit and a selection circuit, wherein the first logic circuit calculates the sum of a source address and address offset to obtain an uncorrected address; the second logic circuit generates a constraint address according to the length of a circulating buffer area to constrain the uncorrected address in the circulating buffer area; the first control circuit compares the base address of the circulating buffer area with the uncorrected address to generate a first control signal; the second control circuit compares the tail address of the circulating buffer area with the uncorrected address to generate a second control signal; the selection circuit selects one of the uncorrected address and the constraint address as corrected address output according to the first control signal and the second control signal. The arithmetic device is characterized in that a register arranged in the arithmetic device is a hidden register; when the operand of other arithmetic devices changes, values in the hidden register are automatically and accordingly updated; therefore, the number of adders is reduced, and the processing speed of address generation operation is increased.
Description
Technical field
The present invention relates to the addressing technique of data handling system, especially relate to a kind of address producing device of circular buffering addressing.
Background technology
In the design of microprocessor and digital information processing system, usually use buffer technology to keep in various signals such as instruction, data.For example the circular buffering addressing is exactly to offer certain zone as cyclic buffer in the internal register of microprocessor and digital information processing system or internal storage, and produce a series of addresses continuously according to certain step change, in certain sector address scope of cyclic buffer, change circularly.When system's addressing exceeds the address realm (on cross the border or under cross the border) of this buffer zone, system will regulate the address of addressing, such as the addressing address is subtracted or increase certainly a buffer length value certainly, the address of addressing can be moved all the time in the scope of buffer zone constraint.Early stage circular buffering addressing is the mode that adopts software programming, earlier the value addition of the value of source address and side-play amount, obtain uncorrected addressing address, again the value of the coboundary of uncorrected addressing address and buffer zone and lower boundary is compared respectively, regulate according to result relatively, the addressing address that obtains revising, and make within its scope that is retained in buffer zone.Adopt software mode to need the addressing address that several instruction cycles just can obtain revising at least, and this can not satisfy the efficiently requirement fast of present microprocessor and digital information processing system far away, and limited/infinite impulse response filter (FIR/IIR) scheduling algorithm that especially often needs in the digital signal processing to handle has very high requirement to speed.Like this, the circular buffering addressing of adopting software mode to realize will inevitably affect to the performance of total system.
Prior art also proposes to realize the circular buffering addressing with hardware mode, a kind of circular buffering address producing device as shown in Figure 1.This device comprises cycle index register 101, offset register 102, base register 103 and length register 104.Wherein, base register 103 is deposited the lowest address (BK) of buffer zone, and length register 104 is deposited the length value (MOD) of buffer zone, the side-play amount (OFFSET) of offset register 102 storage address pointers.Cycle index register 101 is deposited the address (AR) that will visit, and after cyclic buffer being carried out visit, the value of cycle index register 101 changes accordingly, the next address that sensing will be visited at every turn.The first order totalizer 105 that this device is provided with is to be used for carrying out the source address value deposited in the cycle index register 101 and the additive operation of offset value, to obtain a uncorrected addressing address (AR+OFFSET).For this uncorrected addressing address value is remained within the scope of cyclic buffer, uncorrected addressing address value need be compared with plot (BK) and tail location (TOP) of cyclic buffer respectively.Wherein tail location (TOP) is the location superlatively of cyclic buffer, plot and length are carried out addition and produced by a special totalizer 106.Simultaneously, this device also is provided with two comparers 108,109, carries out the comparison operation of plot (BK) and tail location (TOP) of uncorrected addressing address value and cyclic buffer respectively.The operation result of two comparers 108,109 can be controlled multiplexer 107 simultaneously.The result who obtains when comparison operation is greater than the tail location, and multiplexer 107 selection-MOD then deduct the value of a length register 104, i.e. (AR+OFFSET-MOD) to the value of uncorrected addressing address; The result who obtains when comparison operation is less than plot, and multiplexer 107 selection+MOD then add the value of a length register 104, i.e. (AR+OFFSET+MOD) to the value of uncorrected addressing address; When result that comparison operation obtains between plot and tail location, then the value of uncorrected addressing address and 0 addition, i.e. (AR+OFFSET+0).Therefore, also need the addressing address of a totalizer 110 at last to obtain to revise.
This hardware device for addressing adopts multistage totalizer cascade, and make the address remain within the up-and-down boundary of cyclic buffer to the control of multiplexer by comparer, obtain the address of effective cyclic buffer, from having improved the processing speed of addressing to a great extent.Just disclosed a kind of similar design in the United States Patent (USP) (patent No. is US5,623,621).Yet this hardware device for addressing needs three totalizers (on sequential, comparer needs identical time-delay with totalizer) in the AR source address at least on the critical path of the addressing address of revising.The quantity of critical path levels device is severely limited the lifting of the processing speed of address generation level in the system flow waterline, correspondingly, also influenced the processing speed and the performance of entire process system, be difficult to satisfy requirement the computing frequency of higher digital information processing system.
Summary of the invention
The objective of the invention is to overcome the defective that exists in the prior art, a kind of address producing device is provided, by reducing the totalizer quantity on the critical path that produces the address, promote the processing speed that the circular buffering regional address produces operation effectively, thereby improve the computing frequency of total system.
Another object of the present invention is to provide a kind of arithmetic unit that comprises hidden register,, improve the processing speed that promotes circular buffering regional address generation operation effectively, thereby improve the computing frequency of total system by reducing unnecessary assign operation.
According to an aspect of the present invention, provide a kind of address producing device, comprised the address register of depositing source address AR; The offset register of storage address side-play amount OFFSET; With source address AR and the OFFSET addition of address offset amount and obtain not first logical circuit of modified address (AR+OFFSET); Deposit the mode register of cyclic buffer length M OD; Deposit the base register of cyclic buffer plot BK; Deposit the tail location register of cyclic buffer tail location TOP; Produce second logical circuit that modified address not is limited to the constraint address of cyclic buffer according to the circular buffering section length; The cyclic buffer plot is produced the first control circuit of first control signal with modified address comparison not; Cyclic buffer tail location and modified address are not relatively produced the second control circuit of second control signal; With selecting one according to first control signal and second control signal in not modified address and constraint address is the selection circuit of modified address output, wherein, a register in described mode register, base register and the tail location register is a hidden register, and the value of the operand of depositing in this hidden register is by to the operand assignment deposited in other two registers the time or start the calculating of totalizer automatically and obtain when the value of the operand of depositing in other two registers is rewritten.
In above address producing device, described constraint address comprise that modified address not adds the length of cyclic buffer and first address (AR+OFFSET+MOD) that obtains and not modified address deduct the length of cyclic buffer and second address (AR+OFFSET-MOD) that obtains; Described selection circuit is arranged to when first control signal shows that modified address is not less than plot, and selecting first address in the constraint address is modified address; When second control signal showed that modified address is not greater than the tail location, selecting second address in the constraint address was modified address; When first control signal and second control signal showed that modified address is not between plot and tail location, selecting not, modified address was a modified address.
In above address producing device, tail location register is a hidden register, and cyclic buffer tail location is by cyclic buffer plot and the automatic addition of circular buffering section length and obtain.
In above address producing device, include totalizer in described first logical circuit, second logical circuit, first control circuit, the second control circuit, wherein carry out cyclic buffer plot and the automatic addition of circular buffering section length and obtain the totalizer of cyclic buffer tail location operation can be multiplexing with any one totalizer in described first logical circuit, second logical circuit, first control circuit, the second control circuit.
In above address producing device, base register is a hidden register, and the cyclic buffer plot is by cyclic buffer tail location and subtracting each other automatically of circular buffering section length and obtain.
In above address producing device, include totalizer in described first logical circuit, second logical circuit, first control circuit, the second control circuit, wherein carry out cyclic buffer tail location and circular buffering section length subtract each other automatically and obtain the totalizer of cyclic buffer plot operation can be multiplexing with any one totalizer in described first logical circuit, second logical circuit, first control circuit, the second control circuit.
In above address producing device, mode register is a hidden register, and the circular buffering section length is subtracted each other automatically by cyclic buffer tail location and cyclic buffer plot and obtained.
In above address producing device, include totalizer in described first logical circuit, second logical circuit, first control circuit, the second control circuit, carrying out wherein that cyclic buffer tail location and cyclic buffer plot subtract each other automatically and obtain the totalizer of cyclic buffer size operation can be multiplexing with any one totalizer in described first logical circuit, second logical circuit, first control circuit, the second control circuit.
According to a further aspect in the invention, provide a kind of arithmetic unit, comprised at least one register of deposit operation number; , the operand of depositing in described at least one register produces the computing circuit of operation result with being carried out computing, and the adder circuit that the operation result of computing circuit is carried out addition, one in wherein said at least one register is hidden register, when the operand of other arithmetic units by assignment or when changing, the value of the operand of depositing in the described hidden register is upgraded automatically according to the operand of described other arithmetic units.
In above arithmetic unit, when the operand of described other arithmetic units changes, the value of the operand of depositing in the described hidden register be automatically updated into described other arithmetic units operand and or poor.
Address producing device of the present invention provides base register, tail location register and mode register simultaneously, and wherein the value of tail location register can be produced by the automatic computing of the value of base register and mode register, and the totalizer that computing is used can be directly multiplexing with the totalizer in other circuit of address producing device, and the totalizer quantity that the address generation is operated on the critical path is reduced.Simultaneously, to base register or/and mode register when rewriting, the value of tail location register can obtain upgrading automatically, and needn't when carrying out addressing, utilize extra calculating and produce, therefore can improve the processing speed that the address produces operation effectively, thereby improve the travelling speed of whole microprocessor.
Description of drawings
The following drawings is the aid illustration to exemplary embodiment of the present, to the elaboration of the embodiment of the invention, be to disclose feature of the present invention place, but do not limit the present invention in conjunction with the following drawings for further, same-sign is represented respective element or step among the embodiment among the figure, wherein:
Fig. 1 is a prior art address producing device structural drawing.
Fig. 2 is the synoptic diagram of cyclic buffer in one embodiment of the invention.
Fig. 3 is the structural representation of address producing device in one embodiment of the invention.
Fig. 4 is the circuit structure diagram of address producing device in one embodiment of the invention.
Fig. 5 is the circuit structure diagram that produces cyclic buffer tail location in one embodiment of the invention.
Fig. 6 is the circuit structure diagram that produces the cyclic buffer plot in the second embodiment of the invention.
Fig. 7 is the circuit structure diagram that produces the circular buffering section length in the third embodiment of the invention.
The comparison means of Fig. 8 for cyclic buffer tail location and modified address not being compared in one embodiment of the invention.
Embodiment
In one embodiment of the present of invention, in the internal storage of digital information processing system, offer certain zone as cyclic buffer.As shown in Figure 2, between the address 30 to 50 as cyclic buffer, address 30 is made as the initial value of cyclic buffer, promptly plot is represented with BK, 30 of this addresses are deposited in the base register as plot.50 number of addresses that take altogether 21 are the length of cyclic buffer to the address in address 30, represent that with MOD the MOD value leaves in the mode register.Plot BK and cyclic buffer length M OD can carry out assignment with assignment statement and obtain in software.Can be as following assignment statement respectively to base register and mode register assignment.
MOVA＜ARx 〉,＜BK〉and MOVA＜ARy,＜MOD 〉
BK can be arbitrary address value in the internal memory.MOD is rational cyclic buffer length value, here " rationally " meaning is the address realm of this length value less than internal memory, and the end address value of resulting cyclic buffer still remains within the address realm of internal memory behind the length value that adds MOD on the basis of plot BK.The equal presentation address register of ARx and ARy.
The end address value of cyclic buffer is also referred to as the tail location, leaves in the register of tail location, represents with TOP, is label 50 in Fig. 2.The end address value TOP of cyclic buffer is the sightless hidden register of software.It means that TOP is not by the special assignment of the assignment statement of software, but is generated by hardware automatically.The value of TOP is cyclic buffer start address value BK and length value MOD sum.And TOP always is consistent with BK and MOD, that is to say, at every turn to BK or MOD rewrites or when simultaneously BK and MOD being rewritten, TOP can automatically obtain upgrading.The physical circuit that TOP is upgraded will be described hereinafter.
When system need carry out the circular buffering addressing, at first the circular buffering control position in the control register is made as height, expression enters the circular buffering addressing mode.Under the circular buffering addressing mode, the cycle index of in store sensing circular buffering regional address in the address register, cycle index is represented with AR.When carrying out the circular buffering addressing operation, whenever the data access operation of finishing once cycle index address pointed, just need to upgrade cycle index, make its sensing will carry out the address of next step data access operation.Upgrading cycle index at first is to add certain side-play amount on the basis of address register Central Plains cycle index address AR pointed.Side-play amount is represented with OFFSET, leaves in the offset register.The side-play amount OFFSET here can directly be set on software by the programmer.Yet, the cycle index address after AR+OFFSET can not directly obtain upgrading.For the circular buffering addressing, require cycle index address pointed to be positioned at all the time within the scope of cyclic buffer.In other words, the value that requires cycle index is greater than plot BK all the time, simultaneously less than tail location TOP.Therefore, (AR+OFFSET) this value was not defined as uncorrected address with it earlier before determining whether in the cyclic buffer scope.Can calculate (AR+OFFSET-BK) and (AR+OFFSET-TOP) two values earlier,, judge that (AR+OFFSET) is whether in the cyclic buffer scope more respectively according to its symbol.When (AR+OFFSET-BK) symbol for just and (AR+OFFSET-TOP) when negative, (AR+OFFSET) in the cyclic buffer scope, this moment can be (AR+OFFSET) as the address of revising fetch data accordingly operation or direct scheduler register; When (AR+OFFSET-BK) symbol when negative, (AR+OFFSET) not in the cyclic buffer scope, this moment can be (AR+OFFSET) and cyclic buffer length value MOD addition, the address is dropped in the cyclic buffer scope again, and with (AR+OFFSET+MOD) the address output as correction, operation or scheduler register accordingly fetch data; When (AR+OFFSET-TOP) symbol is timing, (AR+OFFSET) not in the cyclic buffer scope, can deduct cyclic buffer length value MOD to (AR+OFFSET) this moment, the address is dropped in the cyclic buffer scope again, and with (AR+OFFSET-MOD) the address output as correction, operation or scheduler register accordingly fetch data.
Figure 3 shows that address producing device structural representation of the present invention.Address producing device can be according to the addressing algorithm of the cyclic buffer of front, the address that output is fast and effeciently revised.Address producing device mainly comprises selects circuit 301, respectively with first logical circuit 302 and second logical circuit 303 of selecting circuit 301 input ends to link to each other, and first control circuit 304 and the second control circuit 305 respectively the selection circuit controlled.First control signal and second control signal of selecting circuit to send according to first control circuit 304 and second control circuit 305 are selected the not modified address and the constraint address of input end, the result of selection promptly send back in the address register as modified address or directly in internal memory addressing carry out data access operation.First logical circuit 302 can carry out summation operation to the side-play amount OFFSET that deposits in the source address AR that deposits in the address register and the offset register, and what obtain is modified address (AR+OFFSET) not.Second logical circuit 303 can calculate the constraint address as one of input end of selecting circuit.The constraint address is to be used for adjusting not modified address, makes at last always can remain within the effective range of cyclic buffer from the modified address of selecting circuit 301 outputs.According to previously described algorithm, the constraint address has two kinds, i.e. first address (AR+OFFSET+MOD) and second address (AR+OFFSET-MOD), the two is used for adjusting not modified address at modified address (AR+OFFSET) not respectively less than race way base address BK with when modified address (AR+OFFSET) is not greater than tail location, race way address TOP.First control circuit 304 not modified address (AR+OFFSET) compares with plot BK, and result relatively sends into the control end of selecting circuit 301 as first control signal; Second control circuit 305 not modified address (AR+OFFSET) compares with tail location TOP, and result relatively sends into the control end of selecting circuit 304 equally as second control signal.
Below in conjunction with Fig. 3 and Fig. 4 address producing device being done one specifies.Select circuit 301 mainly to comprise a multiplexer 361.Its input end has three, and one is the not modified address that first logical circuit 302 is sent, and two is the constraint address that second logical circuit 303 is sent in addition.Control end has two, is respectively second control signal that first control signal that first control circuit 304 sends and second control circuit 305 are sent.Output terminal links to each other respectively with bus with address register, and the modified address of the signal of output for selecting from input end according to control end can leave in the address register or directly be sent to and carry out addressing operation in the internal memory.
First logical circuit 302 mainly is to be made of totalizer 331, obtains not modified address (AR+OFFSET) thereby AR and OFFSET are carried out addition.CSA is carry save adder (carry-save-adder) among Fig. 4, and each CSA and a totalizer constitute an arithmetic unit, and arithmetic unit can carry out additive operation to a plurality of input data, and exports an operation result.Two arithmetic units 343 that second logical circuit 303 adopts that two groups of CSA and two totalizers combine respectively and 353 calculate two kinds and retrain addresses.The arithmetic unit 343 that CSA341 and totalizer 342 combine carries out the computing of first address (AR+OFFSET+MOD), and the arithmetic unit 353 that CSA351 and totalizer 352 combine carries out the computing of second address (AR+OFFSET-MOD).
In the first control circuit 304, the arithmetic unit 313 that CSA311 and totalizer 312 combine is finished (AR+OFFSET-BK) computing, and the operation result of exporting from totalizer 312 is a number that symbol is arranged.First control signal is only got its sign bit, and for example, sign bit is 0, then represent operation result be on the occasion of, modified address (AR+OFFSET) is not greater than plot BK; Sign bit is 1, represents that then operation result is a negative value, and modified address (AR+OFFSET) is not less than plot BK.Correspondingly, first control signal is sent into a control end of multiplexer 361, and first control signal is 1 o'clock, and multiplexer 361 makes a choice, and export for modified address first address (AR+OFFSET+MOD) of getting in the input end constraint address.First control signal is 0 o'clock, need combine the selection of controlling multiplexer 361 with second control signal.
In the second control circuit 305, the arithmetic unit 323 that CSA321 and totalizer 322 combine is finished (AR+OFFSET-TOP) computing, and the operation result of exporting from totalizer 322 is a number that symbol is arranged.Second control signal is only got its sign bit, and for example, sign bit is 0, then represent operation result be on the occasion of, modified address (AR+OFFSET) is not greater than tail location TOP; Sign bit is 1, represents that then operation result is a negative value, and modified address (AR+OFFSET) is not less than tail location TOP.Correspondingly, second control signal is sent into a control end of multiplexer 361, and second control signal is 0 o'clock, and multiplexer 361 makes a choice, and export for modified address second address (AR+OFFSET-MOD) of getting in the input end constraint address.Second control signal is 1 o'clock, and first control signal is 0, and then multiplexer 361 selects the not modified address (AR+OFFSET) of input ends to export as modified address.
In above embodiment, the difference between four arithmetic units 313,323,343,353 is that the tail location register of depositing tail location TOP in arithmetic unit 323 is the sightless hidden register of software.The programmer can't be directly to tail location register assignment, but directly generates tail location TOP automatically by hardware.According to aforesaid algorithm, the value of tail location TOP is cyclic buffer plot BK and cyclic buffer length M OD sum.As seen plot BK in the arithmetic element 313 and the cyclic buffer length M OD in arithmetic element 343 and 353 are software, and promptly the programmer can be according to the actual requirements to its assignment.And, can automatically obtain a definite TOP value as long as to BK and MOD assignment.Referring to Fig. 5, BK and MOD can obtain TOP by the calculating of a totalizer.The totalizer here can be the totalizer 331, the totalizer 342,352 in second logical circuit 303, the totalizer 312 in the first control circuit 304, any one in the totalizer 322 in the second control circuit 305 in first logical circuit 302.BK is automatically finished (BK+MOD) arithmetic operation or/and MOD when rewriting, starts totalizer at every turn, and directly upgrading tail location register with operation result.By carrying out other totalizers in totalizer that generates tail location TOP and the address generating device multiplexing, reduce the address effectively and generated required totalizer, more owing to the arithmetic operation that generates TOP is finished when setting cyclic buffer, and just needn't generate the arithmetic operation of TOP during addressing again, the address of having accelerated cyclic buffer greatly generates processing speed.
Similarly, in the second embodiment of the present invention, only be that with the difference of previous embodiment the base register of depositing plot BK is set to the sightless hidden register of software.As shown in Figure 6, utilize totalizer to calculate the value that (TOP-MOD) upgrades BK at any time automatically.The totalizer here can be the totalizer 331, the totalizer 342,352 in second logical circuit 303, the totalizer 312 in the first control circuit 304, any one in the totalizer 322 in the second control circuit 305 in multiplexing first logical circuit 302.
And in the third embodiment of the present invention, only be that with the difference of previous embodiment the mode register of depositing cyclic buffer length M OD is set to the sightless hidden register of software.As shown in Figure 7, utilize totalizer to calculate the value that (TOP-BK) upgrades MOD at any time automatically.The totalizer here can be the totalizer 331, the totalizer 342,352 in second logical circuit 303, the totalizer 312 in the first control circuit 304, any one in the totalizer 322 in the second control circuit 305 in multiplexing first logical circuit 302.
Fig. 8 has illustrated the principle of work that cyclic buffer tail location TOP and modified address (AR+OFFSET) is not relatively produced second control signal from another angle.Comparison means shown in Figure 8 mainly comprises computing circuit and comparator circuit.Computing circuit is a totalizer in the present embodiment, with cyclic buffer plot (BK) in the base register and circular buffering section length (MOD) addition in the mode register, and the operation result that obtains automatically write tail location register, thereby the tail location TOP that obtains upgrading.Tail location register is a hidden register, and its rewriting is to be carried out automatically by computing circuit, and computing circuit is to carry out arithmetic operation when changing automatically at each plot (BK) or length (MOD).Comparator circuit compares operation and produces second control signal the tail location (TOP) of depositing in the register of tail location and modified address (AR+OFFSET) not.
Present embodiment is just in order further more clearly to describe the present invention, but not limitation of the present invention.For example, the present invention is not limited to specific data handling system, equally also can realize the present invention in other different data handling systems.Be to be understood that the present invention is not limited to the elaboration that embodiment does, anyly all should be encompassed within the spirit and scope of claim of the present invention based on modification of the present invention and equivalent of the present invention.
Claims (8)
1. an address producing device comprises
Deposit the address register of source address AR,
The offset register of storage address side-play amount OFFSET,
With source address AR and the OFFSET addition of address offset amount and obtain not first logical circuit of modified address AR+OFFSET,
Deposit the mode register of cyclic buffer length M OD,
Deposit the base register of cyclic buffer plot BK,
Deposit the tail location register of cyclic buffer tail location TOP,
Produce second logical circuit that modified address not is limited to the constraint address of cyclic buffer according to the circular buffering section length,
The cyclic buffer plot is produced the first control circuit of first control signal with modified address comparison not,
With cyclic buffer tail location and modified address not relatively produce second control signal second control circuit and
Selecting one according to first control signal and second control signal in not modified address and constraint address is the selection circuit of modified address output,
Wherein, a register in described mode register, base register and the tail location register is a hidden register, and the value of the operand of depositing in this hidden register is by to the operand assignment deposited in other two registers the time or start the calculating of totalizer automatically and obtain when the value of the operand of depositing in other two registers is rewritten.
2. address producing device as claimed in claim 1 is characterized in that,
Described constraint address comprise that modified address not adds the length of cyclic buffer and the first address AR+OFFSET+MOD that obtains and not modified address deduct the length of cyclic buffer and the second address AR+OFFSET-MOD that obtains;
Described selection circuit is arranged to when first control signal shows that modified address is not less than plot, and selecting first address in the constraint address is modified address; When second control signal showed that modified address is not greater than the tail location, selecting second address in the constraint address was modified address; When first control signal and second control signal showed that modified address is not between plot and tail location, selecting not, modified address was a modified address.
3. address producing device as claimed in claim 1 is characterized in that, tail location register is a hidden register, and cyclic buffer tail location is by cyclic buffer plot and the automatic addition of circular buffering section length and obtain.
4. address producing device as claimed in claim 3, it is characterized in that, include totalizer in described first logical circuit, second logical circuit, first control circuit, the second control circuit, wherein carry out cyclic buffer plot and the automatic addition of circular buffering section length and obtain the totalizer of cyclic buffer tail location operation can be multiplexing with any one totalizer in described first logical circuit, second logical circuit, first control circuit, the second control circuit.
5. address producing device as claimed in claim 1 is characterized in that, base register is a hidden register, and the cyclic buffer plot is by cyclic buffer tail location and subtracting each other automatically of circular buffering section length and obtain.
6. address producing device as claimed in claim 5, it is characterized in that, include totalizer in described first logical circuit, second logical circuit, first control circuit, the second control circuit, wherein carry out cyclic buffer tail location and circular buffering section length subtract each other automatically and obtain the totalizer of cyclic buffer plot operation can be multiplexing with any one totalizer in described first logical circuit, second logical circuit, first control circuit, the second control circuit.
7. address producing device as claimed in claim 1 is characterized in that, mode register is a hidden register, and the circular buffering section length is subtracted each other automatically by cyclic buffer tail location and cyclic buffer plot and obtained.
8. address producing device as claimed in claim 7, it is characterized in that, include totalizer in described first logical circuit, second logical circuit, first control circuit, the second control circuit, carrying out wherein that cyclic buffer tail location and cyclic buffer plot subtract each other automatically and obtain the totalizer of cyclic buffer size operation can be multiplexing with any one totalizer in described first logical circuit, second logical circuit, first control circuit, the second control circuit.
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| WO2002054227A1 (en) * | 2000-12-29 | 2002-07-11 | Intel Corporation | Modulo addressing |
| US6604169B2 (en) * | 2001-06-01 | 2003-08-05 | Microchip Technology Incorporated | Modulo addressing based on absolute offset |
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