CN109860036A

CN109860036A - Nanowire gate electrode of non-volatile 3D NAND memory and preparation method thereof

Info

Publication number: CN109860036A
Application number: CN201910001812.0A
Authority: CN
Inventors: 缪向水; 杨哲; 童浩
Original assignee: Huazhong University of Science and Technology
Current assignee: Huazhong University of Science and Technology
Priority date: 2019-01-02
Filing date: 2019-01-02
Publication date: 2019-06-07
Anticipated expiration: 2039-01-02
Also published as: CN109860036B

Abstract

The invention discloses a nanowire gate electrode of a non-volatile 3D NAND memory and a preparation method thereof. Each gate electrode unit has a columnar structure; the upper surface of the gate electrode is used for connecting the gate layer, and the lower surface is used for connecting the word line. The nanowire gate electrode structure provided by the present invention connects different ultra-high-level stacks and corresponding gate layers in a stepped shape, and the non-corresponding gate layers and gate electrodes in the stacked layers are separated by an insulating layer, which is suitable for solving the problem of ultra-high-level stacking. The non-volatile 3D NAND memory gate electrode occupies an excessively large area, the bottleneck of ultra-deep hole etching and filling, and thermal crosstalk, and realizes the nanowire electrode structure connecting the ultra-high gate layer stack.

Description

A kind of nanometer wire grid electrodes and preparation method thereof of non-volatile 3D nand memory

Technical field

The invention belongs to technical field of microelectronic devices, more particularly, to a kind of non-volatile 3D nand memory Nanometer wire grid electrodes and preparation method thereof.

Background technique

In order to meet the development of efficient and cheap microelectronic industry, semiconductor memory need to have it is higher integrate it is close Degree.High density is most important for the reduction of semiconductor product cost.For traditional two dimension and planar semiconductor memory, it Integration density depend primarily on unit area shared by single memory device, integrated level is highly dependent on the good of masking process It is bad.But even if constantly improving masking process precision with expensive process equipment, the promotion of integration density remains to be had very much Limit.Especially with the development of Moore's Law, in 22nm process node hereinafter, planar semiconductor memory faces needles of various sizes The problems such as effect, heat dissipation, urgent need to resolve.

As the substitution for overcoming this two-dimentional limit, three-dimensional semiconductor memory is suggested.Three-dimensional semiconductor memory needs There is the technique that can obtain lower manufacturing cost, and positive means structure can be obtained.In 3D NAND (not And, it is non-simultaneously) in type memory, BiCS (Bit Cost Scalable) is considered as that one kind can reduce each unit area Three dimensional nonvolatile memory technology.Technique realized by the design of through-hole and hitching post, and in 2007 It is delivered in VLSI technical brief annual meeting.Using after BiCS technology in nonvolatile semiconductor memory, not only make this storage Device has three-dimensional structure, and makes the reduction of data storage position directly proportional to the stacking number of layer frame.But since this is special Device architecture, still need to solve there are many problem in this present structure.

Its problem of, is mainly reflected in how to be mutually compatible with storage unit with driving circuit.In the memory of BiCS In, although memory cell array is designed to three-dimensional structure, the design of peripheral circuit still maintains traditional two-dimensional structure Design.Therefore in this 3D nand memory, the grid layer that need to be connected to wordline etches step into a ladder by design, then makes The gate electrode structure of standby connection grid layer and wordline.And as stacking number constantly increases, this ladder-like grid layer can expend a large amount of faces Product.And existing improvement vertical gate electrode is continued growing in stacking number can face more severe superdeep holes afterwards to a certain extent Etching and filling problem.Furthermore for vertical gate structure during being written and read, the cross-interference issue of storage unit is relatively serious, and With storage the number of plies increase, cell density increase and it is more significant.Thus existing various gate electrodes are not particularly suited for having super The 3D nand memory that high level stacks.

Summary of the invention

In view of the drawbacks of the prior art, receiving the purpose of the present invention is to provide a kind of non-volatile 3D nand memory Rice noodles gate electrode and preparation method thereof, it is intended to solve to go out after facing stacking number and being continuously increased certain amount in the prior art Existing area dissipates, superdeep holes etch and fills and hot cross-interference issue.

The present invention provides a kind of nanometer wire grid electrodes and preparation method thereof of non-volatile 3D nand memory, including Following step:

(1) gate electrode array is prepared

(1.1) porous alumina formwork is placed on the substrate for having prepared wordline and bit line, is placed in corresponding electricity It chemically reacts in solution, the bore dia range of porous alumina formwork is 5nm~100nm.Pitch of holes is 10nm~500nm, hole Depth is greater than 100nm, and the hole of porous alumina formwork is aligned with wordline；

(1.2) n gate electrode post is formed by electrochemical deposition in porous alumina formwork, is followed successively by first gate electrode Column, the second gate electrode post ... n-th of gate electrode post, first gate electrode column, second the i-th gate electrode of gate electrode post ... Successively into a ladder, height is from low to high for column ... and the n-th gate electrode post；M gate electrode post is formed in same wordline, is constituted The gate electrode array of m*n；Wherein i=3,4 ... n, n be wordline number, n, m be positive integer；Wherein electrochemical reaction solution Built-in graphite electrode, and by the external different driving sources in each wordline junction, regulated and controled by regulation excitation source size from it is different The deposition rate and height of gate electrode post in the alumina formwork hole of word line contact；

(1.3) pass through acid solution erosion removal alumina formwork；

(2) the first control grid layer connecting with first gate electrode column is prepared

(2.1) pass through the smooth insulating layer of CMP to the n-th gate electrode post is covered in gate electrode deposited over arrays insulating layer Upper surface；

(2.2) it is aligned with the first wordline WL0 and carries out lithography and etching, until exposing first gate electrode column；

(2.3) conductive material identical with gate electrode post is deposited on the surface of exposed first gate electrode column, is formed and is served as a contrast Bottom surface is parallel and the first control grid layer for being connected with first gate electrode column；

(3) gate electrode of nonvolatile three-dimensional semiconductor memory is prepared

It repeats the above steps, deposition of insulative material is to being completely covered the n-th gate electrode after the completion of prepared by i-th layer of control grid layer Column is aligned with i-th wordline and carries out a photoetching and insulating layer etching, and in the upper surface sedimentary facies of exposed i-th gate electrode post Same conductive material forms the i-th control grid layer being attached thereto, and forms the grid electricity of the non-volatile 3D nand memory Pole.

Further, can not have to use photoetching, directly progress selective etch in the preparation of the n-th control grid layer, it is naked Expose the n-th gate electrode post, and deposits conductive material identical with the n-th gate electrode post and form the n-th control grid layer.

Wherein, insulating materials is silica, silicon nitride or silicon oxynitride；Conductive material include one or more conductors or Semiconductor material, for example DOPOS doped polycrystalline silicon, tungsten, copper, aluminium, tantalum, titanium, cobalt, titanium nitride or their alloy；Acid solution is hydrogen Sodium hydroxide solution.

As another aspect of the present invention, the present invention also provides a kind of using the non-volatile of above-mentioned preparation method formation Property 3D nand memory nanometer wire grid electrodes, including m*n gate electrode array, formed in same wordline m it is highly identical Gate electrode post, the n gate electrode post along word-line direction successively arrange into a ladder, and each gate electrode post is column structure, grid electricity The upper surface of pole is for connecting grid layer, and lower surface is for connecting wordline.

The present invention constantly rises for stacking number in 3D nand memory, and the etching of superdeep holes and filling become device The bottleneck of performance boost.And electrochemical process can be with the gate electrode of previously prepared different height, then prepares step-like control grid layer. The problem of not only solving superdeep holes etching, it is also ensured that the homogeneity of the size up and down of gate electrode promotes device performance.This Outside, the gate electrode post size of electrochemical process deposition depends on pore size, and minimum feature size can achieve 5 nanometers, Minimum 10 nanometers of pitch of holes.The nanometer gate electrode of dense arrangement reduces area dissipation, and it is close to increase integrating for unit area Degree.And device heat dissipation problem further can be regulated and controled by regulation aperture and pitch of holes.

Detailed description of the invention

Fig. 1 is the structural schematic diagram of non-volatile 3D nand memory provided in an embodiment of the present invention；

Fig. 2 (a) is the structure top view of non-volatile 3D nand memory provided in an embodiment of the present invention；

Fig. 2 (b) is the cross-sectional view of the structure of non-volatile 3D nand memory provided in an embodiment of the present invention；

Fig. 3 is the preparation method step of the nanometer gate electrode of non-volatile 3D nand memory provided in an embodiment of the present invention Schematic diagram of the porous aluminas in conjunction with substrate in rapid one；

Fig. 4 is the preparation method of the nanometer gate electrode of non-volatile 3D nand memory provided in an embodiment of the present invention Gate electrode array structure schematic diagram in step 1；

Fig. 5 is the preparation method of the nanometer gate electrode of non-volatile 3D nand memory provided in an embodiment of the present invention Aluminum modules are aoxidized in step 1 removes step schematic diagram；

Fig. 6 is the preparation method of the nanometer gate electrode of non-volatile 3D nand memory provided in an embodiment of the present invention First insulative material deposition step schematic diagram in step 2；

Fig. 7 is the preparation method of the nanometer gate electrode of non-volatile 3D nand memory provided in an embodiment of the present invention First gate electrode rod structure schematic diagram in step 2；

Fig. 8 is the preparation method of the nanometer gate electrode of non-volatile 3D nand memory provided in an embodiment of the present invention First control grid layer structural schematic diagram in step 2；

Fig. 9 is the preparation method of the nanometer gate electrode of non-volatile 3D nand memory provided in an embodiment of the present invention Second insulative material deposition step schematic diagram in step 3；

Figure 10 is the preparation method of the nanometer gate electrode of non-volatile 3D nand memory provided in an embodiment of the present invention Second gate electrode post structural schematic diagram in step 3；

Figure 11 is the preparation method of the nanometer gate electrode of non-volatile 3D nand memory provided in an embodiment of the present invention Second control grid layer structural schematic diagram in step 3；

Figure 12 is the preparation method of the nanometer gate electrode of non-volatile 3D nand memory provided in an embodiment of the present invention Third insulative material deposition step schematic diagram in step 3；

Figure 13 is the preparation method of the nanometer gate electrode of non-volatile 3D nand memory provided in an embodiment of the present invention Third gate electrode post structural schematic diagram in step 3；

Figure 14 is the preparation method of the nanometer gate electrode of non-volatile 3D nand memory provided in an embodiment of the present invention Third control grid layer structure in step 3；

Figure 15 is the preparation method of the nanometer gate electrode of non-volatile 3D nand memory provided in an embodiment of the present invention 4th insulative material deposition step schematic diagram in step 3；

Figure 16 is the preparation method of the nanometer gate electrode of non-volatile 3D nand memory provided in an embodiment of the present invention 4th gate electrode post structural schematic diagram in step 3；

Figure 17 is the preparation method of the nanometer gate electrode of non-volatile 3D nand memory provided in an embodiment of the present invention 4th control grid layer structural schematic diagram in step 3；

In figure, WLO, WL1, WL2, WL3 are wordline；100 be substrate；200 be more empty alumina formworks；110a,111a, 112a, 113a are followed successively by first to fourth control grid layer；110b, 111b, 112b, 113b are followed successively by first to fourth gate electrode Column.

Specific embodiment

In order to make the objectives, technical solutions, and advantages of the present invention clearer, with reference to the accompanying drawings and embodiments, right The present invention is further elaborated.It should be appreciated that the specific embodiments described herein are merely illustrative of the present invention, and It is not used in the restriction present invention.

The present invention provides a kind of gate electrode structure that can be applied to 3D NAND and technique preparation flows.This gate electrode Structure can carry out the preparation of bit line and wordline in advance, facilitate the interconnection of storage unit and peripheral circuit, and can effectively subtract The crosstalk of few storage unit periphery area and storage unit.

Specific step is as follows for preparation method provided in an embodiment of the present invention:

Such as Fig. 1, shown in Fig. 2 (a), Fig. 2 (b), this gate electrode is the hierarchic structure of cylindric (or square column), from low It arranges, is built in the grid layer and insulating layer of multiple-level stack in the x-direction to height.Each gate electrode has upper and lower surface, wherein The upper surface of gate electrode is connected with corresponding grid layer, and lower surface is connected with corresponding wordline.

The structure of gate electrode can be described by detailed technique preparation flow in this embodiment, now in conjunction with It is as follows that the step of preparation method is described in detail in Fig. 3 to Figure 17:

Step 1: as shown in figure 3, forming bit line BL and wordline WL0, WL1, WL2, WL3 on substrate 100.Wordline patterns The groove for being formed in parallel with substrate can be etched by RIE, deposition respective material fills full groove, by CMP planarization surface, most Wordline WL0, WL1, WL2, WL3 of strip are formed afterwards, and wherein wordline width is 22nm~110nm.

Step 2: placing porous alumina formwork 200, hole on the substrate 100 for having prepared wordline WL and bit line BL Diameter is 5nm~100nm, and pitch of holes is 10nm~500nm, and hole depth is greater than 100nm, the hole of porous alumina formwork 200 and wordline WL alignment, is placed in corresponding electrochemical reaction solution, graphite electrode built in electrochemical reaction solution, and each wordline is connected The external different driving sources in place are connect, are regulated and controled in 200 hole of alumina formwork from different word line contacts by regulation excitation source size The deposition rate and height of gate electrode post, as shown in figure 4, ultimately form gate electrode post 110b, 111b of 3*4 array, 112b, 113b.Then as shown in figure 5, removal alumina formwork 200.

Step 3: as shown in fig. 6, deposition first layer insulating materials 300 passes through CMP to the 4th gate electrode post 113b of covering The surface of smooth packing material.It is aligned with first wordline WL0 and carries out a lithography and etching, until exposing first gate electrode Column 110b, as shown in Figure 7.Conductive material identical with gate electrode post is deposited on the surface of exposed first gate electrode column 110b, The first control grid layer 110a that is parallel with 100 surface of substrate and being connected with first gate electrode column 110b is formed, as shown in Figure 8.

Step 4: being sequentially completed the preparation of remaining control grid layer according to the preparation method of above-mentioned first control grid layer, specifically Preparation process as shown in Fig. 9 to 17.Ultimately form the gate electrode of stepped upright substrate.Wherein gate electrode has both ends, grid electricity The first end of pole is contacted with wordline WL and is aligned, and the second end of gate electrode is contacted with corresponding grid layer.To by gate electrode come Realization storage unit is connected to peripheral gating circuit.

In above-mentioned step three, the method for deposition can use sputtering, CVD, MBE etc..Deposition forms first gate electrode The material of column is the stronger material of electric conductivity such as DOPOS doped polycrystalline silicon, tungsten, copper, aluminium, tantalum, titanium, cobalt, titanium nitride or their conjunction Gold.

The preparation of this gate electrode is different from the preparation of the ladder gate layer in existing structure, needs to complete after the preparation of device again The connection with peripheral circuit is carried out to prepare.Adopting can carry out on peripheral circuit substrate well prepared in advance with the aforedescribed process Subsequent device preparation technology generates pollution to reduce journey peripheral circuit preparation and three-dimensional semiconductor memory device is formed The introducing of equal undesirable elements.

As it will be easily appreciated by one skilled in the art that the foregoing is merely illustrative of the preferred embodiments of the present invention, not to The limitation present invention, any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should all include Within protection scope of the present invention.

Claims

1. a preparation method of the nanowire gate electrode of a non-volatile 3D NAND memory, is characterized in that, comprises the following steps:

(1) Preparation of grid electrode array

(1.1) placing a porous alumina template (200) on the substrate (100) on which wordlines and bitlines have been prepared, and the holes of the porous alumina template (200) are aligned with the wordlines;

(1.2) forming n gate electrode pillars by electrochemical deposition in the porous alumina template (200), which are the first gate electrode pillar (110b), the second gate electrode pillar (111b), the nth gate in sequence electrode pillars (11(n-1)b), the first gate electrode pillars (110b), the second gate electrode pillars (111b), the i-th gate electrode pillars (11(i-1)b), and the The nth gate electrode column (11(n-1)b) is stepped in sequence, and the height is from low to high; m gate electrode columns are formed on the same word line to form an m*n gate electrode array;

where i=3, 4, ... n, n is the number of word lines, and n and m are positive integers;

(1.3) removing the alumina template (200) by etching with an acid solution;

(2) preparing a first control gate layer (110a) connected to the first gate electrode column (110b)

(2.1) depositing an insulating layer (300) on the gate electrode array to cover the nth gate electrode column (11(n-1)b), and smoothing the upper surface of the insulating layer (300) by CMP;

(2.2) performing a photolithography and etching in alignment with the first word line WL0 until the first gate electrode column (110b) is exposed;

(2.3) Deposit the same conductive material as the gate electrode column on the surface of the exposed first gate electrode column (110b) to form a surface parallel to the substrate (100) and connected to the first gate electrode column (110b) the first control gate layer (110a);

(3) Preparation of gate electrode of non-volatile three-dimensional semiconductor memory

Repeat the above steps, after the preparation of the i-th control gate layer is completed, deposit an insulating material to completely cover the n-th gate electrode column (11(n-1)b), and align with the i-th word line WL(i-1) to carry out One photolithography and etching, and deposit the same conductive material on the upper surface of the exposed i-th gate electrode pillar (11(i-1)b) to form the i-th control gate layer (11(i-1)a) connected to it ), forming the gate electrode of the non-volatile 3D NAND memory.

2 . The preparation method according to claim 1 , wherein photolithography is not used in the preparation of the nth control gate layer, and selective etching is directly performed to expose the nth gate electrode column, and deposit and the nth gate electrode column. 3 . The same conductive material of the n gate electrode column forms the nth control gate layer.

3 . The preparation method of claim 1 , wherein the porous alumina template has a pore diameter of 5 nm to 100 nm, a pore spacing of 10 nm to 500 nm, and a pore depth greater than 100 nm. 4 .

4. The preparation method according to claim 1, wherein the insulating material is silicon dioxide, silicon nitride or silicon oxynitride.

5. The preparation method of claim 1, wherein the conductive material comprises one or more conductor or semiconductor materials, such as doped polysilicon, tungsten, copper, aluminum, tantalum, titanium, cobalt, nitride Titanium or their alloys.

6. The preparation method of claim 1, wherein the acidic solution is a sodium hydroxide solution.

7. A nanowire gate electrode of a non-volatile 3D NAND memory formed by the preparation method according to any one of claims 1 to 6, characterized in that it comprises m*n gate electrode arrays, and the same word line m gate electrode pillars with the same height are formed on the upper surface, n gate electrode pillars along the word line direction are arranged in a step-like manner, each gate electrode pillar is a pillar-like structure, the upper surface of the gate electrode is used for connecting the gate layer, and the lower The surface is used to connect word lines.