CN109817615B - ESD protection device based on FDSOI gg-NMOS auxiliary trigger - Google Patents

Abstract

The embodiment of the present invention provides an ESD protection device based on FDSOI gg-NMOS assisted triggering. An N-well injection region is arranged in a P-type substrate, and the N-well lead-out region is connected to the drain region, so that the ESD current at the bulk silicon level can be obtained. The discharge capability meets the requirements of the ESD design window of the internal core circuit under the FDSOI process, and can play an effective protective role when ESD arrives.

Description

ESD protection device based on FDSOI gg-NMOS auxiliary trigger

technical field

Embodiments of the present invention relate to the technical field of electrostatic discharge protection for semiconductor integrated chips, and more particularly, to an ESD protection device based on FDSOI gg-NMOS auxiliary triggering.

Background technique

An electrostatic discharge (Electrostatic Discharge, ESD) phenomenon of an integrated circuit is an instantaneous process in which a large amount of electric charge is poured into the integrated circuit from the outside to the inside when the chip is floating. Since the internal resistance of the integrated circuit chip is very low, when the ESD phenomenon occurs, an instantaneous (time-consuming 100-200 nanoseconds, rise time is only about 0.1-10 nanoseconds), high peak (several amperes) current, and A large amount of Joule heat is generated, which will cause the failure of the integrated circuit chip.

For the advanced FDSOI process, the traditional gg-NMOS device structure is limited by the thickness of the silicon film and cannot provide a high enough ESD current discharge capability, and because the existing FDSOI-based gg-NMOS device is not stable under ESD impact Based on the avalanche breakdown, the parasitic npn BJT inside the gg-NMOS device has a relatively high trigger voltage, and the higher trigger voltage cannot meet the requirements of the ESD design window of the internal core circuit under the FDSOI process. Play an effective ESD protection role.

Therefore, there is an urgent need to provide an ESD protection device based on FDSOI gg-NMOS assisted triggering, so as to solve the technical problems existing in the FDSOI-based gg-NMOS device in the prior art.

SUMMARY OF THE INVENTION

To overcome the above problems or at least partially solve the above problems, embodiments of the present invention provide an ESD protection device based on FDSOI gg-NMOS auxiliary triggering.

An embodiment of the present invention provides an ESD protection device based on FDSOI gg-NMOS assisted triggering, including: a P-type substrate, a substrate lead-out region, a buried oxide region, a drain region, a channel region, an N-well implanted region, and an N-well lead-out area;

The substrate lead-out region is arranged on one side of the surface of the P-type substrate, the N-well lead-out region is arranged on the other side of the surface of the P-type substrate, and the buried oxide region is arranged on the surface of the P-type substrate. the upper part of the P-type substrate, and the buried oxide region is located between the substrate lead-out region and the N-well lead-out region;

The drain region is arranged on the buried oxide region near the N-well lead-out region, the channel region is arranged on the buried oxide region, and the drain region is in contact with the channel region, so the drain region is connected to the N well lead-out region;

A part of the N-well implanted region is arranged in the P-type substrate under the N-well lead-out region, and the N-well implanted region extends to the bottom of the buried oxide region, and the N-well implanted region is connected to the N-well implanted region. The coupling area of the channel region is greater than zero.

The embodiment of the present invention provides an ESD protection device based on FDSOI gg-NMOS assisted triggering. An N-well injection region is arranged in a P-type substrate, and the N-well lead-out region is connected to the drain region, so that the ESD current at the bulk silicon level can be obtained. The discharge capability meets the requirements of the ESD design window of the internal core circuit under the FDSOI process, and can play an effective ESD protection role when ESD arrives.

Description of drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the accompanying drawings that need to be used in the description of the embodiments or the prior art. Obviously, the accompanying drawings in the following description These are some embodiments of the present invention. For those of ordinary skill in the art, other drawings can also be obtained according to these drawings without creative efforts.

Fig. 1 is the structural representation of the gg-NMOS device based on FDSOI existing in the prior art;

2 is a schematic structural diagram of an ESD protection device based on FDSOI gg-NMOS auxiliary triggering provided by an embodiment of the present invention;

FIG. 3 shows that the positions of the left boundary of the N-well injection region in an ESD protection device based on FDSOI gg-NMOS assisted triggering according to an embodiment of the present invention are positions (1), (2), and (3) in FIG. 2 . ) when the TLP test data result graph;

FIG. 4 is a TLP test data result diagram when the lengths of gate regions in an ESD protection device based on FDSOI gg-NMOS assisted triggering according to an embodiment of the present invention are different.

Detailed ways

In order to make the purposes, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments These are some embodiments of the present invention, but not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

In the description of the embodiments of the present invention, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer" The orientation or positional relationship indicated by ” etc. is based on the orientation or positional relationship shown in the accompanying drawings, and is only for the convenience of describing the embodiments of the present invention and simplifying the description, rather than indicating or implying that the indicated device or element must have a specific orientation, It is constructed and operated in a particular orientation and therefore should not be construed as a limitation of the embodiments of the present invention. Furthermore, the terms "first", "second", and "third" are used for descriptive purposes only and should not be construed to indicate or imply relative importance.

As shown in FIG. 1, FIG. 1 is a schematic structural diagram of an FDSOI-based gg-NMOS device existing in the prior art, including: a P-type substrate 100, the substrate lead-out region 111 and the buried oxide region 102 are both arranged on the P-type substrate On the upper surface of the base 100 , a metal region 112 is provided on the substrate lead-out region 111 . The substrate lead-out region 111 is a P+ implantation region, and the buried oxide region 102 is a BOX layer. An active region 103 , a channel region 105 and a drain region 104 are provided on the buried oxide region 102 . The source region 103 is an N+ implantation region, the channel region 105 is a P--type doped region, and the drain region 104 is an N+ implantation region. A metal region 109 is provided on the source region 103 , and a gate region 106 is provided on the channel region 105 . A metal region 107 is provided on the drain region 104 . The metal region 107 is connected to the electrostatic input terminal V _ESD , the metal regions 112 , 109 and the gate region 106 are all grounded to G _ND , the metal region 109 serves as a source, and the metal region 107 serves as a drain.

As shown in Figure 1, the gg-NMOS device based on FDSOI works when an ESD shock occurs at the electrostatic input terminal V _ESD : when the ESD shock arrives, the gg-NMOS device is in a closed state and does not discharge current, so that the leakage current occurs. A relatively high voltage will be formed in the region 104. When the voltage reaches the avalanche breakdown voltage of the reverse pn junction formed by the channel region 105 and the drain region 104, a large number of unbalanced carriers will be formed in the drain region 104, and in the drain region 104, etc. Under the action of the high-efficiency electric field, it moves to the source region, and gradually accumulates a higher potential at the bottom of the channel region 105. When the voltage is higher than the pn turn-on voltage formed by the channel region 105 and the source region, the internal gg-NMOS device based on FDSOI The parasitic npn BJT turns on, conducting ESD current to ground _GND .

Because the existing FDSOI-based gg-NMOS device is turned on based on avalanche breakdown under ESD impact, it has a relatively high trigger voltage, which cannot meet the ESD design window of the internal core circuit under the FDSOI process, and cannot provide effective ESD Protect. Therefore, the embodiment of the present invention provides an ESD protection device based on FDSOI gg-NMOS auxiliary triggering.

As shown in FIG. 2, the ESD protection device based on FDSOI gg-NMOS assisted triggering provided in the embodiment of the present invention includes: a P-type substrate 200, a substrate lead-out region 211, a buried oxide region 202, a drain region 204, a channel region 205 , N-well implant region 210 and N-well lead-out region 201 . The substrate lead-out region 211 is disposed on one side of the surface of the P-type substrate 200 , the substrate lead-out region 211 is a P+ injection region, and the substrate lead-out region 211 is grounded to G _ND . The N-well lead-out region 201 is disposed on the other side of the surface of the P-type substrate 200 , the buried oxide region 202 is disposed on the upper portion of the P-type substrate 200 , and the buried oxide region 202 is located in the substrate lead-out region 211 and the N-well lead-out region 201 between. The substrate lead-out region 211 is grounded to G _ND , and the buried oxide region 202 is the BOX layer.

The drain region 204 is arranged on the buried oxide region 202 near the N-well lead-out region 201 , the channel region 205 is arranged on the buried oxide region 202 , and the drain region 204 is in contact with the channel region 205 . The drain region 204 is connected to the N-well lead-out region 201, and both are connected to the electrostatic input terminal V _ESD . It should be noted here that, in the embodiment of the present invention, the drain region 204 is an N+ implantation region, and the channel region 205 is P--type doped.

A part of the N-well implantation region 210 is disposed in the P-type substrate under the N-well lead-out region 201 , and the N-well implantation region 210 extends to the bottom of the buried oxide region 202 , so that the N-well implantation region 210 and the lower part of the buried oxide region 202 are formed. Part of the surface is in contact, and the coupling area between the N-well implanted region 210 and the channel region 205 is greater than zero.

When the ESD event arrives, due to the introduction of the N-well implantation region on the P-type substrate, a reverse PN junction will be formed at the lower part of the gg-NMOS device. Due to the capacitive coupling brought by the reverse PN junction, the N-well implantation region is With a relatively higher potential, more electrons are coupled at the channel region 205 through the buried oxide region 202, thereby enhancing the avalanche breakdown effect. At the same time, the ESD transient current will form the parasitic capacitance of the reverse PN junction in the internal resistance of the N-well injection region 210, the P-type substrate 200 and the N-well injection region 210, and the parasitic capacitance of the reverse PN junction and the buried oxygen region 202 The voltage division between the formed parallel plate capacitors is realized, the npn BJT trigger voltage under the buried oxygen region 202 is reduced, the ESD current discharge capability of the bulk silicon level can be obtained, and the requirements of the ESD design window of the internal core circuit under the FDSOI process are met. It can play an effective ESD protection role when ESD arrives.

In the ESD protection device based on FDSOI gg-NMOS assisted triggering provided in the embodiment of the present invention, an N-well implantation region is set in the P-type substrate, and the N-well lead-out region is connected to the drain region, so that the ESD current leakage at the bulk silicon level can be obtained. It can meet the requirements of the ESD design window of the internal core circuit under the FDSOI process, and can play an effective ESD protection role when ESD arrives.

As shown in FIG. 2 , on the basis of the above embodiment, the ESD protection device based on FDSOI gg-NMOS assisted triggering provided in the embodiment of the present invention further includes: a source region 203 and a gate region 206 .

The gate region 206 is arranged on the channel region 205 ; the source region 203 is arranged on the buried oxide region 202 away from the N-well lead-out region 201 , and the channel region 205 is arranged between the source region 203 and the drain region 204 . The source region 203 is in contact with both the channel region 205 and the gate region 206 , and the drain region 204 is in contact with both the channel region 205 and the gate region 206 . The source region 203 is an N+ injection region, and both the source region 203 and the gate region 206 are grounded to G _ND . The parallel-plate capacitance formed by the buried oxide region 202 in the above embodiments is the parasitic capacitance formed between the P-type substrate 200 and the source region 203 .

On the basis of the above embodiment, in the ESD protection device based on FDSOI gg-NMOS assisted triggering provided in the embodiment of the present invention, the area of the part of the region where the lower surface of the buried oxide region is in contact with the N-well implanted region can be adjusted .

Specifically, as shown in FIG. 2 , the positions of the left boundary of the N-well implantation region are given, which are respectively position (1), position (2) and position (3) from right to left. It should be noted that the position of the left boundary of the N-well implantation region can be set to an appropriate position according to actual design requirements.

By adjusting the position of the left boundary of the N-well implanted region, the area of the part of the region where the lower surface of the buried oxide region 202 is in contact with the N-well implanted region 210 can be changed, thereby changing the coupling between the N-well implanted region 210 and the channel region 205 area, to adjust the triggering degree of the ESD protection device based on FDSOI gg-NMOS assisted triggering under ESD events, and to change the injection of electrons under the buried oxygen region 202 from the source region 203 of the ESD protection device based on FDSOI gg-NMOS assisted triggering Therefore, the trigger voltage of the npn BJT under the buried oxygen region 202 can be adjusted downward to meet the requirements of different ESD design windows, and at the same time, high ESD protection capability of bulk silicon can be obtained.

On the basis of the above embodiments, in the ESD protection device based on FDSOI gg-NMOS assisted triggering provided in the embodiments of the present invention, the length of the gate region is adjustable.

Specifically, studies in the embodiments of the present invention show that by adjusting the length Lg of the gate region 206, the trigger voltage of the npn BJT under the buried oxygen region 202 can also be adjusted downward to meet the requirements of different ESD design windows At the same time, it can also obtain high ESD protection capability of bulk silicon level.

It should be noted that, the ESD protection device based on FDSOI gg-NMOS assisted triggering provided in the embodiment of the present invention can not only adjust the left boundary position of the N-well injection region and the length of the gate region, but also adjust the two to adjust.

On the basis of the above embodiments, in the ESD protection device based on FDSOI gg-NMOS assisted triggering provided in the embodiments of the present invention, the gate region 206 is specifically: a high-k metal gate region.

As shown in FIG. 2 , on the basis of the above embodiments, the ESD protection device based on FDSOI gg-NMOS assisted triggering provided in the embodiments of the present invention further includes: a first metal region 209 and a second metal region 207 . The first metal region 209 is provided on the source region 203 , and the second metal region 207 is provided on the drain region 204 . The source region 203 is grounded to G _ND through the first metal region 209 , and the second metal region 207 is connected to the electrostatic input terminal V _ESD . The N-well lead-out region 201 is connected to the second metal region 207 , which is further connected to the drain region 204 .

As shown in FIG. 2 , on the basis of the above embodiment, the ESD protection device based on FDSOI gg-NMOS assisted triggering provided in the embodiment of the present invention further includes: a third metal region 212 and a fourth metal region 208 . The third metal region 212 is disposed on the substrate lead-out region 211 , and the fourth metal region 208 is disposed on the N-well lead-out region 201 . The third metal region 212 is grounded, the drain region 204 is connected to the fourth metal region 208 and further connected to the N-well lead-out region 201 .

On the basis of the above embodiments, in the ESD protection device based on FDSOI gg-NMOS assisted triggering provided in the embodiments of the present invention, the N-well implantation region is used for implanting N-type doping.

As shown in FIG. 3 , the positions of the left boundary of the N-well injection region in the ESD protection device based on FDSOI gg-NMOS assisted triggering provided in the embodiment of the present invention are positions (1), (2) and At position (3), the transmission line pulse (Transmission Line Pulse, TLP) test data result graph. Among them, the length Lg of the gate region of the ESD protection device based on FDSOI gg-NMOS auxiliary triggering is all 146 nm. In FIG. 3 , the abscissa is the transmission line pulse voltage (TLP voltage), namely V _ESD , the unit is V, and the ordinate is the transmission line pulse current (TLP current), the unit is mA/μm.

It can be seen from FIG. 3 that the trigger voltages of the ESD protection devices based on the FDSOI gg-NMOS assisted triggering provided in the embodiments of the present invention are all less than 3V. However, the trigger voltage of the existing FDSOI-based gg-NMOS device generally reaches 5.5V. Compared with the existing FDSOI-based gg-NMOS device, the ESDSOI-based gg-NMOS auxiliary triggering ESD provided in the embodiment of the present invention The protection device has a lower trigger voltage, and can adjust the trigger voltage by changing the position of the left boundary of the N-well injection region, so as to meet the requirements of the ESD design window and be applied to different ESD protection environments. As the position of the left boundary of the N-well implanted region moves to the left, the area of the part of the region where the lower surface of the buried oxide region is in contact with the N-well implanted region increases, thereby increasing the coupling area between the N-well implanted region and the channel region , the trigger voltage of the ESD protection device based on the FDSOI gg-NMOS auxiliary trigger becomes lower.

As shown in FIG. 4 , it is a test data result diagram of transmission line pulse (TLP) when the gate region lengths of the ESD protection device based on FDSOI gg-NMOS assisted triggering provided in the embodiment of the present invention are different. Among them, the position of the left boundary of the N-well implantation region in the FDSOI gg-NMOS-assisted triggering ESD protection device is the position (2) in FIG. 2 , and the lengths Lg of the gate region are 146 nm, 106 nm and 26 nm, respectively. In FIG. 4 , the abscissa is the transmission line pulse voltage (TLP voltage), namely V _ESD , the unit is V, and the ordinate is the transmission line pulse current (TLP current), the unit is mA/μm.

It can be seen from FIG. 4 that the trigger voltages of the ESD protection devices based on the FDSOI gg-NMOS assisted triggering provided in the embodiments of the present invention are all less than 3V. However, the trigger voltage of the existing FDSOI-based gg-NMOS device generally reaches 5.5V. Compared with the existing FDSOI-based gg-NMOS device, the ESDSOI-based gg-NMOS auxiliary triggering ESD provided in the embodiment of the present invention The protection device has a lower trigger voltage, and can adjust the trigger voltage by changing the length of the gate region, so as to meet the requirements of the ESD design window and be used in different ESD protection environments. As the length of the gate region becomes smaller, the triggering voltage of the ESD protection device based on FDSOI gg-NMOS assisted triggering becomes lower.

Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present invention, but not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand: it can still be Modifications are made to the technical solutions described in the foregoing embodiments, or some technical features thereof are equivalently replaced; and these modifications or replacements do not make the essence of the corresponding technical solutions depart from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims (7)

1. an ESD protection device based on FDSOIgg-NMOS auxiliary triggering, is characterized in that, comprises: P-type substrate, substrate lead-out region, buried oxygen region, drain region, channel region, N-well implantation region and N-well lead-out Area; The substrate lead-out region is arranged on one side of the surface of the P-type substrate, the N-well lead-out region is arranged on the other side of the surface of the P-type substrate, and the buried oxide region is arranged on the surface of the P-type substrate. the upper part of the P-type substrate, and the buried oxide region is located between the substrate lead-out region and the N-well lead-out region; The drain region is arranged on the buried oxide region near the N-well lead-out region, the channel region is arranged on the buried oxide region, and the drain region is in contact with the channel region, so the drain region is connected to the N well lead-out region; A part of the N-well implanted region is arranged in the P-type substrate under the N-well lead-out region, and the N-well implanted region extends to the bottom of the buried oxide region, and the N-well implanted region is connected to the N-well implanted region. The coupling area of the channel region is greater than zero; Also includes: source region and gate region; the gate region is disposed on the channel region; the source region is arranged on the buried oxide region away from the N-well lead-out region, and the channel region is arranged between the source region and the drain region; The source region is in contact with both the channel region and the gate region, and the drain region is in contact with both the channel region and the gate region. 2 . The ESD protection device based on FDSOIgg-NMOS assisted triggering according to claim 1 , wherein the area of the part of the region where the lower surface of the buried oxygen region is in contact with the N-well implanted region is adjustable. 3 . 3 . The ESD protection device based on FDSOIgg-NMOS assisted triggering according to claim 1 , wherein the length of the gate region is adjustable. 4 . 4 . The ESD protection device based on FDSOIgg-NMOS assisted triggering according to claim 1 , wherein the gate region is specifically: a high-k metal gate region. 5 . 5. The ESD protection device based on FDSOIgg-NMOS assisted triggering according to claim 1, further comprising: a first metal region and a second metal region; the first metal region is arranged on the source region, and the second metal region is arranged on the drain region; The first metal area is grounded, and the second metal area is connected to the electrostatic input terminal. 6. The ESD protection device based on FDSOI gg-NMOS assisted triggering according to any one of claims 1-5, characterized in that, further comprising: a third metal region and a fourth metal region; The third metal region is arranged on the substrate lead-out region, and the fourth metal region is arranged on the N-well lead-out region; The third metal region is grounded, and the drain region is connected to the N-well lead-out region through the fourth metal region. 7 . The ESD protection device based on FDSOI gg-NMOS assisted triggering according to claim 1 , wherein the N-well implantation region is used for implanting N-type doping. 8 .

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