CN109817153A - Gate driving unit, gate driving method, gate driving circuit and display device - Google Patents
Gate driving unit, gate driving method, gate driving circuit and display device Download PDFInfo
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Abstract
Description
技术领域technical field
本发明涉及显示驱动技术领域，尤其涉及一种栅极驱动单元、栅极驱动方法、栅极驱动电路和显示装置。The present invention relates to the technical field of display driving, and in particular, to a gate driving unit, a gate driving method, a gate driving circuit and a display device.
背景技术Background technique
现有的栅极驱动单元在工作时，当输入端的脉冲信号到来时，为上拉节点充电，随后输入信号的电位被置低时，保持上拉节点的电位，当该行时钟信号到来时，由于自举作用，上拉节点的电位被进一步拉高。然而在真实的这个过程中，由于与上拉节点电连接的晶体管众多，且在现有的GOA(Gate On Array，设置于阵列基板上的栅极驱动电路)架构设计情况下，与上拉节点连接的晶体管的栅源电压Vgs一般都在0V以上(以该晶体管为n型晶体管为例)，所以该晶体管的漏电流造成的上拉节点的电位下降不可忽略。上拉节点的电位的高低直接决定了输出晶体管的开启是否充分，上拉节点的电位下降便直接导致该输出晶体管的输出能力下降，不能保证栅极驱动单元的驱动能力。When the existing gate drive unit is working, when the pulse signal at the input terminal arrives, it charges the pull-up node, and then when the potential of the input signal is set low, the potential of the pull-up node is maintained. Due to the bootstrapping, the potential of the pull-up node is further pulled up. However, in the real process, since there are many transistors electrically connected to the pull-up node, and in the existing GOA (Gate On Array, gate drive circuit disposed on the array substrate) architecture design, it is not related to the pull-up node. The gate-source voltage Vgs of the connected transistor is generally above 0V (taking the transistor as an n-type transistor as an example), so the potential drop of the pull-up node caused by the leakage current of the transistor cannot be ignored. The level of the potential of the pull-up node directly determines whether the output transistor is fully turned on. The drop in the potential of the pull-up node directly reduces the output capability of the output transistor, which cannot guarantee the drive capability of the gate drive unit.
发明内容SUMMARY OF THE INVENTION
本发明的主要目的在于提供一种栅极驱动单元、栅极驱动方法、栅极驱动电路和显示装置，解决现有技术中无法在输出阶段维持上拉节点的电位，从而不能保证栅极驱动单元的驱动能力的问题。The main purpose of the present invention is to provide a gate driving unit, a gate driving method, a gate driving circuit and a display device, so as to solve the problem that the potential of the pull-up node cannot be maintained in the output stage in the prior art, so that the gate driving unit cannot be guaranteed. problem of driving ability.
为了达到上述目的，本发明提供了一种栅极驱动单元，包括上拉节点复位电路、上拉节点下拉电路和控制电路；In order to achieve the above object, the present invention provides a gate driving unit, including a pull-up node reset circuit, a pull-up node pull-down circuit and a control circuit;
所述控制电路用于在输出阶段，控制所述上拉节点复位电路中的与上拉节点连接的晶体管的栅源电压在第一预定电压范围内，并控制所述上拉节点下拉电路中的与上拉节点连接的晶体管的栅源电压在第二预定电压范围内。The control circuit is used to control the gate-source voltage of the transistor connected to the pull-up node in the pull-up node reset circuit to be within a first predetermined voltage range, and to control the pull-up node pull-down circuit in the output stage. The gate-source voltage of the transistor connected to the pull-up node is within a second predetermined voltage range.
实施时，所述上拉节点复位电路中的与上拉节点连接的晶体管为n型晶体管，所述第一预定电压范围为小于或等于0；或者，During implementation, the transistor connected to the pull-up node in the pull-up node reset circuit is an n-type transistor, and the first predetermined voltage range is less than or equal to 0; or,
所述上拉节点复位电路中的与上拉节点连接的晶体管为p型晶体管，所述第一预定电压范围为大于或等于0。The transistor connected to the pull-up node in the pull-up node reset circuit is a p-type transistor, and the first predetermined voltage range is greater than or equal to zero.
实施时，所述上拉节点下拉电路中的与上拉节点连接的晶体管为n型晶体管，所述第二预定电压范围为小于或等于0；或者，During implementation, the transistor connected to the pull-up node in the pull-up node pull-down circuit is an n-type transistor, and the second predetermined voltage range is less than or equal to 0; or,
所述上拉节点下拉电路中的与上拉节点连接的晶体管为p型晶体管，所述第二预定电压范围为大于或等于0。The transistor connected to the pull-up node in the pull-up node pull-down circuit is a p-type transistor, and the second predetermined voltage range is greater than or equal to zero.
实施时，所述上拉节点复位电路包括上拉节点复位晶体管；During implementation, the pull-up node reset circuit includes a pull-up node reset transistor;
所述上拉节点复位晶体管的控制极与复位端连接，所述上拉节点复位晶体管的第一极与所述上拉节点连接，所述上拉节点复位晶体管的第二极与第一电压端连接；The control pole of the pull-up node reset transistor is connected to the reset terminal, the first pole of the pull-up node reset transistor is connected to the pull-up node, and the second pole of the pull-up node reset transistor is connected to the first voltage terminal connect;
所述控制电路包括电压提供电路；the control circuit includes a voltage supply circuit;
所述电压提供电路用于向所述第一电压端提供第一电压，以使得在输出阶段，该上拉节点复位晶体管的栅源电压在第一预定电压范围内。The voltage supply circuit is used for supplying a first voltage to the first voltage terminal, so that in an output stage, the gate-source voltage of the pull-up node reset transistor is within a first predetermined voltage range.
实施时，所述上拉节点下拉电路包括上拉节点下拉晶体管；During implementation, the pull-up node pull-down circuit includes a pull-up node pull-down transistor;
所述上拉节点下拉晶体管的控制极与下拉节点连接，所述上拉节点下拉晶体管的第一极与所述上拉节点连接，所述上拉节点下拉晶体管的第二极与第二电压端连接；The control electrode of the pull-up node pull-down transistor is connected to the pull-down node, the first electrode of the pull-up node pull-down transistor is connected to the pull-up node, and the second electrode of the pull-up node pull-down transistor is connected to the second voltage end connect;
所述控制电路包括电压提供电路；所述电压提供电路用于向所述第二电压端提供第二电压，以使得在输出阶段，该上拉节点下拉晶体管的栅源电压在第二预定电压范围内；和/或，The control circuit includes a voltage supply circuit; the voltage supply circuit is used for supplying a second voltage to the second voltage terminal, so that in the output stage, the gate-source voltage of the pull-up node pull-down transistor is within a second predetermined voltage range within; and/or,
所述控制电路包括电压控制电路；所述电压控制电路用于在输出阶段，通过控制所述下拉节点的电压，以使得该上拉节点下拉晶体管的栅源电压在第二预定电压范围内。The control circuit includes a voltage control circuit; the voltage control circuit is used for controlling the voltage of the pull-down node in the output stage, so that the gate-source voltage of the pull-down transistor of the pull-up node is within a second predetermined voltage range.
实施时，所述栅极驱动单元还包括下拉节点控制电路，所述下拉节点控制电路用于在输入端输入的输入信号的控制下，控制所述下拉节点与第三电压端之间连通；During implementation, the gate driving unit further includes a pull-down node control circuit, and the pull-down node control circuit is configured to control the connection between the pull-down node and the third voltage terminal under the control of the input signal input from the input terminal;
所述控制电路包括电压控制电路；所述电压控制电路用于向第三电压端提供第三电压，以使得在所述输出阶段，所述下拉节点的电压为所述第三电压。The control circuit includes a voltage control circuit; the voltage control circuit is configured to provide a third voltage to the third voltage terminal, so that in the output stage, the voltage of the pull-down node is the third voltage.
本发明还提供了一种栅极驱动方法，应用于上述的栅极驱动单元，所述栅极驱动方法包括：The present invention also provides a gate driving method, which is applied to the above-mentioned gate driving unit, and the gate driving method includes:
在输出阶段，控制电路控制上拉节点复位电路中的与上拉节点连接的晶体管的栅源电压在第一预定电压范围内，并控制上拉节点下拉电路中的与上拉节点连接的晶体管的栅源电压在第二预定电压范围内。In the output stage, the control circuit controls the gate-source voltage of the transistor connected to the pull-up node in the pull-up node reset circuit to be within the first predetermined voltage range, and controls the transistors connected to the pull-up node in the pull-up node pull-down circuit. The gate-source voltage is within a second predetermined voltage range.
实施时，所述上拉节点复位电路中的与上拉节点连接的晶体管为n型晶体管，所述第一预定电压范围为小于或等于0；或者，During implementation, the transistor connected to the pull-up node in the pull-up node reset circuit is an n-type transistor, and the first predetermined voltage range is less than or equal to 0; or,
所述上拉节点复位电路中的与上拉节点连接的晶体管为p型晶体管，所述第一预定电压范围为大于或等于0。The transistor connected to the pull-up node in the pull-up node reset circuit is a p-type transistor, and the first predetermined voltage range is greater than or equal to zero.
实施时，所述上拉节点下拉电路中的与上拉节点连接的晶体管为n型晶体管，所述第二预定电压范围为小于或等于0；或者，During implementation, the transistor connected to the pull-up node in the pull-up node pull-down circuit is an n-type transistor, and the second predetermined voltage range is less than or equal to 0; or,
所述上拉节点下拉电路中的与上拉节点连接的晶体管为p型晶体管，所述第二预定电压范围为大于或等于0。The transistor connected to the pull-up node in the pull-up node pull-down circuit is a p-type transistor, and the second predetermined voltage range is greater than or equal to zero.
本发明还提供了一种栅极驱动电路，包括多级上述的栅极驱动单元。The present invention also provides a gate driving circuit, which includes the above-mentioned gate driving units in multiple stages.
本发明还提供了一种显示装置，包括上述的栅极驱动电路。The present invention also provides a display device including the above gate driving circuit.
与现有技术相比，本发明所述的栅极驱动单元、栅极驱动方法、栅极驱动电路和显示装置在输出阶段，控制减小所述上拉节点复位电路中的与上拉节点连接的晶体管的漏电流，并控制减小所述上拉节点下拉电路中的与上拉节点连接的晶体管的漏电流，从而能够在输出阶段很好的保持上拉节点的电位，保证所述栅极驱动单元的驱动能力。Compared with the prior art, the gate driving unit, the gate driving method, the gate driving circuit and the display device of the present invention control to reduce the connection with the pull-up node in the pull-up node reset circuit in the output stage. The leakage current of the transistor is controlled to reduce the leakage current of the transistor connected to the pull-up node in the pull-up node pull-down circuit, so that the potential of the pull-up node can be well maintained in the output stage to ensure that the gate Drive capability of the drive unit.
附图说明Description of drawings
图1是本发明实施例所述的栅极驱动单元的结构图；FIG. 1 is a structural diagram of a gate driving unit according to an embodiment of the present invention;
图2A是现有的栅极驱动单元中的上拉节点PU的电位的波形图；2A is a waveform diagram of the potential of the pull-up node PU in the conventional gate driving unit;
图2B是现有的栅极驱动单元输出的栅极驱动信号的波形图；2B is a waveform diagram of a gate driving signal output by a conventional gate driving unit;
图3是本发明另一实施例所述的栅极驱动单元的电路图；3 is a circuit diagram of a gate driving unit according to another embodiment of the present invention;
图4是本发明又一实施例所述的栅极驱动单元的电路图；4 is a circuit diagram of a gate driving unit according to another embodiment of the present invention;
图5是本发明所述的栅极驱动单元的第一具体实施例的电路图；FIG. 5 is a circuit diagram of a first specific embodiment of the gate driving unit according to the present invention;
图6A是本发明所述的栅极驱动单元的第一具体实施例中的上拉节点PU的电位的波形图；6A is a waveform diagram of the potential of the pull-up node PU in the first embodiment of the gate driving unit according to the present invention;
图6B是本发明所述的栅极驱动单元的第一具体实施例输出的栅极驱动信号的波形图；6B is a waveform diagram of a gate driving signal output by the first specific embodiment of the gate driving unit of the present invention;
图7是本发明所述的栅极驱动单元的第二具体实施例的电路图。FIG. 7 is a circuit diagram of a second specific embodiment of the gate driving unit according to the present invention.
具体实施方式Detailed ways
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, but not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.
本发明所有实施例中采用的晶体管均可以为三极管、薄膜晶体管或场效应管或其他特性相同的器件。在本发明实施例中，为区分晶体管除控制极之外的两极，将其中一极称为第一极，另一极称为第二极。The transistors used in all embodiments of the present invention may be triodes, thin film transistors, field effect transistors, or other devices with the same characteristics. In the embodiment of the present invention, in order to distinguish the two poles of the transistor except the control pole, one pole is called the first pole, and the other pole is called the second pole.
在实际操作时，当所述晶体管为三极管时，所述控制极可以为基极，所述第一极可以为集电极，所述第二极可以发射极；或者，所述控制极可以为基极，所述第一极可以为发射极，所述第二极可以集电极。In actual operation, when the transistor is a triode, the control electrode may be the base electrode, the first electrode may be the collector electrode, and the second electrode may be the emitter electrode; or the control electrode may be the base electrode electrode, the first electrode can be an emitter electrode, and the second electrode can be a collector electrode.
在实际操作时，当所述晶体管为薄膜晶体管或场效应管时，所述控制极可以为栅极，所述第一极可以为漏极，所述第二极可以为源极；或者，所述控制极可以为栅极，所述第一极可以为源极，所述第二极可以为漏极。In actual operation, when the transistor is a thin film transistor or a field effect transistor, the control electrode may be a gate electrode, the first electrode may be a drain electrode, and the second electrode may be a source electrode; The control electrode may be a gate electrode, the first electrode may be a source electrode, and the second electrode may be a drain electrode.
如图1所示，本发明实施例所述的栅极驱动单元包括上拉节点复位电路11、上拉节点下拉电路12和控制电路13；As shown in FIG. 1 , the gate driving unit according to the embodiment of the present invention includes a pull-up node reset circuit 11 , a pull-up node pull-down circuit 12 and a control circuit 13 ;
所述控制电路13用于在输出阶段，控制所述上拉节点复位电路11中的与上拉节点连接的晶体管的栅源电压在第一预定电压范围内，并控制所述上拉节点下拉电路12中的与上拉节点连接的晶体管的栅源电压在第二预定电压范围内，以在输出阶段，控制所述上拉节点复位电路11中的与上拉节点连接的晶体管完全关断，并控制减小所述上拉节点复位电路11中的与上拉节点连接的晶体管的漏电流，并在所述输出阶段，控制所述上拉节点下拉电路12中的与上拉节点连接的晶体管完全关断，并控制减小所述上拉节点下拉电路12中的与上拉节点连接的晶体管的漏电流。The control circuit 13 is used to control the gate-source voltage of the transistor connected to the pull-up node in the pull-up node reset circuit 11 to be within a first predetermined voltage range, and to control the pull-up node pull-down circuit in the output stage The gate-source voltage of the transistor connected to the pull-up node in 12 is within a second predetermined voltage range, so as to control the transistor connected to the pull-up node in the pull-up node reset circuit 11 to be completely turned off in the output stage, and The control reduces the leakage current of the transistor connected to the pull-up node in the pull-up node reset circuit 11, and in the output stage, controls the transistor connected to the pull-up node in the pull-up node pull-down circuit 12 to completely It is turned off and controlled to reduce the leakage current of the transistor connected to the pull-up node in the pull-up node pull-down circuit 12 .
本发明实施例所述的栅极驱动单元在输出阶段，控制减小所述上拉节点复位电路11中的与上拉节点连接的晶体管的漏电流，并控制减小所述上拉节点下拉电路12中的与上拉节点连接的晶体管的漏电流，从而能够在输出阶段很好的保持上拉节点的电位，保证所述栅极驱动单元的驱动能力。In the output stage of the gate driving unit according to the embodiment of the present invention, the leakage current of the transistor connected to the pull-up node in the pull-up node reset circuit 11 is controlled to reduce, and the pull-up node pull-down circuit is controlled to reduce The leakage current of the transistor connected to the pull-up node in 12 can well maintain the potential of the pull-up node in the output stage and ensure the driving capability of the gate driving unit.
在现有技术中，如图2A所示，由于在输出阶段S2，所述上拉节点下拉电路12中的与上拉节点连接的晶体管和/或所述上拉节点复位电路11中的与上拉节点连接的晶体管存在的漏电流较大，则上拉节点PU的电位保持能力差，PU的电处于漏电掉压的状态，直接的结果是所述栅极驱动单元输出的栅极驱动信号的上升时间Tr和该栅极驱动信号的下降时间Tf增大，降低栅极驱动能力。In the prior art, as shown in FIG. 2A , since in the output stage S2, the transistor connected to the pull-up node in the pull-up node pull-down circuit 12 and/or the pull-up node reset circuit 11 is connected to the pull-up node. The leakage current of the transistor connected to the pull-up node is relatively large, and the potential retention capability of the pull-up node PU is poor, and the power of the PU is in a state of leakage and voltage drop. The direct result is that the gate driving signal output by the gate driving unit The rise time Tr and the fall time Tf of the gate drive signal increase, reducing the gate drive capability.
图2B是在现有技术中，栅极驱动信号输出端OUT1输出的栅极驱动信号的波形图。FIG. 2B is a waveform diagram of the gate driving signal output by the gate driving signal output terminal OUT1 in the prior art.
根据一种具体实施方式，所述上拉节点复位电路中的与上拉节点连接的晶体管可以为n型晶体管，所述第一预定电压范围为小于或等于0；或者，According to a specific implementation manner, the transistor connected to the pull-up node in the pull-up node reset circuit may be an n-type transistor, and the first predetermined voltage range is less than or equal to 0; or,
所述上拉节点复位电路中的与上拉节点连接的晶体管可以为p型晶体管，所述第一预定电压范围为大于或等于0。The transistor connected to the pull-up node in the pull-up node reset circuit may be a p-type transistor, and the first predetermined voltage range is greater than or equal to zero.
根据另一种具体实施方式，所述上拉节点下拉电路中的与上拉节点连接的晶体管可以为n型晶体管，所述第二预定电压范围为小于或等于0；或者，According to another specific implementation manner, the transistor connected to the pull-up node in the pull-up node pull-down circuit may be an n-type transistor, and the second predetermined voltage range is less than or equal to 0; or,
所述上拉节点下拉电路中的与上拉节点连接的晶体管可以为p型晶体管，所述第二预定电压范围为大于或等于0。The transistor connected to the pull-up node in the pull-up node pull-down circuit may be a p-type transistor, and the second predetermined voltage range is greater than or equal to zero.
具体的，所述上拉节点复位电路可以包括上拉节点复位晶体管；Specifically, the pull-up node reset circuit may include a pull-up node reset transistor;
所述上拉节点复位晶体管的控制极与复位端连接，所述上拉节点复位晶体管的第一极与所述上拉节点连接，所述上拉节点复位晶体管的第二极与第一电压端连接；The control pole of the pull-up node reset transistor is connected to the reset terminal, the first pole of the pull-up node reset transistor is connected to the pull-up node, and the second pole of the pull-up node reset transistor is connected to the first voltage terminal connect;
所述控制电路包括电压提供电路；the control circuit includes a voltage supply circuit;
所述电压提供电路用于向所述第一电压端提供第一电压，以使得在输出阶段，该上拉节点复位晶体管的栅源电压在第一预定电压范围内。The voltage supply circuit is used for supplying a first voltage to the first voltage terminal, so that in an output stage, the gate-source voltage of the pull-up node reset transistor is within a first predetermined voltage range.
在具体实施时，所述上拉节点复位电路可以包括上拉节点复位晶体管，所述控制电路可以包括电压提供电路，所述电压提供电路用于向所述上拉节点复位端的第二极提供第一电压，以使得在输出阶段，该上拉节点复位晶体管的栅源电压在第一预定电压范围内。In a specific implementation, the pull-up node reset circuit may include a pull-up node reset transistor, and the control circuit may include a voltage supply circuit, and the voltage supply circuit is configured to provide a first voltage supply circuit to the second pole of the pull-up node reset terminal. A voltage such that in the output stage, the gate-source voltage of the pull-up node reset transistor is within a first predetermined voltage range.
具体的，所述上拉节点下拉电路可以包括上拉节点下拉晶体管；Specifically, the pull-up node pull-down circuit may include a pull-up node pull-down transistor;
所述上拉节点下拉晶体管的控制极与下拉节点连接，所述上拉节点下拉晶体管的第一极与所述上拉节点连接，所述上拉节点下拉晶体管的第二极与第二电压端连接；The control electrode of the pull-up node pull-down transistor is connected to the pull-down node, the first electrode of the pull-up node pull-down transistor is connected to the pull-up node, and the second electrode of the pull-up node pull-down transistor is connected to the second voltage end connect;
所述控制电路包括电压提供电路；所述电压提供电路用于向所述第二电压端提供第二电压，以使得在输出阶段，该上拉节点下拉晶体管的栅源电压在第二预定电压范围内；和/或，The control circuit includes a voltage supply circuit; the voltage supply circuit is used for supplying a second voltage to the second voltage terminal, so that in the output stage, the gate-source voltage of the pull-up node pull-down transistor is within a second predetermined voltage range within; and/or,
所述控制电路包括电压控制电路；所述电压控制电路用于在输出阶段，通过控制所述下拉节点的电压，以使得该上拉节点下拉晶体管的栅源电压在第二预定电压范围内。The control circuit includes a voltage control circuit; the voltage control circuit is used for controlling the voltage of the pull-down node in the output stage, so that the gate-source voltage of the pull-down transistor of the pull-up node is within a second predetermined voltage range.
在具体实施时，所述上拉节点下拉电路可以包括上拉节点下拉晶体管，所述控制电路可以包括电压提供电路，所述电压提供电路用于向所述上拉节点下拉晶体管的第二极提供第二电压，以使得在输出阶段，该上拉节点下拉晶体管的栅源电压在第二预定电压范围内；In a specific implementation, the pull-up node pull-down circuit may include a pull-up node pull-down transistor, and the control circuit may include a voltage supply circuit configured to provide a second pole of the pull-up node pull-down transistor a second voltage, such that in the output stage, the gate-source voltage of the pull-up node pull-down transistor is within a second predetermined voltage range;
在具体实施时，所述上拉节点下拉电路可以包括上拉节点下拉晶体管，所述控制电路可以包括电压控制电路，所述电压控制电路用于在输出阶段，控制下拉节点的电压，以使得在输出阶段，该上拉节点下拉晶体管的栅源电压在第二预定电压范围内。In a specific implementation, the pull-up node pull-down circuit may include a pull-up node pull-down transistor, the control circuit may include a voltage control circuit, and the voltage control circuit is configured to control the voltage of the pull-down node in the output stage, so that at the output stage In the output stage, the gate-source voltage of the pull-up node pull-down transistor is within a second predetermined voltage range.
具体的，本发明实施例所述的栅极驱动单元还可以包括下拉节点控制电路，所述下拉节点控制电路用于在输入端输入的输入信号的控制下，控制所述下拉节点与第三电压端之间连通；Specifically, the gate driving unit according to the embodiment of the present invention may further include a pull-down node control circuit, and the pull-down node control circuit is configured to control the pull-down node and the third voltage under the control of the input signal input from the input terminal. connection between terminals;
当所述控制电路包括电压控制电路时，所述电压控制电路用于向第三电压端提供第三电压，以使得在所述输出阶段，所述下拉节点的电压为所述第三电压。When the control circuit includes a voltage control circuit, the voltage control circuit is configured to provide a third voltage to the third voltage terminal, so that in the output stage, the voltage of the pull-down node is the third voltage.
如图3所示，在图1所示的栅极驱动单元的实施例的基础上，所述上拉节点复位电路11包括第一上拉节点复位晶体管M2和第二上拉节点复位晶体管M15；所述上拉节点下拉电路12包括第一上拉节点下拉晶体管M8A和第二上拉节点下拉晶体管M8B；所述控制电路包括电压提供电路131；As shown in FIG. 3, based on the embodiment of the gate driving unit shown in FIG. 1, the pull-up node reset circuit 11 includes a first pull-up node reset transistor M2 and a second pull-up node reset transistor M15; The pull-up node pull-down circuit 12 includes a first pull-up node pull-down transistor M8A and a second pull-up node pull-down transistor M8B; the control circuit includes a voltage supply circuit 131;
M2的栅极与第一复位端RST连接，M2的漏极与上拉节点PU连接，M2的源极与第一低电压端连接；所述第一低电压端用于输入第一低电压VGL；The gate of M2 is connected to the first reset terminal RST, the drain of M2 is connected to the pull-up node PU, and the source of M2 is connected to the first low voltage terminal; the first low voltage terminal is used to input the first low voltage VGL ;
M15的栅极与第二复位端TGOA_RST连接，M15的漏极与上拉节点PU连接，M15的源极与第一低电压端连接；所述第一低电压端用于输入第一低电压VGL；The gate of M15 is connected to the second reset terminal TGOA_RST, the drain of M15 is connected to the pull-up node PU, and the source of M15 is connected to the first low voltage terminal; the first low voltage terminal is used to input the first low voltage VGL ;
M8A的栅极与第一下拉节点PD_A连接，M8A的漏极与所述上拉节点PU连接，M8A的源极与所述第一低电压端连接；The gate of M8A is connected to the first pull-down node PD_A, the drain of M8A is connected to the pull-up node PU, and the source of M8A is connected to the first low-voltage terminal;
M8B的栅极与第二下拉节点PD_B连接，M8B的漏极与所述上拉节点PU连接，M8B的源极与所述第一低电压端连接；The gate of M8B is connected to the second pull-down node PD_B, the drain of M8B is connected to the pull-up node PU, and the source of M8B is connected to the first low-voltage terminal;
所述电压提供电路131与所述第一低电压端连接，用于提供所述第一低电压VGL，以使得在输出阶段M2的栅源电压、M15的栅源电压，M8A的栅源电压和M8B的栅源电压都小于或等于0，以使得在输出阶段，M2、M15、M8A和M8B都完全关断，减小M2的漏电流、M15的漏电流、M8A的漏电流和M8B的漏电流。The voltage supply circuit 131 is connected to the first low voltage terminal for supplying the first low voltage VGL, so that the gate-source voltage of M2, the gate-source voltage of M15, the gate-source voltage of M8A and the The gate-source voltage of M8B is less than or equal to 0, so that in the output stage, M2, M15, M8A and M8B are completely turned off, reducing the leakage current of M2, the leakage current of M15, the leakage current of M8A and the leakage current of M8B .
在图3所示的实施例中，第一电压端和第二电压端都为所述第一低电压端，但不以此为限；In the embodiment shown in FIG. 3 , both the first voltage terminal and the second voltage terminal are the first low voltage terminal, but not limited thereto;
在图3所示的实施例中，M2、M15、M8A和M8B都为NMOS管(N型金属-氧化物-半导体晶体管)，但不以此为限。In the embodiment shown in FIG. 3 , M2 , M15 , M8A and M8B are all NMOS transistors (N-type metal-oxide-semiconductor transistors), but not limited thereto.
如图4所示，在图1所示的栅极驱动单元的实施例的基础上，本发明实施例所述的栅极驱动单元还包括下拉节点控制电路14；下拉节点包括第一下拉节点PD_A和第二下拉节点PD_B；As shown in FIG. 4 , on the basis of the embodiment of the gate driving unit shown in FIG. 1 , the gate driving unit according to the embodiment of the present invention further includes a pull-down node control circuit 14 ; the pull-down node includes a first pull-down node PD_A and the second pull-down node PD_B;
所述下拉节点控制电路14用于在输入端INPUT输入的输入信号的控制下，控制所述第一下拉节点PD_A与第三低电压端之间连通，控制所述第二下拉节点PD_B与第三低电压端之间连通；The pull-down node control circuit 14 is used to control the connection between the first pull-down node PD_A and the third low-voltage end, and control the second pull-down node PD_B to communicate with the third pull-down node PD_B under the control of the input signal input from the input terminal INPUT. Connected between the three low-voltage terminals;
所述上拉节点复位电路11包括第一上拉节点复位晶体管M2和第二上拉节点复位晶体管M15；所述上拉节点下拉电路12包括第一上拉节点下拉晶体管M8A和第二上拉节点下拉晶体管M8B；The pull-up node reset circuit 11 includes a first pull-up node reset transistor M2 and a second pull-up node reset transistor M15; the pull-up node pull-down circuit 12 includes a first pull-up node pull-down transistor M8A and a second pull-up node pull-down transistor M8B;
M2的栅极与第一复位端RST连接，M2的漏极与上拉节点PU连接，M2的源极与第一低电压端连接；所述第一低电压端用于输入第一低电压VGL；The gate of M2 is connected to the first reset terminal RST, the drain of M2 is connected to the pull-up node PU, and the source of M2 is connected to the first low voltage terminal; the first low voltage terminal is used to input the first low voltage VGL ;
M15的栅极与第二复位端TGOA_RST连接，M15的漏极与上拉节点PU连接，M15的源极与第一低电压端连接；所述第一低电压端用于输入第一低电压VGL；The gate of M15 is connected to the second reset terminal TGOA_RST, the drain of M15 is connected to the pull-up node PU, and the source of M15 is connected to the first low voltage terminal; the first low voltage terminal is used to input the first low voltage VGL ;
M8A的栅极与第一下拉节点PD_A连接，M8A的漏极与所述上拉节点PU连接，M8A的源极与第二低电压端连接；The gate of M8A is connected to the first pull-down node PD_A, the drain of M8A is connected to the pull-up node PU, and the source of M8A is connected to the second low voltage terminal;
M8B的栅极与第二下拉节点PD_B连接，M8B的漏极与所述上拉节点PU连接，M8B的源极与所述第二低电压端连接；所述第二低电压端用于输入第二低电压LVGL；The gate of M8B is connected to the second pull-down node PD_B, the drain of M8B is connected to the pull-up node PU, and the source of M8B is connected to the second low voltage terminal; the second low voltage terminal is used to input the first Two low voltage LVGL;
所述控制电路包括电压提供电路131和电压控制电路132；The control circuit includes a voltage supply circuit 131 and a voltage control circuit 132;
所述电压提供电路131与所述第一低电压端连接，用于提供所述第一低电压VGL，以使得在输出阶段M2的栅源电压和M15的栅源电压都小于或等于0，以使得在输出阶段，M2和M15都完全关断，减小M2的漏电流和M15的漏电流；The voltage supply circuit 131 is connected to the first low voltage terminal for supplying the first low voltage VGL, so that the gate-source voltage of M2 and the gate-source voltage of M15 are both less than or equal to 0 in the output stage, so as to In the output stage, both M2 and M15 are completely turned off, reducing the leakage current of M2 and the leakage current of M15;
所述电压控制电路132用于向第三低电压端提供第三低电压LLVGL，以使得在所述输出阶段，所述第一下拉节点PD_A的电压为所述第三低电压LLVGL，所述第二下拉节点PD_B的电压为所述第三低电压LLVGL；The voltage control circuit 132 is configured to provide the third low voltage LLVGL to the third low voltage terminal, so that in the output stage, the voltage of the first pull-down node PD_A is the third low voltage LLVGL, the The voltage of the second pull-down node PD_B is the third low voltage LLVGL;
所述第三低电压LLVGL小于所述第二低电压LVGL，以使得在输出阶段，M8A的栅源电压小于或等于0，M8B的栅源电压小于或等于0，以使得在输出阶段，M8A和M8B都完全关断，减小M8A的漏电流和M8B的漏电流。The third low voltage LLVGL is smaller than the second low voltage LVGL, so that in the output stage, the gate-source voltage of M8A is less than or equal to 0, and the gate-source voltage of M8B is less than or equal to 0, so that in the output stage, M8A and M8B are completely turned off, reducing the leakage current of M8A and the leakage current of M8B.
在图4所示的实施例中，第一电压端为第一低电压端，第二电压端为第二低电压端，第三电压端为第三低电压端，但不以此为限。In the embodiment shown in FIG. 4 , the first voltage terminal is the first low voltage terminal, the second voltage terminal is the second low voltage terminal, and the third voltage terminal is the third low voltage terminal, but not limited thereto.
在图4所示的实施例中，M2、M15、M8A和M8B都为NMOS管，但不以此为限。In the embodiment shown in FIG. 4 , M2, M15, M8A and M8B are all NMOS transistors, but not limited thereto.
具体的，所述下拉节点控制电路可以包括第一下拉节点控制晶体管和第二下拉节点控制晶体管；Specifically, the pull-down node control circuit may include a first pull-down node control transistor and a second pull-down node control transistor;
所述第一下拉节点控制晶体管的控制极与所述输入端连接，所述第一下拉节点控制晶体管的第一极与所述第一下拉节点连接，所述第一下拉节点控制晶体管的第二极与第三电压端连接；The control electrode of the first pull-down node control transistor is connected to the input terminal, the first electrode of the first pull-down node control transistor is connected to the first pull-down node, and the first pull-down node controls the second pole of the transistor is connected to the third voltage terminal;
所述第二下拉节点控制晶体管的控制极与所述输入端连接，所述第二下拉节点控制晶体管的第一极与所述第二下拉节点连接，所述第二下拉节点控制晶体管的第二极与第三电压端连接。The control electrode of the second pull-down node control transistor is connected to the input terminal, the first electrode of the second pull-down node control transistor is connected to the second pull-down node, and the second pull-down node controls the second pull-down node of the transistor. The pole is connected to the third voltage terminal.
具体的，本发明实施例所述的栅极驱动单元还可以包括输入电路，第一下拉控制电路，第二下拉控制电路、栅极驱动信号输出电路和进位信号输出电路，其中，Specifically, the gate driving unit according to the embodiment of the present invention may further include an input circuit, a first pull-down control circuit, a second pull-down control circuit, a gate drive signal output circuit and a carry signal output circuit, wherein,
所述输入电路用于在输入端的控制下，控制上拉节点与输入端之间连通；The input circuit is used to control the connection between the pull-up node and the input end under the control of the input end;
所述第一下拉控制电路用于在第一控制电压端输入的第一控制电压的控制下，控制所述第一控制电压端与第一下拉节点之间连通，并用于在上拉节点的电压的控制下，控制第一下拉节点的电位；The first pull-down control circuit is used to control the connection between the first control voltage terminal and the first pull-down node under the control of the first control voltage input from the first control voltage terminal, and is used for the pull-up node Under the control of the voltage of , the potential of the first pull-down node is controlled;
所述第二下拉控制电路用于在第二控制电压端输入的第二控制电压的控制下，控制所述第二控制电压端与第二下拉节点之间连通，并用于在上拉节点的电压的控制下，控制第二下拉节点的电位；The second pull-down control circuit is used to control the connection between the second control voltage terminal and the second pull-down node under the control of the second control voltage input from the second control voltage terminal, and is used for pulling up the voltage of the node Under the control of , control the potential of the second pull-down node;
所述栅极驱动信号输出电路用于在上拉节点的电位的控制下，控制栅极驱动信号输出端与时钟信号端连接，在第一下拉节点的电位的控制下，控制栅极驱动信号输出端与第二低电压端之间连通，在第二下拉节点的电位的控制下，控制栅极驱动信号输出端与第二低电压端之间连通，在第三复位端输入的第三复位信号的控制下，控制所述栅极驱动信号输出端与所述第一低电压端之间连通；The gate drive signal output circuit is used to control the gate drive signal output terminal to be connected to the clock signal terminal under the control of the potential of the pull-up node, and to control the gate drive signal under the control of the potential of the first pull-down node The output terminal is connected with the second low voltage terminal, and under the control of the potential of the second pull-down node, the control gate driving signal output terminal is connected with the second low voltage terminal, and the third reset terminal inputted at the third reset terminal Under the control of the signal, the gate driving signal output terminal is controlled to communicate with the first low voltage terminal;
所述进位信号输出电路用于在上拉节点的电位的控制下，控制进位信号输出端与时钟信号端连接，在第一下拉节点的电位的控制下，控制进位信号输出端与第一低电压端之间连通，在第二下拉节点的电位的控制下，控制进位信号输出端与第一低电压端之间连通。The carry signal output circuit is used to control the carry signal output end to be connected to the clock signal end under the control of the potential of the pull-up node, and to control the carry signal output end to be connected to the first low node under the control of the potential of the first pull-down node. The voltage terminals are connected, and under the control of the potential of the second pull-down node, the control carry signal output terminal is connected to the first low voltage terminal.
在具体实施时，所述输入电路可以包括输入晶体管；In a specific implementation, the input circuit may include an input transistor;
所述输入晶体管的控制极和第一极都与所述输入端连接，所述输入晶体管的第二极与所述上拉节点连接；Both the control electrode and the first electrode of the input transistor are connected to the input terminal, and the second electrode of the input transistor is connected to the pull-up node;
所述第一下拉控制电路包括第一控制晶体管和第二控制晶体管；the first pull-down control circuit includes a first control transistor and a second control transistor;
所述第一控制晶体管的控制极与所述第一控制电压端连接，所述第一控制晶体管的第一极与所述第一控制电压端连接，所述第一控制晶体管的第二极与所述第一下拉节点连接；The control electrode of the first control transistor is connected to the first control voltage terminal, the first electrode of the first control transistor is connected to the first control voltage terminal, and the second electrode of the first control transistor is connected to the first control voltage terminal. the first drop-down node is connected;
所述第二控制晶体管的控制极与所述上拉节点连接，所述第二控制晶体管的第一极与所述第一下拉节点连接，所述第二控制晶体管的第二极与第二低电压端连接；The control electrode of the second control transistor is connected to the pull-up node, the first electrode of the second control transistor is connected to the first pull-down node, and the second electrode of the second control transistor is connected to the second pull-down node. Low voltage terminal connection;
所述第二下拉控制电路包括第三控制晶体管和第四控制晶体管；the second pull-down control circuit includes a third control transistor and a fourth control transistor;
所述第三控制晶体管的控制极与所述第二控制电压端连接，所述第三控制晶体管的第一极与所述第二控制电压端连接，所述第三控制晶体管的第二极与所述第二下拉节点连接；The control electrode of the third control transistor is connected to the second control voltage end, the first electrode of the third control transistor is connected to the second control voltage end, and the second electrode of the third control transistor is connected to the second control voltage end. the second drop-down node is connected;
所述第四控制晶体管的控制极与所述上拉节点连接，所述第四控制晶体管的第一极与所述第二下拉节点连接，所述第四控制晶体管的第二极与第二低电压端连接；The control electrode of the fourth control transistor is connected to the pull-up node, the first electrode of the fourth control transistor is connected to the second pull-down node, and the second electrode of the fourth control transistor is connected to the second low node. voltage terminal connection;
所述栅极驱动信号输出电路包括第一输出晶体管、第一输出下拉晶体管、第二输出下拉晶体管、输出复位晶体管和存储电容；The gate drive signal output circuit includes a first output transistor, a first output pull-down transistor, a second output pull-down transistor, an output reset transistor and a storage capacitor;
所述第一输出晶体管的控制极与所述上拉节点连接，所述第一输出晶体管的第一极与所述时钟信号端连接，所述第一输出晶体管的第二极与栅极驱动信号输出端连接；The control electrode of the first output transistor is connected to the pull-up node, the first electrode of the first output transistor is connected to the clock signal terminal, and the second electrode of the first output transistor is connected to the gate driving signal output connection;
所述第一输出下拉晶体管的控制极与所述第一下拉节点连接，所述第一输出下拉晶体管的第一极与所述栅极驱动信号输出端连接，所述第一输出下拉晶体管的第二极与所述第一低电压端连接；The control electrode of the first output pull-down transistor is connected to the first pull-down node, the first electrode of the first output pull-down transistor is connected to the gate driving signal output end, and the first output pull-down transistor is connected to the gate driving signal output terminal. The second pole is connected to the first low voltage terminal;
所述第二输出下拉晶体管的控制极与所述第二下拉节点连接，所述第二输出下拉晶体管的第一极与所述栅极驱动信号输出端连接，所述第二输出下拉晶体管的第二极与所述第一低电压端连接；The control electrode of the second output pull-down transistor is connected to the second pull-down node, the first electrode of the second output pull-down transistor is connected to the gate driving signal output end, and the second output pull-down transistor is connected to the gate driving signal output terminal. The diode is connected to the first low voltage terminal;
所述输出复位晶体管的控制极与所述第三复位端连接，所述输出复位晶体管的第一极与所述栅极驱动信号输出端连接，所述输出复位晶体管的第二极与所述第一低电压端连接；The control pole of the output reset transistor is connected to the third reset terminal, the first pole of the output reset transistor is connected to the gate drive signal output terminal, and the second pole of the output reset transistor is connected to the third reset terminal. A low-voltage terminal connection;
所述进位信号输出电路包括第二输出晶体管、第三输出下拉晶体管和第四输出下拉晶体管；The carry signal output circuit includes a second output transistor, a third output pull-down transistor and a fourth output pull-down transistor;
所述第二输出晶体管的控制极与所述上拉节点连接，所述第二输出晶体管的第一极与所述时钟信号端连接，所述第二输出晶体管的第二极与进位信号输出端连接；The control pole of the second output transistor is connected to the pull-up node, the first pole of the second output transistor is connected to the clock signal terminal, and the second pole of the second output transistor is connected to the carry signal output terminal connect;
所述第三输出下拉晶体管的控制极与所述第一下拉节点连接，所述第三输出下拉晶体管的第一极与所述进位信号输出端连接，所述第三输出下拉晶体管的第二极与所述第二低电压端连接；The control electrode of the third output pull-down transistor is connected to the first pull-down node, the first electrode of the third output pull-down transistor is connected to the carry signal output terminal, and the second output end of the third output pull-down transistor is connected to the carry signal output terminal. the pole is connected to the second low voltage terminal;
所述第四输出下拉晶体管的控制极与所述第二下拉节点连接，所述第四输出下拉晶体管的第一极与所述进位信号输出端连接，所述第四输出下拉晶体管的第二极与所述第二低电压端连接。The control electrode of the fourth output pull-down transistor is connected to the second pull-down node, the first electrode of the fourth output pull-down transistor is connected to the carry signal output terminal, and the second electrode of the fourth output pull-down transistor is connected connected to the second low voltage terminal.
下面通过两个具体实施例来说明本发明所述的栅极驱动单元。The gate driving unit according to the present invention will be described below through two specific embodiments.
如图5所示，本发明所述的栅极驱动单元的第一具体实施例包括上拉节点复位电路11、上拉节点下拉电路12、下拉节点控制电路14、输入电路、第一下拉控制电路，第二下拉控制电路、栅极驱动信号输出电路、进位信号输出电路和控制电路；As shown in FIG. 5 , the first specific embodiment of the gate driving unit of the present invention includes a pull-up node reset circuit 11 , a pull-up node pull-down circuit 12 , a pull-down node control circuit 14 , an input circuit, and a first pull-down control circuit. circuit, a second pull-down control circuit, a gate drive signal output circuit, a carry signal output circuit and a control circuit;
所述上拉节点复位电路11包括第一上拉节点复位晶体管M2和第二上拉节点复位晶体管M15；所述上拉节点下拉电路12包括第一上拉节点下拉晶体管M8A和第二上拉节点下拉晶体管M8B；所述控制电路包括电压提供电路(图5中未示出所述电压提供电路)；The pull-up node reset circuit 11 includes a first pull-up node reset transistor M2 and a second pull-up node reset transistor M15; the pull-up node pull-down circuit 12 includes a first pull-up node pull-down transistor M8A and a second pull-up node pull-down transistor M8B; the control circuit includes a voltage supply circuit (the voltage supply circuit is not shown in FIG. 5 );
M2的栅极与第一复位端RST连接，M2的漏极与上拉节点PU连接，M2的源极与第一低电压端连接；所述第一低电压端用于输入第一低电压VGL；The gate of M2 is connected to the first reset terminal RST, the drain of M2 is connected to the pull-up node PU, and the source of M2 is connected to the first low voltage terminal; the first low voltage terminal is used to input the first low voltage VGL ;
M15的栅极与第二复位端TGOA_RST连接，M15的漏极与上拉节点PU连接，M15的源极与第一低电压端连接；所述第一低电压端用于输入第一低电压VGL；The gate of M15 is connected to the second reset terminal TGOA_RST, the drain of M15 is connected to the pull-up node PU, and the source of M15 is connected to the first low voltage terminal; the first low voltage terminal is used to input the first low voltage VGL ;
M8A的栅极与第一下拉节点PD_A连接，M8A的漏极与所述上拉节点PU连接，M8A的源极与所述第一低电压端连接；The gate of M8A is connected to the first pull-down node PD_A, the drain of M8A is connected to the pull-up node PU, and the source of M8A is connected to the first low-voltage terminal;
M8B的栅极与第二下拉节点PD_B连接，M8B的漏极与所述上拉节点PU连接，M8B的源极与所述第一低电压端连接；The gate of M8B is connected to the second pull-down node PD_B, the drain of M8B is connected to the pull-up node PU, and the source of M8B is connected to the first low-voltage terminal;
所述下拉节点控制电路14包括第一下拉节点控制晶体管M7A和第二下拉节点控制晶体管M7B；The pull-down node control circuit 14 includes a first pull-down node control transistor M7A and a second pull-down node control transistor M7B;
所述第一下拉节点控制晶体管M7A的栅极与输入端INPUT连接，所述第一下拉节点控制晶体管M7A的漏极与所述第一下拉节点PD_A连接，所述第一下拉节点控制晶体管M7A的源极与第二低电压端连接；所述第二低电压端用于输入第二低电压LVGL；The gate of the first pull-down node control transistor M7A is connected to the input terminal INPUT, the drain of the first pull-down node control transistor M7A is connected to the first pull-down node PD_A, and the first pull-down node the source of the control transistor M7A is connected to the second low voltage terminal; the second low voltage terminal is used for inputting the second low voltage LVGL;
所述第二下拉节点控制晶体管M7B的栅极与所述输入端INPUT连接，所述第二下拉节点控制晶体管M7B的漏极与所述第二下拉节点PD_B连接，所述第二下拉节点控制晶体管M7B的源极与所述第二低电压端连接；The gate of the second pull-down node control transistor M7B is connected to the input terminal INPUT, the drain of the second pull-down node control transistor M7B is connected to the second pull-down node PD_B, and the second pull-down node controls the transistor The source of M7B is connected to the second low voltage terminal;
所述输入电路包括输入晶体管M1；The input circuit includes an input transistor M1;
所述输入晶体管M1的栅极和漏极都与所述输入端INPUT连接，所述输入晶体管M1的源极与所述上拉节点PU连接；The gate and drain of the input transistor M1 are both connected to the input terminal INPUT, and the source of the input transistor M1 is connected to the pull-up node PU;
所述第一下拉控制电路包括第一控制晶体管M5A和第二控制晶体管M6A；The first pull-down control circuit includes a first control transistor M5A and a second control transistor M6A;
所述第一控制晶体管M5A的栅极与所述第一控制电压端连接，所述第一控制晶体管M5A的漏极与所述第一控制电压端连接，所述第一控制晶体管M5A的第二极与所述第一下拉节点PD_A连接；所述第一控制电压端用于输入第一控制电压VDD_A；The gate of the first control transistor M5A is connected to the first control voltage terminal, the drain of the first control transistor M5A is connected to the first control voltage terminal, and the second control transistor M5A is connected to the first control voltage terminal. The pole is connected to the first pull-down node PD_A; the first control voltage terminal is used to input the first control voltage VDD_A;
所述第二控制晶体管M6A的栅极与所述上拉节点PU连接，所述第二控制晶体管M6A的漏极与所述第一下拉节点PD_A连接，所述第二控制晶体管M6A的源极与第二低电压端连接；The gate of the second control transistor M6A is connected to the pull-up node PU, the drain of the second control transistor M6A is connected to the first pull-down node PD_A, and the source of the second control transistor M6A connected with the second low voltage terminal;
所述第二下拉控制电路包括第三控制晶体管M5B和第四控制晶体管M6B；The second pull-down control circuit includes a third control transistor M5B and a fourth control transistor M6B;
所述第三控制晶体管M5B的栅极与所述第二控制电压端连接，所述第三控制晶体管M5B的漏极与所述第二控制电压端连接，所述第三控制晶体管M5B的源极与所述第二下拉节点PD_B连接；所述第二控制电压端用于输入第二控制电压VDD_B；The gate of the third control transistor M5B is connected to the second control voltage terminal, the drain of the third control transistor M5B is connected to the second control voltage terminal, and the source of the third control transistor M5B connected to the second pull-down node PD_B; the second control voltage terminal is used for inputting the second control voltage VDD_B;
所述第四控制晶体管M6B的栅极与所述上拉节点PU连接，所述第四控制晶体管M6B的漏极与所述第二下拉节点PD_B连接，所述第四控制晶体管M6B的第二极与第二低电压端连接；The gate of the fourth control transistor M6B is connected to the pull-up node PU, the drain of the fourth control transistor M6B is connected to the second pull-down node PD_B, and the second pole of the fourth control transistor M6B connected with the second low voltage terminal;
所述栅极驱动信号输出电路包括第一输出晶体管M3、第一输出下拉晶体管M13A、第二输出下拉晶体管M13B、输出复位晶体管M4和存储电容Cs；The gate drive signal output circuit includes a first output transistor M3, a first output pull-down transistor M13A, a second output pull-down transistor M13B, an output reset transistor M4 and a storage capacitor Cs;
所述第一输出晶体管M3的栅极与所述上拉节点PU连接，所述第一输出晶体管M3的漏极与所述时钟信号端连接，所述第一输出晶体管M3的源极与栅极驱动信号输出端OUT1连接；所述时钟信号端用于输入时钟信号CLK；The gate of the first output transistor M3 is connected to the pull-up node PU, the drain of the first output transistor M3 is connected to the clock signal terminal, and the source and gate of the first output transistor M3 The drive signal output terminal OUT1 is connected; the clock signal terminal is used for inputting the clock signal CLK;
所述第一输出下拉晶体管M13A的栅极与所述第一下拉节点PD_A连接，所述第一输出下拉晶体管M13A的漏极与所述栅极驱动信号输出端OUT1连接，所述第一输出下拉晶体管M13A的源极与所述第一低电压端连接；The gate of the first output pull-down transistor M13A is connected to the first pull-down node PD_A, the drain of the first output pull-down transistor M13A is connected to the gate driving signal output terminal OUT1, and the first output the source of the pull-down transistor M13A is connected to the first low voltage terminal;
所述第二输出下拉晶体管M13B的栅极与所述第二下拉节点PD_B连接，所述第二输出下拉晶体管M13B的漏极与所述栅极驱动信号输出端OUT1连接，所述第二输出下拉晶体管M13B的源极与所述第一低电压端连接；The gate of the second output pull-down transistor M13B is connected to the second pull-down node PD_B, the drain of the second output pull-down transistor M13B is connected to the gate driving signal output terminal OUT1, and the second output pull-down transistor M13B is connected to the gate driving signal output terminal OUT1. the source of the transistor M13B is connected to the first low voltage terminal;
所述输出复位晶体管M4的栅极与所述第三复位端RST_2连接，所述输出复位晶体管M4的漏极与所述栅极驱动信号输出端OUT1连接，所述输出复位晶体管M4的源极与所述第一低电压端连接；The gate of the output reset transistor M4 is connected to the third reset terminal RST_2, the drain of the output reset transistor M4 is connected to the gate drive signal output terminal OUT1, and the source of the output reset transistor M4 is connected to the gate drive signal output terminal OUT1. the first low voltage terminal is connected;
所述进位信号输出电路包括第二输出晶体管M11、第三输出下拉晶体管M13A和第四输出下拉晶体管M13B；The carry signal output circuit includes a second output transistor M11, a third output pull-down transistor M13A and a fourth output pull-down transistor M13B;
所述第二输出晶体管M11的栅极与所述上拉节点PU连接，所述第二输出晶体管M11的漏极与所述时钟信号端连接，所述第二输出晶体管M11的源极与进位信号输出端OUT_C连接；The gate of the second output transistor M11 is connected to the pull-up node PU, the drain of the second output transistor M11 is connected to the clock signal terminal, and the source of the second output transistor M11 is connected to the carry signal The output terminal OUT_C is connected;
所述第三输出下拉晶体管M13A的栅极与所述第一下拉节点PD_A连接，所述第三输出下拉晶体管M13的漏极与所述进位信号输出端OUT_C连接，所述第三输出下拉晶体管M13A的源极与所述第二低电压端连接；The gate of the third output pull-down transistor M13A is connected to the first pull-down node PD_A, the drain of the third output pull-down transistor M13 is connected to the carry signal output terminal OUT_C, and the third output pull-down transistor The source of M13A is connected to the second low voltage terminal;
所述第四输出下拉晶体管M13B的栅极与所述第二下拉节点PD_B连接，所述第四输出下拉晶体管M13B的漏极与所述进位信号输出端OUT_C连接，所述第四输出下拉晶体管M13B的源极与所述第二低电压端连接；The gate of the fourth output pull-down transistor M13B is connected to the second pull-down node PD_B, the drain of the fourth output pull-down transistor M13B is connected to the carry signal output terminal OUT_C, and the fourth output pull-down transistor M13B The source is connected to the second low voltage terminal;
所述电压提供电路与所述第一低电压端连接，用于提供所述第一低电压VGL，以使得在输出阶段，M2的栅源电压、M15的栅源电压，M8A的栅源电压和M8B的栅源电压都小于或等于0，以使得在输出阶段，M2、M15、M8A和M8B都完全关断，减小M2的漏电流、M15的漏电流、M8A的漏电流和M8B的漏电流。The voltage supply circuit is connected to the first low voltage terminal for supplying the first low voltage VGL, so that in the output stage, the gate-source voltage of M2, the gate-source voltage of M15, the gate-source voltage of M8A and The gate-source voltage of M8B is less than or equal to 0, so that in the output stage, M2, M15, M8A and M8B are completely turned off, reducing the leakage current of M2, the leakage current of M15, the leakage current of M8A and the leakage current of M8B .
在本发明如图5所示的栅极驱动单元的第一具体实施例中，所有的晶体管都为NMOS管，但不以此为限。In the first specific embodiment of the gate driving unit shown in FIG. 5 of the present invention, all transistors are NMOS transistors, but not limited thereto.
本发明如图5所示的栅极驱动单元的第一具体实施例在工作时，所述电压提供电路向所述第一低电压端提供所述第一低电压VGL，以使得在输出阶段，M2的栅源电压、M15的栅源电压，M8A的栅源电压和M8B的栅源电压都小于或等于0，以使得在输出阶段，M2、M15、M8A和M8B都完全关断，减小M2的漏电流、M15的漏电流、M8A的漏电流和M8B的漏电流。When the first specific embodiment of the gate driving unit of the present invention as shown in FIG. 5 is in operation, the voltage supply circuit provides the first low voltage VGL to the first low voltage terminal, so that in the output stage, The gate-source voltage of M2, the gate-source voltage of M15, the gate-source voltage of M8A and the gate-source voltage of M8B are all less than or equal to 0, so that in the output stage, M2, M15, M8A and M8B are all turned off, reducing M2 leakage current of M15, leakage current of M8A and leakage current of M8B.
本发明如图5所示的栅极驱动单元的第一具体实施例在工作时，在输出阶段，M15的栅极的电位和M2的栅极的电位都为VGL，M8A的栅极的电位和M8B的栅极的电位略高于LVGL，M15的源极的电位、M2的源极的电位、M8A的源极的电位和M8B的源极的电位都为VGL，所述电压提供电路提供VGL，VGL高于LVGL，以使得M15的栅源电压和M2的栅源电压等于0、M8A的栅源电压和M8B的栅源电压都小于0，以减小M15的漏电流、M2的漏电流、M8A的漏电流和M8B的漏电流。When the first specific embodiment of the gate driving unit of the present invention as shown in FIG. 5 is in operation, in the output stage, the potential of the gate of M15 and the potential of the gate of M2 are both VGL, and the potential of the gate of M8A and The potential of the gate of M8B is slightly higher than that of LVGL, the potential of the source of M15, the potential of the source of M2, the potential of the source of M8A and the potential of the source of M8B are all VGL, and the voltage supply circuit provides VGL, VGL is higher than LVGL, so that the gate-source voltage of M15 and the gate-source voltage of M2 are equal to 0, and the gate-source voltage of M8A and the gate-source voltage of M8B are both less than 0, so as to reduce the leakage current of M15, the leakage current of M2, and the leakage current of M8A. leakage current and leakage current of M8B.
在具体实施时，VGL可以为-8V，LVGL可以为-11V，但不以此为限。In a specific implementation, the VGL may be -8V, and the LVGL may be -11V, but not limited thereto.
本发明如图5所示的栅极驱动单元的第一具体实施例在工作时，如图6A所示，在输出阶段S2，PU的电位能够很好的保持为高电位。When the first specific embodiment of the gate driving unit of the present invention as shown in FIG. 5 is in operation, as shown in FIG. 6A , in the output stage S2 , the potential of the PU can be well maintained at a high potential.
并且，本发明如图5所示的栅极驱动单元的第一具体实施例在工作时，6B是OUT1输出的栅极驱动信号的波形图。Moreover, when the first specific embodiment of the gate driving unit of the present invention as shown in FIG. 5 is in operation, 6B is a waveform diagram of the gate driving signal output by OUT1.
由图6B可知，与图2B相比，所述栅极驱动信号的上升时间Tr减小，所述栅极驱动信号的下降时间Tf减小。It can be seen from FIG. 6B that, compared with FIG. 2B , the rising time Tr of the gate driving signal is reduced, and the falling time Tf of the gate driving signal is reduced.
如图7所示，本发明所述的栅极驱动单元的第二具体实施例包括上拉节点复位电路11、上拉节点下拉电路12、下拉节点控制电路14、输入电路、第一下拉控制电路，第二下拉控制电路、栅极驱动信号输出电路、进位信号输出电路和控制电路；所述控制电路包括电压提供电路和电压控制电路(图7中未示出所述电压提供电路和电压控制电路)；As shown in FIG. 7 , the second specific embodiment of the gate driving unit of the present invention includes a pull-up node reset circuit 11 , a pull-up node pull-down circuit 12 , a pull-down node control circuit 14 , an input circuit, and a first pull-down control circuit. circuit, a second pull-down control circuit, a gate drive signal output circuit, a carry signal output circuit and a control circuit; the control circuit includes a voltage supply circuit and a voltage control circuit (the voltage supply circuit and voltage control circuit are not shown in FIG. 7 ) circuit);
所述上拉节点复位电路11包括第一上拉节点复位晶体管M2和第二上拉节点复位晶体管M15；所述上拉节点下拉电路12包括第一上拉节点下拉晶体管M8A和第二上拉节点下拉晶体管M8B；The pull-up node reset circuit 11 includes a first pull-up node reset transistor M2 and a second pull-up node reset transistor M15; the pull-up node pull-down circuit 12 includes a first pull-up node pull-down transistor M8A and a second pull-up node pull-down transistor M8B;
M2的栅极与第一复位端RST连接，M2的漏极与上拉节点PU连接，M2的源极与第一低电压端连接；所述第一低电压端用于输入第一低电压VGL；The gate of M2 is connected to the first reset terminal RST, the drain of M2 is connected to the pull-up node PU, and the source of M2 is connected to the first low voltage terminal; the first low voltage terminal is used to input the first low voltage VGL ;
M15的栅极与第二复位端TGOA_RST连接，M15的漏极与上拉节点PU连接，M15的源极与第一低电压端连接；所述第一低电压端用于输入第一低电压VGL；The gate of M15 is connected to the second reset terminal TGOA_RST, the drain of M15 is connected to the pull-up node PU, and the source of M15 is connected to the first low voltage terminal; the first low voltage terminal is used to input the first low voltage VGL ;
M8A的栅极与第一下拉节点PD_A连接，M8A的漏极与所述上拉节点PU连接，M8A的源极与所述第一低电压端连接；The gate of M8A is connected to the first pull-down node PD_A, the drain of M8A is connected to the pull-up node PU, and the source of M8A is connected to the first low-voltage terminal;
M8B的栅极与第二下拉节点PD_B连接，M8B的漏极与所述上拉节点PU连接，M8B的源极与所述第一低电压端连接；The gate of M8B is connected to the second pull-down node PD_B, the drain of M8B is connected to the pull-up node PU, and the source of M8B is connected to the first low-voltage terminal;
所述电压提供电路与所述第一低电压端连接，用于提供所述第一低电压VGL，以使得在输出阶段，M2的栅源电压和M15的栅源电压都小于或等于0，以使得在输出阶段，M2和M15都完全关断，减小M2的漏电流和M15的漏电流；The voltage supply circuit is connected to the first low voltage terminal for supplying the first low voltage VGL, so that in the output stage, the gate-source voltage of M2 and the gate-source voltage of M15 are both less than or equal to 0, so that In the output stage, both M2 and M15 are completely turned off, reducing the leakage current of M2 and the leakage current of M15;
所述下拉节点控制电路14包括第一下拉节点控制晶体管M7A和第二下拉节点控制晶体管M7B；The pull-down node control circuit 14 includes a first pull-down node control transistor M7A and a second pull-down node control transistor M7B;
所述第一下拉节点控制晶体管M7A的栅极与输入端INPUT连接，所述第一下拉节点控制晶体管M7A的漏极与所述第一下拉节点PD_A连接，所述第一下拉节点控制晶体管M7A的源极与第三低电压端连接；所述第三低电压端用于输入第三低电压LLVGL；The gate of the first pull-down node control transistor M7A is connected to the input terminal INPUT, the drain of the first pull-down node control transistor M7A is connected to the first pull-down node PD_A, and the first pull-down node The source of the control transistor M7A is connected to the third low voltage terminal; the third low voltage terminal is used to input the third low voltage LLVGL;
所述第二下拉节点控制晶体管M7B的栅极与所述输入端INPUT连接，所述第二下拉节点控制晶体管M7B的漏极与所述第二下拉节点PD_B连接，所述第二下拉节点控制晶体管M7B的源极与所述第三低电压端连接；The gate of the second pull-down node control transistor M7B is connected to the input terminal INPUT, the drain of the second pull-down node control transistor M7B is connected to the second pull-down node PD_B, and the second pull-down node controls the transistor The source of M7B is connected to the third low voltage terminal;
所述电压控制电路用于为所述第三低电压端提供所述第三低电压LLVGL，以使得在输出阶段，M8A的栅源电压和M8B的栅源电压小于或等于0；The voltage control circuit is configured to provide the third low voltage LLVGL to the third low voltage terminal, so that in the output stage, the gate-source voltage of M8A and the gate-source voltage of M8B are less than or equal to 0;
所述输入电路包括输入晶体管M1；The input circuit includes an input transistor M1;
所述输入晶体管M1的栅极和漏极都与所述输入端INPUT连接，所述输入晶体管M1的源极与所述上拉节点PU连接；The gate and drain of the input transistor M1 are both connected to the input terminal INPUT, and the source of the input transistor M1 is connected to the pull-up node PU;
所述第一下拉控制电路包括第一控制晶体管M5A和第二控制晶体管M6A；The first pull-down control circuit includes a first control transistor M5A and a second control transistor M6A;
所述第一控制晶体管M5A的栅极与所述第一控制电压端连接，所述第一控制晶体管M5A的漏极与所述第一控制电压端连接，所述第一控制晶体管M5A的第二极与所述第一下拉节点PD_A连接；所述第一控制电压端用于输入第一控制电压VDD_A；The gate of the first control transistor M5A is connected to the first control voltage terminal, the drain of the first control transistor M5A is connected to the first control voltage terminal, and the second control transistor M5A is connected to the first control voltage terminal. The pole is connected to the first pull-down node PD_A; the first control voltage terminal is used to input the first control voltage VDD_A;
所述第二控制晶体管M6A的栅极与所述上拉节点PU连接，所述第二控制晶体管M6A的漏极与所述第一下拉节点PD_A连接，所述第二控制晶体管M6A的源极与第二低电压端连接；The gate of the second control transistor M6A is connected to the pull-up node PU, the drain of the second control transistor M6A is connected to the first pull-down node PD_A, and the source of the second control transistor M6A connected with the second low voltage terminal;
所述第二下拉控制电路包括第三控制晶体管M5B和第四控制晶体管M6B；The second pull-down control circuit includes a third control transistor M5B and a fourth control transistor M6B;
所述第三控制晶体管M5B的栅极与所述第二控制电压端连接，所述第三控制晶体管M5B的漏极与所述第二控制电压端连接，所述第三控制晶体管M5B的源极与所述第二下拉节点PD_B连接；所述第二控制电压端用于输入第二控制电压VDD_B；The gate of the third control transistor M5B is connected to the second control voltage terminal, the drain of the third control transistor M5B is connected to the second control voltage terminal, and the source of the third control transistor M5B connected to the second pull-down node PD_B; the second control voltage terminal is used for inputting the second control voltage VDD_B;
所述第四控制晶体管M6B的栅极与所述上拉节点PU连接，所述第四控制晶体管M6B的漏极与所述第二下拉节点PD_B连接，所述第四控制晶体管M6B的第二极与第二低电压端连接；The gate of the fourth control transistor M6B is connected to the pull-up node PU, the drain of the fourth control transistor M6B is connected to the second pull-down node PD_B, and the second pole of the fourth control transistor M6B connected with the second low voltage terminal;
所述栅极驱动信号输出电路包括第一输出晶体管M3、第一输出下拉晶体管M13A、第二输出下拉晶体管M13B、输出复位晶体管M4和存储电容Cs；The gate drive signal output circuit includes a first output transistor M3, a first output pull-down transistor M13A, a second output pull-down transistor M13B, an output reset transistor M4 and a storage capacitor Cs;
所述第一输出晶体管M3的栅极与所述上拉节点PU连接，所述第一输出晶体管M3的漏极与所述时钟信号端连接，所述第一输出晶体管M3的源极与栅极驱动信号输出端OUT1连接；所述时钟信号端用于输入时钟信号CLK；The gate of the first output transistor M3 is connected to the pull-up node PU, the drain of the first output transistor M3 is connected to the clock signal terminal, and the source and gate of the first output transistor M3 The drive signal output terminal OUT1 is connected; the clock signal terminal is used for inputting the clock signal CLK;
所述第一输出下拉晶体管M13A的栅极与所述第一下拉节点PD_A连接，所述第一输出下拉晶体管M13A的漏极与所述栅极驱动信号输出端OUT1连接，所述第一输出下拉晶体管M13A的源极与所述第一低电压端连接；The gate of the first output pull-down transistor M13A is connected to the first pull-down node PD_A, the drain of the first output pull-down transistor M13A is connected to the gate driving signal output terminal OUT1, and the first output the source of the pull-down transistor M13A is connected to the first low voltage terminal;
所述第二输出下拉晶体管M13B的栅极与所述第二下拉节点PD_B连接，所述第二输出下拉晶体管M13B的漏极与所述栅极驱动信号输出端OUT1连接，所述第二输出下拉晶体管M13B的源极与所述第一低电压端连接；The gate of the second output pull-down transistor M13B is connected to the second pull-down node PD_B, the drain of the second output pull-down transistor M13B is connected to the gate driving signal output terminal OUT1, and the second output pull-down transistor M13B is connected to the gate driving signal output terminal OUT1. the source of the transistor M13B is connected to the first low voltage terminal;
所述输出复位晶体管M4的栅极与所述第三复位端RST_2连接，所述输出复位晶体管M4的漏极与所述栅极驱动信号输出端OUT1连接，所述输出复位晶体管M4的源极与所述第一低电压端连接；The gate of the output reset transistor M4 is connected to the third reset terminal RST_2, the drain of the output reset transistor M4 is connected to the gate driving signal output terminal OUT1, and the source of the output reset transistor M4 is connected to the gate drive signal output terminal OUT1. the first low voltage terminal is connected;
所述进位信号输出电路包括第二输出晶体管M11、第三输出下拉晶体管M13A和第四输出下拉晶体管M13B；The carry signal output circuit includes a second output transistor M11, a third output pull-down transistor M13A and a fourth output pull-down transistor M13B;
所述第二输出晶体管M11的栅极与所述上拉节点PU连接，所述第二输出晶体管M11的漏极与所述时钟信号端连接，所述第二输出晶体管M11的源极与进位信号输出端OUT_C连接；The gate of the second output transistor M11 is connected to the pull-up node PU, the drain of the second output transistor M11 is connected to the clock signal terminal, and the source of the second output transistor M11 is connected to the carry signal The output terminal OUT_C is connected;
所述第三输出下拉晶体管M13A的栅极与所述第一下拉节点PD_A连接，所述第三输出下拉晶体管M13的漏极与所述进位信号输出端OUT_C连接，所述第三输出下拉晶体管M13A的源极与所述第二低电压端连接；The gate of the third output pull-down transistor M13A is connected to the first pull-down node PD_A, the drain of the third output pull-down transistor M13 is connected to the carry signal output terminal OUT_C, and the third output pull-down transistor The source of M13A is connected to the second low voltage terminal;
所述第四输出下拉晶体管M13B的栅极与所述第二下拉节点PD_B连接，所述第四输出下拉晶体管M13B的漏极与所述进位信号输出端OUT_C连接，所述第四输出下拉晶体管M13B的源极与所述第二低电压端连接。The gate of the fourth output pull-down transistor M13B is connected to the second pull-down node PD_B, the drain of the fourth output pull-down transistor M13B is connected to the carry signal output terminal OUT_C, and the fourth output pull-down transistor M13B The source is connected to the second low voltage terminal.
在本发明如图7所示的栅极驱动单元的第二具体实施例中，所有的晶体管都为NMOS管，但不以此为限。In the second specific embodiment of the gate driving unit shown in FIG. 7 of the present invention, all transistors are NMOS transistors, but not limited thereto.
本发明如图7所示的栅极驱动单元的第二具体实施例在工作时，所述电压提供电路向所述第一低电压端提供所述第一低电压VGL，以使得在输出阶段，M2的栅源电压、M15的栅源电压都等于0，以使得在输出阶段，M2和M15完全关断，减小M2的漏电流和M15的漏电流。When the second specific embodiment of the gate driving unit of the present invention as shown in FIG. 7 is in operation, the voltage supply circuit provides the first low voltage VGL to the first low voltage terminal, so that in the output stage, The gate-source voltage of M2 and the gate-source voltage of M15 are both equal to 0, so that in the output stage, M2 and M15 are completely turned off, reducing the leakage current of M2 and the leakage current of M15.
本发明如图7所示的栅极驱动单元的第二具体实施例在工作时，所述电压控制电路向所述第三低电压端提供所述第三低电压LLVGL，LLVGL小于LVGL，以使得在输出阶段，PD_A的电位和PD_B的电位略高于LLVGL，进而使得在输出阶段，M8A的栅源电压和M8B的栅源电压小于0，以减小M8A的漏电流和M8B的漏电流。When the second specific embodiment of the gate driving unit of the present invention as shown in FIG. 7 is in operation, the voltage control circuit provides the third low voltage LLVGL to the third low voltage terminal, and LLVGL is smaller than LVGL, so that In the output stage, the potentials of PD_A and PD_B are slightly higher than LLVGL, so that in the output stage, the gate-source voltage of M8A and the gate-source voltage of M8B are less than 0, so as to reduce the leakage current of M8A and the leakage current of M8B.
在具体实施时，LLVGL可以为-15V，但不以此为限。In a specific implementation, LLVGL can be -15V, but not limited thereto.
本发明实施例所述的栅极驱动方法，应用于上述的栅极驱动单元，所述栅极驱动方法包括：The gate driving method according to the embodiment of the present invention is applied to the above-mentioned gate driving unit, and the gate driving method includes:
在输出阶段，控制电路控制上拉节点复位电路中的与上拉节点连接的晶体管的栅源电压在第一预定电压范围内，并控制上拉节点下拉电路中的与上拉节点连接的晶体管的栅源电压在第二预定电压范围内。In the output stage, the control circuit controls the gate-source voltage of the transistor connected to the pull-up node in the pull-up node reset circuit to be within the first predetermined voltage range, and controls the transistors connected to the pull-up node in the pull-up node pull-down circuit. The gate-source voltage is within a second predetermined voltage range.
本发明实施例所述的栅极驱动方法在输出阶段，控制减小所述上拉节点复位电路中的与上拉节点连接的晶体管的漏电流，并控制减小所述上拉节点下拉电路中的与上拉节点连接的晶体管的漏电流，从而能够在输出阶段很好的保持上拉节点的电位，保证所述栅极驱动单元的驱动能力。In the output stage of the gate driving method according to the embodiment of the present invention, the leakage current of the transistor connected to the pull-up node in the pull-up node reset circuit is controlled to decrease, and the leakage current of the pull-up node pull-down circuit is controlled to decrease. Therefore, the potential of the pull-up node can be well maintained in the output stage, and the driving capability of the gate driving unit can be ensured.
具体的，所述上拉节点复位电路中的与上拉节点连接的晶体管可以为n型晶体管，所述第一预定电压范围为小于或等于0；或者，Specifically, the transistor connected to the pull-up node in the pull-up node reset circuit may be an n-type transistor, and the first predetermined voltage range is less than or equal to 0; or,
所述上拉节点复位电路中的与上拉节点连接的晶体管可以为p型晶体管，所述第一预定电压范围为大于或等于0。The transistor connected to the pull-up node in the pull-up node reset circuit may be a p-type transistor, and the first predetermined voltage range is greater than or equal to zero.
具体的，所述上拉节点下拉电路中的与上拉节点连接的晶体管可以为n型晶体管，所述第二预定电压范围为小于或等于0；或者，Specifically, the transistor connected to the pull-up node in the pull-up node pull-down circuit may be an n-type transistor, and the second predetermined voltage range is less than or equal to 0; or,
所述上拉节点下拉电路中的与上拉节点连接的晶体管为p型晶体管，所述第二预定电压范围为大于或等于0。The transistor connected to the pull-up node in the pull-up node pull-down circuit is a p-type transistor, and the second predetermined voltage range is greater than or equal to zero.
本发明实施例所述的栅极驱动电路包括多级上述的栅极驱动单元。The gate driving circuit according to the embodiment of the present invention includes multiple stages of the above-mentioned gate driving units.
本发明实施例所述的显示装置包括上述的栅极驱动电路。The display device according to the embodiment of the present invention includes the above-mentioned gate driving circuit.
本发明实施例所提供的显示装置可以为手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。The display device provided by the embodiment of the present invention may be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, and a navigator.
以上所述是本发明的优选实施方式，应当指出，对于本技术领域的普通技术人员来说，在不脱离本发明所述原理的前提下，还可以作出若干改进和润饰，这些改进和润饰也应视为本发明的保护范围。The above are the preferred embodiments of the present invention. It should be pointed out that for those skilled in the art, without departing from the principles of the present invention, several improvements and modifications can be made. It should be regarded as the protection scope of the present invention.
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