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CN109659362A - A kind of structure and preparation method thereof based on the low ohm contact resistance of gallium nitride power HEMT structure - Google Patents

A kind of structure and preparation method thereof based on the low ohm contact resistance of gallium nitride power HEMT structure Download PDF

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CN109659362A
CN109659362A CN201811384305.1A CN201811384305A CN109659362A CN 109659362 A CN109659362 A CN 109659362A CN 201811384305 A CN201811384305 A CN 201811384305A CN 109659362 A CN109659362 A CN 109659362A
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gallium nitride
layer
contact resistance
ohm contact
power hemt
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陈兴
王东
吴勇
张进成
何滇
伍旭东
檀生辉
卫祥
张金生
郝跃
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Wuhu Research Institute of Xidian University
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Wuhu Research Institute of Xidian University
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    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00Field-effect transistors [FET]
    • H10D30/40FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels
    • H10D30/47FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels having 2D charge carrier gas channels, e.g. nanoribbon FETs or high electron mobility transistors [HEMT]
    • H10D30/471High electron mobility transistors [HEMT] or high hole mobility transistors [HHMT]
    • H10D30/473High electron mobility transistors [HEMT] or high hole mobility transistors [HHMT] having confinement of carriers by multiple heterojunctions, e.g. quantum well HEMT
    • H10D30/4732High electron mobility transistors [HEMT] or high hole mobility transistors [HHMT] having confinement of carriers by multiple heterojunctions, e.g. quantum well HEMT using Group III-V semiconductor material
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28575Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising AIIIBV compounds
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00Field-effect transistors [FET]
    • H10D30/01Manufacture or treatment
    • H10D30/015Manufacture or treatment of FETs having heterojunction interface channels or heterojunction gate electrodes, e.g. HEMT
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00Field-effect transistors [FET]
    • H10D30/60Insulated-gate field-effect transistors [IGFET]
    • H10D30/67Thin-film transistors [TFT]
    • H10D30/6729Thin-film transistors [TFT] characterised by the electrodes
    • H10D30/6737Thin-film transistors [TFT] characterised by the electrodes characterised by the electrode materials
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00Field-effect transistors [FET]
    • H10D30/60Insulated-gate field-effect transistors [IGFET]
    • H10D30/67Thin-film transistors [TFT]
    • H10D30/674Thin-film transistors [TFT] characterised by the active materials
    • H10D30/675Group III-V materials, Group II-VI materials, Group IV-VI materials, selenium or tellurium

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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
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Abstract

一种基于氮化镓功率HEMT结构低欧姆接触电阻的结构及其制作方法,属于微电子技术领域,包括衬底、低温氮化镓成核层、氮化镓缓冲层、氮化镓沟道层、氮化铝插入层、铝镓氮势垒层、漏电极、源电极、栅电极和介质层,其中漏电极和源电极分居栅电极的两端,栅电极与铝镓氮势垒层之间还设有介质层,在氮化镓沟道层与铝镓氮势垒层之间形成二维电子气沟道,本发明制造工艺简单,重复性好,适用于GaN基功率HEMT器件应用。

A low-ohmic contact resistance structure based on a gallium nitride power HEMT structure and a manufacturing method thereof belong to the technical field of microelectronics, and include a substrate, a low-temperature gallium nitride nucleation layer, a gallium nitride buffer layer, and a gallium nitride channel layer , an aluminum nitride insertion layer, an aluminum gallium nitride barrier layer, a drain electrode, a source electrode, a gate electrode and a dielectric layer, wherein the drain electrode and the source electrode are separated at both ends of the gate electrode, and between the gate electrode and the aluminum gallium nitride barrier layer A dielectric layer is also provided to form a two-dimensional electron gas channel between the gallium nitride channel layer and the aluminum gallium nitrogen barrier layer.

Description

A kind of structure and its system based on the low ohm contact resistance of gallium nitride power HEMT structure Make method
Technical field
The invention belongs to microelectronics technology, specifically a kind of nitrogen based on Sn/Ti/Al/Ti/Au composite construction Change the production method of gallium HEMT low resistance Ohmic contact, the device of preparation can be used for high-power application.
Background technique
Third generation semiconductor material, that is, broad stopband (Wide Band Gap Semiconductor, abbreviation WBGS) semiconductor Material is grown up after first generation silicon, germanium and second generation GaAs, indium phosphide etc..In third generation semiconductor material, Gallium nitride (GaN) have broad-band gap, direct band gap, high breakdown electric field, lower dielectric constant, high electronics saturation drift velocity, Capability of resistance to radiation by force and the superior property such as good chemical stability, becomes and manufactures the micro- electricity of a new generation after germanium, silicon, GaAs The key semiconductor material of sub- device and circuit.Especially high temperature, high-power, high frequency and Flouride-resistani acid phesphatase electronic device and all-wave There is advantageous advantage in terms of long and short wavelength photoelectric device, be to realize high temperature and high-power, high frequency and anti-radiation, all-wave The ideal material of long photoelectric device, be the new and high technologies such as microelectronics, power electronics, photoelectron and national defense industry, information industry, The pillar industries such as mechanical and electrical industry and energy industry, which enter after 21 century to rely, continues the key basic material of development.
GaN base HEMT device is on the hetero-junctions that can form two-dimensional electron gas (2DEG) with metalloid semiconductcor field effect The technique of transistor (MESFET) is answered to be fabricated to, the main conductance between source and drain is provided by 2DEG conducting channel, then by Schottky gate in AlGaN potential barrier is biased to change the thickness of depletion region, to control the concentration and device of channel 2DEG The working condition of part." the power GaN: extension, device, application and technology issued according to YoleD é veloppement company's last year Trend -2017 editions " report, 2016, Global Power GaN market scale had reached 14,000,000 dollars.Power GaN technology with It is estimated in a short time to show huge market potential by means of its high-performance and high frequency solution applicability.
Summary of the invention
It is an object of the invention to be directed to the difficult point of the high ohmic contact resistance of gallium nitride HEMT power device, from device technology The optimization angle of preparation process proposes the gallium nitride HEMT low resistance Ohmic contact based on Sn/Ti/Al/Ti/Au composite construction Production method improves the performance of HEMT device to reduce ohmic contact resistance.
To achieve the above object, each layer of device architecture of the invention is successively arranged from bottom to up, including substrate, low temperature nitride Gallium nucleating layer, nitride buffer layer, gallium nitride channel layer, aln inserting layer, aluminum gallium nitride barrier layer, drain electrode, source electrode, grid Electrode and dielectric layer, wherein the both ends of drain electrode and source electrode separation gate electrode, also set between gate electrode and aluminum gallium nitride barrier layer There is dielectric layer, forms Two-dimensional electron gas channel between aln inserting layer and aluminum gallium nitride barrier layer.
Preferably, the substrate is all material that can be used to epitaxial nitride gallium film, including insulation or semi-insulated The materials such as sapphire, silicon, silicon carbide, gallium nitride and diamond.
Preferably, low temperature nitride gallium nucleating layer, 400-700 DEG C of growth temperature, film thickness 10-50nm, for being subsequent Nitride buffer layer growth provide nucleation node, improve gallium nitride film crystalline quality.
Preferably, the nitride buffer layer, to use metal organic source chemical vapor deposition (MOCVD) or other methods The gallium nitride film layer that unintentional doped growing is formed, film thickness range are 100nm-10um.Its quality directly affects then The quality of the hetero-junctions of growth, the various lattice defects in the region can also trapped electron, to influence the density of 2DEG.
Preferably, what is formed at the gallium nitride channel layer, aluminum gallium nitride insert layer and AlGaN barrier functions bed boundary is highly concentrated Spend the channel of 2DEG.
Preferably, the drain electrode and source electrode are closed using tin/titanium/aluminium/titanium/gold (Sn/Ti/Al/Ti/Au) multilayer Gold.Tin metal layer forms N-type heavy doping with a thickness of 1-20nm, reduces ohmic contact resistance.
Preferably, the gate electrode is conventional Schottky contacts or metal-dielertric-semiconductor structure.
Preferably, the insulating medium layer is SiNxOr SiO2Thin-film material is straight with gate electrode for completely cutting off AlGaN Contact reduces grid leak electricity, improves device electric breakdown strength.
Preferably, Ohmic contact refers to contact of the Sn/Ti/Al/Ti/Au alloy with AlGaN/GaN, the resistance of contact surface Value is much smaller than the resistance of semiconductor itself, will not generate apparent additional impedance, will not make inside AlGaN/GaN hetero-junctions Significant change occurs for equilibrium carrier concentration.When device works, most voltage drop is at behaviour area (Active region) Without the C-V characteristic in contact surface, during will not influence.In high frequency and high power device, Ohmic contact is to design and manufacture One of critical issue.
The Ohmic contact is prepared on the principle AlGaN/GaN hetero-junctions using tunnel-effect.Metal and When semiconductor contact, if doping content of semiconductor is very high, potential barrier sector width can be thinning, and ohmic contact resistance becomes smaller, and electronics is very It is easy to generate tunnel current by tunnel-effect.Its contact resistance size is defined by formula 1:
Wherein, mn *Indicate that electron effective mass, ε indicate dielectric constant, NDIndicate doping concentration.It can be seen from formula 1 Doping concentration is higher, contact resistance RcSmaller, present invention introduces Sn metal, the first purpose is to improve AlGaN/GaN hetero-junctions The electron adulterated concentration of the N-type on surface.
The ohmic contact resistance generally uses transmission line model (Transmission Line Model:TLM) to carry out Measurement.Table top is formed by etachable material surface, is fabricated to a series of a length of W linearly arranged, the rectangular metal electricity that width is d Pole.A different spacing is all corresponding between every two adjacent electrode, all-in resistance R consists of two parts:
Wherein, Rc is contact resistance size, RSHFor the square resistance of material, L is the spacing of adjacent two electrode.
Preferably, the Schottky contacts refer to contact of the alloys such as Ni/Au with AlGaN/GaN, since the two combines Contact berrier is higher afterwards, forms Schottky contacts.
Preferably, the Sn/Ti/Al/Ti/Au alloy is prepared using electron beam evaporation method, successively sputter Sn, Five kinds of materials of Ti, Al, Ti, Au form multiple layer metal, finally form alloy by high annealing.
Preferably, the Ti/Al/Ti/Au is as traditional alloying metal, and wherein Al is natural Ohmic contact material Material, basic work function is low, using affected for main material;First layer Ti can form TiN, while shape with bottom AlGaN/GaN At a large amount of vacancy N for playing n-type doping, contact resistance is reduced;Protective layer of the Au as top layer, protects alloy not by air oxygen Change;Second layer Ti prevents Au from permeating downwards as barrier layer.
Preferably, the Sn is formed with bottom AlGaN/GaN phase separation as the film layer deposited at first and is largely played n The vacancy N of type doping, reduces contact berrier.
Preferably, the high-temperature annealing process, temperature range are 300 DEG C -1000 DEG C, annealing time 5-300s.
Preferably, the ohmic contact resistance is capable of mutual conductance and the saturation current of effective influence HEMT device.Ohm Contact resistance is lower, and the mutual conductance of device is higher, and saturation current is bigger, and the electrical characteristics of device are better.
Preferably, the Sn metal layer with a thickness of 3nm, 5nm or 8nm.
Compared with prior art, the invention has the advantages that and technical effect:
The device is a kind of HEMT devices of GaN base, the Ohmic contact formed using this method, For contact resistance lower than the state of the art (reducing by 0.2 Ω .cm or so), the conducting resistance of device can decline 10%-20%, mutual conductance Increase 5%-15%, and manufacturing process is simple, reproducible feature.In combination with the original high threshold electricity of device HEMT Pressure, high-breakdown-voltage, high current density and excellent pinch-off behavior are suitable for high-power electronic device applications.
Detailed description of the invention
Fig. 1 is the structural diagram of the present invention.
Wherein: 101- substrate, 102- nucleating layer, 103- buffer layer, 104- channel layer, 105- insert layer, 106- aluminum gallium nitride Barrier layer, 107- drain electrode, 108- source electrode, 109- gate electrode, 110- Two-dimensional electron gas channel, 111- dielectric layer.
Specific embodiment
To be easy to understand the technical means, the creative features, the aims and the efficiencies achieved by the present invention, below with reference to Specific embodiment, the present invention is further explained.
Each layer of device architecture of the invention is successively arranged from bottom to up, comprising: substrate 101, low temperature nitride gallium nucleating layer 102, nitride buffer layer 103, gallium nitride channel layer 104, aln inserting layer 105, aluminum gallium nitride barrier layer 106, drain electrode 107, source electrode 108, gate electrode 109 and dielectric layer 111, wherein drain electrode 107 and source electrode 108 are lived apart the two of gate electrode 109 End, is additionally provided with dielectric layer 111, in aln inserting layer 105 and aluminum gallium nitride gesture between gate electrode 109 and aluminum gallium nitride barrier layer 106 Two-dimensional electron gas channel 110 is formed between barrier layer 106.Device architecture of the invention is prepared by the following method:
Embodiment 1
(1) use MOCVD technology and equipment in the substrate insulation or semi-insulated sapphire, silicon, carbonization of 6inch size The materials such as silicon, gallium nitride, zinc oxide and diamond carry out AlGaN/GaN heterogenous junction epitaxy.The technology is general traditional technology, AlGaN/GaN heterojunction structure successively includes GaN buffer layer 102, low temperature GaN nucleating layer 103, GaN channel layer 104, AlGaN gesture Build the Two-dimensional electron gas channel 110 of the high concentration 2DEG of functional layer 105 and interface formation.
(2) it is deposited using plasma-reinforced chemical deposition method (PECVD) on above-mentioned AlGaN/GaN heterojunction material surface Layer of sin x film layer is as dielectric layer, with a thickness of 100nm.
(3) above-mentioned material for obtaining step (2) carries out organic washing, will using lithography and etching technology after cleaning The thin film dielectric layer at hetero-junctions both ends is dispelled, remaining place retains photoresist coating, forms source-drain electrode groove.
(4) by step (3) obtain above-mentioned material carry out organic washing, after cleaning using electron beam evaporation technique into Row metal deposition.Tin (Sn), titanium (Ti), aluminium (Al), titanium (Ti) and golden (Au) five kinds of metals are sequentially depositing, wherein x value is 10%, the thickness of five layers of metal layer is respectively 3nm, 20nm, 1500nm, 30nm and 100nm.Metal-stripping is used after vapor deposition Equipment dispels the multiple layer metal above photoresist, forms the figure for only having above-mentioned hetero-junctions both ends just to there is the multiple layer metal Case.
(5) above-mentioned material for obtaining step (4) carries out organic washing, carries out at annealing after cleaning to above-mentioned material Reason, annealing temperature are 830 DEG C, annealing time 30s.
(6) above-mentioned material for obtaining step (5) carries out organic washing, will using lithography and etching technology after cleaning Thin film dielectric layer among hetero-junctions is dispelled, remaining place retains photoresist coating, forms gate electrode groove.
(7) by step (6) obtain above-mentioned material carry out organic washing, after cleaning using electron beam evaporation technique into Row metal deposition.It is sequentially depositing nickel (Ni), platinum (Pt), golden (Au) and four kinds of metals of titanium (Ti), thickness difference 15nm, 20nm, 5000nm and 5nm.The multiple layer metal above photoresist is dispelled using metal-stripping equipment after vapor deposition, formation only has Among above-mentioned hetero-junctions just there is the pattern of the multiple layer metal in gate electrode position.
Embodiment 2
(1) use MOCVD technology and equipment in the substrate insulation or semi-insulated sapphire, silicon, carbonization of 6inch size The materials such as silicon, gallium nitride, zinc oxide and diamond carry out AlGaN/GaN heterogenous junction epitaxy.The technology is general traditional technology, AlGaN/GaN heterojunction structure successively includes GaN buffer layer 102, low temperature GaN nucleating layer 103, GaN channel layer 104, AlGaN gesture Build the channel 110 of the high concentration 2DEG of functional layer 105 and interface formation.
(2) it is deposited using plasma-reinforced chemical deposition method (PECVD) on above-mentioned AlGaN/GaN heterojunction material surface Layer of sin x film layer is as dielectric layer, with a thickness of 150nm.
(3) above-mentioned material for obtaining step (2) carries out organic washing, will using lithography and etching technology after cleaning The thin film dielectric layer at hetero-junctions both ends is dispelled, remaining place retains photoresist coating, forms source-drain electrode groove.
(4) by step (3) obtain above-mentioned material carry out organic washing, after cleaning using electron beam evaporation technique into Row metal deposition.Tin (Sn), titanium (Ti), aluminium (Al), titanium (Ti) and golden (Au) five kinds of metals are sequentially depositing, wherein x value is 10%, the thickness of five layers of metal layer is respectively 5nm, 20nm, 1500nm, 30nm and 100nm.Metal-stripping is used after vapor deposition Equipment dispels the multiple layer metal above photoresist, forms the figure for only having above-mentioned hetero-junctions both ends just to there is the multiple layer metal Case.
(5) above-mentioned material for obtaining step (4) carries out organic washing, carries out at annealing after cleaning to above-mentioned material Reason, annealing temperature are 830 DEG C, annealing time 30s.
(6) above-mentioned material for obtaining step (5) carries out organic washing, will using lithography and etching technology after cleaning Thin film dielectric layer among hetero-junctions is removed, remaining place retains photoresist coating, forms gate electrode groove.
(7) by step (6) obtain above-mentioned material carry out organic washing, after cleaning using electron beam evaporation technique into Row metal deposition.It is sequentially depositing nickel (Ni), platinum (Pt), golden (Au) and four kinds of metals of titanium (Ti), thickness difference 15nm, 20nm, 5000nm and 5nm.The multiple layer metal above photoresist is dispelled using metal-stripping equipment after vapor deposition, formation only has Among above-mentioned hetero-junctions just there is the pattern of the multiple layer metal in gate electrode position.
Embodiment 3
(1) use MOCVD technology and equipment in the substrate insulation or semi-insulated sapphire, silicon, carbonization of 6inch size The materials such as silicon, gallium nitride, zinc oxide and diamond carry out AlGaN/GaN heterogenous junction epitaxy.The technology is general traditional technology, AlGaN/GaN heterojunction structure successively includes GaN buffer layer 102, low temperature GaN nucleating layer 103, GaN channel layer 104, AlGaN gesture Build the Two-dimensional electron gas channel 110 of the high concentration 2DEG of functional layer 105 and interface formation.
(2) it is deposited using plasma-reinforced chemical deposition method (PECVD) on above-mentioned AlGaN/GaN heterojunction material surface Layer of sin x film layer is as dielectric layer, with a thickness of 150nm.
(3) above-mentioned material for obtaining step (2) carries out organic washing, will using lithography and etching technology after cleaning The thin film dielectric layer at hetero-junctions both ends is dispelled, remaining place retains photoresist coating, forms source-drain electrode groove.
(4) by step (3) obtain above-mentioned material carry out organic washing, after cleaning using electron beam evaporation technique into Row metal deposition.Tin (Sn), titanium (Ti), aluminium (Al), titanium (Ti) and golden (Au) five kinds of metals are sequentially depositing, wherein x value is 10%, the thickness of five layers of metal layer is respectively 8nm, 20nm, 1500nm, 30nm and 100nm.Metal-stripping is used after vapor deposition Equipment dispels the multiple layer metal above photoresist, forms the figure for only having above-mentioned hetero-junctions both ends just to there is the multiple layer metal Case.
(5) above-mentioned material for obtaining step (4) carries out organic washing, carries out at annealing after cleaning to above-mentioned material Reason, annealing temperature are 830 DEG C, annealing time 30s.
(6) above-mentioned material for obtaining step (5) carries out organic washing, will using lithography and etching technology after cleaning Thin film dielectric layer among hetero-junctions is dispelled, remaining place retains photoresist coating, forms gate electrode groove.
(7) by step (6) obtain above-mentioned material carry out organic washing, after cleaning using electron beam evaporation technique into Row metal deposition.It is sequentially depositing nickel (Ni), platinum (Pt), golden (Au) and four kinds of metals of titanium (Ti), thickness difference 15nm, 20nm, 5000nm and 5nm.The multiple layer metal above photoresist is dispelled using metal-stripping equipment after vapor deposition, formation only has Among above-mentioned hetero-junctions just there is the pattern of the multiple layer metal in gate electrode position.
As known by the technical knowledge, the present invention can pass through the embodiment party of other essence without departing from its spirit or essential feature Case is realized.Therefore, embodiment disclosed above, in all respects are merely illustrative, not the only.Institute Have within the scope of the present invention or is included in the invention in the change being equal in the scope of the present invention.

Claims (10)

1. a kind of structure based on the low ohm contact resistance of gallium nitride power HEMT structure, which is characterized in that including substrate (101), low temperature nitride gallium nucleating layer (102), nitride buffer layer (103), gallium nitride channel layer (104), aln inserting layer (105), aluminum gallium nitride barrier layer (106), the drain electrode (107) at both ends of living apart and the grid electricity among source electrode (108) and the two Pole (109), above layers are successively arranged from bottom to up, are additionally provided with medium between gate electrode (109) and aluminum gallium nitride barrier layer (106) Layer (111).
2. a kind of structure based on the low ohm contact resistance of gallium nitride power HEMT structure according to claim 1, special Sign is that the material of substrate is any one in silicon, silicon carbide, gallium nitride and diamond.
3. a kind of structure based on the low ohm contact resistance of gallium nitride power HEMT structure according to claim 1, special Sign is, 400-700 DEG C of growth temperature of the low temperature nitride gallium nucleating layer (102), film thickness 10-50nm.
4. a kind of structure based on the low ohm contact resistance of gallium nitride power HEMT structure according to claim 1, special Sign is that the nitride buffer layer (103) deposits the partly exhausted of unintentional doped growing formation using metal organic vapor The gallium nitride film layer of edge high quality, film thickness range are 100nm-10um.
5. a kind of structure based on the low ohm contact resistance of gallium nitride power HEMT structure according to claim 1, special Sign is that the gallium nitride channel layer (104) deposits the partly exhausted of unintentional doped growing formation using metal organic vapor The gallium nitride channel thin-film layer of edge high quality, film thickness range are 50-200nm.
6. a kind of structure based on the low ohm contact resistance of gallium nitride power HEMT structure according to claim 1, special Sign is that the aln inserting layer (105) uses the semi-insulating high quality nitrogen of metal organic vapor deposition growing formation Change aluminium film insert layer, film thickness range is 1-5nm.
7. a kind of structure based on the low ohm contact resistance of gallium nitride power HEMT structure according to claim 1, special Sign is that the structural formula of the aluminum gallium nitride barrier layer (106) is AlxGa1-xN, wherein 0 < x < 1, with a thickness of 5-35nm.
8. a kind of structure based on the low ohm contact resistance of gallium nitride power HEMT structure according to claim 1, special Sign is that the drain electrode (107) and source electrode (108) of top two sides are all made of tin/titanium/aluminium/titanium/gold multilayer alloy, wherein tin Metal layer and aluminum gallium nitride barrier layer form N-type heavy doping, and tin metal layer is with a thickness of 2-10nm, drain electrode (107) and source electrode It (108) is prepared using the method for electron beam evaporation.
9. a kind of structure based on the low ohm contact resistance of gallium nitride power HEMT structure according to claim 8, special Sign is that tin/titanium/aluminium/titanium/gold multilayer alloy and the Ohmic contact method of aluminum gallium nitride barrier layer (106) are as follows:
In a nitrogen environment, by 600 DEG C -1000 DEG C of the thermal annealing process of 15-180s time, make tin/titanium/aluminium/titanium/gold Multilayer alloy and aluminum gallium nitride barrier layer (106) form Ohmic contact.
10. a kind of structure based on the low ohm contact resistance of gallium nitride power HEMT structure according to claim 1, special Sign is that the gate electrode (109) is Schottky junction structure or metal-dielertric-semiconductor structure.
CN201811384305.1A 2018-11-20 2018-11-20 A kind of structure and preparation method thereof based on the low ohm contact resistance of gallium nitride power HEMT structure Pending CN109659362A (en)

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Cited By (3)

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Publication number Priority date Publication date Assignee Title
CN110867488A (en) * 2019-11-28 2020-03-06 西安电子科技大学芜湖研究院 Gallium nitride HEMT device structure and preparation method thereof
CN112466770A (en) * 2020-11-20 2021-03-09 西安电子科技大学 Heterojunction device-based hot electron effect test structure and characterization method
CN114038750A (en) * 2021-11-05 2022-02-11 西安电子科技大学芜湖研究院 A kind of preparation method of gallium nitride power device

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Application publication date: 20190419