CN109597787B - SIO UART configuration method, system, device and readable storage medium - Google Patents

Abstract

The application discloses a method, a system, a device and a readable storage medium for configuring an SIO UART, comprising the following steps: determining information of an output port, wherein the information comprises an LPC address corresponding to the output port; in an SEC stage of the bios process, the LPC address is configured to a corresponding register in the SIO UART through the first preset configuration port and the second preset configuration port, respectively, so that the SIO UART outputs serial port information through the output port. According to the method and the device, the SIO UART is configured through the first preset configuration port and the second preset configuration port respectively at the SEC stage of the BIOS POST process, the configuration ports do not need to be determined in advance through chip selection signals, when the configuration ports are changed, the BIOS does not need to be compiled and burnt again, the configuration process is simple, serial port information can be normally output at the SEC stage, and monitoring on each operation stage of the BIOS is achieved.

Description

SIO UART configuration method, system, device and readable storage medium

technical field

The present application relates to the field of BIOS, and in particular, to a SIO UART configuration method, system, device and readable storage medium.

Background technique

AMI BIOS (Base Input/Output System, Basic Input/Output System) will select LPC (Low Pin Count, Low Pin Count) configuration port with address 0x2E/0x2F or LPC address 0x4E/0x4F configuration port pair according to hardware during design SIO (Super Input/Output, super input and output chip) UART (Universal Asynchronous Receiver/Transmitter, Universal Asynchronous Receiver/Transmitter) is configured, so that the problem location can be quickly located through the serial port information output by the SIO UART in the event of a downtime.

In the prior art, the 0x2E/0x2F configuration port or the 0x4E/0x4F configuration port is generally selected according to the hardware chip select signal to configure the SIO UART, and then the BIOS is compiled and programmed according to the determined configuration port. In the PEI (Pre-EFI Initialization) stage of the process, the SIO UART is configured through the determined configuration port in the early stage, so that the SIO UART can output serial information, but when the configuration port is changed, the BIOS needs to be recompiled and burned, which makes the configuration process complicated. , if the chip select signal of the pre-selected configuration port is abnormal, the serial port log information will be disordered or the serial port information cannot be output normally. In the prior art, the SIO UART is configured in the PEI stage, resulting in the failure to output in the SEC stage before it. Serial port information, unable to locate the problem in the SEC stage.

Therefore, how to provide a solution to the above technical problem is a problem that those skilled in the art need to solve at present.

SUMMARY OF THE INVENTION

The purpose of this application is to provide a SIO UART configuration method, system, device and readable storage medium, without the need to determine the configuration port in advance through the chip select signal, when the configuration port is changed, there is no need to recompile and burn the BIOS, and the configuration process is simple , and at the same time ensure that the serial port information can be output normally in the SEC stage, so as to monitor each running stage of the BIOS.

In order to solve the above technical problems, the present application provides a SIO UART configuration method, including:

determining the information of the output port, the information including the LPC address corresponding to the output port;

In the SEC stage of the BIOS POST process, the LPC address is configured to the corresponding register in the SIO UART through the first preset configuration port and the second preset configuration port respectively, so that the SIO UART outputs serial port information through the output port ;

The LPC address corresponding to the first preset configuration port is 0x2E or 0x2F, and the LPC address corresponding to the second preset configuration port is 0x4E or 0x4F.

Preferably, the process of configuring the LPC address to the corresponding register in the SIO UART through the first preset configuration port and the second preset configuration port respectively is as follows:

Configuring the LPC address to the corresponding register in the SIO UART through the first preset configuration port and the second preset configuration port in turn;

Or the LPC address is sequentially configured to the corresponding register in the SIO UART through the second preset configuration port and the first preset configuration port.

Preferably, the LPC address corresponding to the output port is any one of 0x3F8, 0x3E8, 0x2F8 or 0x2E8.

Preferably, the LPC address is configured to the corresponding register in the SIO UART through the first preset configuration port and the second preset configuration port respectively, so that after the SIO UART outputs serial port information through the output port, the SIO UART configuration methods also include:

The serial port information is sent to the terminal, so that the terminal displays BIOS information corresponding to the serial port information.

Preferably, the process of sending the serial port information to the terminal is as follows:

Send the serial port information to the terminal in a preset format.

In order to solve the above technical problems, the present application also provides a SIO UART configuration system, including:

a determining module, configured to determine the information of the output port, the information including the LPC address corresponding to the output port;

A configuration module, configured to configure the LPC address to the corresponding register in the SIO UART through the first preset configuration port and the second preset configuration port respectively in the SEC stage of the BIOS POST process, so that the SIO UART passes the The output port outputs serial information;

The LPC address corresponding to the first preset configuration port is 0x2E or 0x2F, and the LPC address corresponding to the second preset configuration port is 0x4E or 0x4F.

Preferably, the process of configuring the LPC address to the corresponding register in the SIO UART through the first preset configuration port and the second preset configuration port respectively is as follows:

Configuring the LPC address to the corresponding register in the SIO UART through the first preset configuration port and the second preset configuration port in turn;

Or the LPC address is sequentially configured to the corresponding register in the SIO UART through the second preset configuration port and the first preset configuration port.

Preferably, the LPC address corresponding to the output port is any one of 0x3F8, 0x3E8, 0x2F8 or 0x2E8.

In order to solve the above technical problems, the present application also provides a SIO UART configuration device, including:

memory for storing computer programs;

The processor is configured to implement the steps of the SIO UART configuration method according to any one of the above when executing the computer program.

In order to solve the above technical problems, the present application also provides a readable storage medium, where a computer program is stored on the readable storage medium, and when the computer program is executed by a processor, the SIO UART configuration described in any one of the above is realized. steps of the method.

The present application provides a SIO UART configuration method, including: determining information of an output port, where the information includes an LPC address corresponding to the output port; and in the SEC stage of the BIOS POST process, passing the LPC address through the first preset configuration port and the first preset configuration port respectively. The second preset configuration port is configured to the corresponding register in the SIO UART, so that the SIO UART outputs serial information through the output port; wherein, the LPC address corresponding to the first preset configuration port is 0x2E or 0x2F, and the LPC corresponding to the second preset configuration port The address is 0x4E or 0x4F.

It can be seen that, in practical applications, the solution of the present application is adopted to configure the SIO UART through the first preset configuration port and the second preset configuration port respectively in the SEC stage of the BIOS POST process, which is not affected by hardware and does not need to be selected by chip selection. The signal determines the configuration port in advance. Therefore, when the configuration port is changed, there is no need to recompile and burn the BIOS. The configuration process is simple, and at the same time, the serial port information can be output normally during the SEC stage, so as to monitor each running stage of the BIOS.

The present application also provides a SIO UART configuration system, a device and a readable storage medium, which have the same beneficial effects as the above-mentioned SIO UART configuration method.

Description of drawings

In order to illustrate the technical solutions in the embodiments of the present application more clearly, the following briefly introduces the prior art and the drawings required in the embodiments. Obviously, the drawings in the following description are only some of the drawings in the present application. In the embodiments, for those of ordinary skill in the art, other drawings can also be obtained according to these drawings without any creative effort.

1 is a flow chart of steps of a SIO UART configuration method provided by the application;

FIG. 2 is a schematic structural diagram of a SIO UART configuration system provided by the application.

Detailed ways

The core of the present application is to provide a SIO UART configuration method, system, device and readable storage medium. It is not necessary to determine the configuration port in advance through the chip select signal. When the configuration port is changed, there is no need to recompile and burn the BIOS, and the configuration process is simple. , and at the same time ensure that the serial port information can be output normally in the SEC stage, so as to monitor each running stage of the BIOS.

In order to make the purposes, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments It is a part of the embodiments of the present application, but not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present application.

Please refer to FIG. 1. FIG. 1 is a flowchart of steps of a SIO UART configuration method provided by the application, including:

Step 1: determine the information of the output port, the information includes the LPC address corresponding to the output port;

Specifically, the LPC address of the output port is selected first, and the optional LPC address is any one of 0x3F8, 0x3E8, 0x2F8 or 0x2E8.

Step 2: in the SEC stage of the BIOS POST process, configure the LPC address to the corresponding register in the SIO UART through the first preset configuration port and the second preset configuration port respectively, so that the SIO UART outputs serial port information through the output port;

The LPC address corresponding to the first preset configuration port is 0x2E or 0x2F, and the LPC address corresponding to the second preset configuration port is 0x4E or 0x4F.

Specifically, in the SEC stage of the BIOS POST process (that is, the first stage of the BIOS POST process, and the PEI stage is the second stage of the BIOS POST process), the BIOS can enter the configuration mode according to the instructions in the SIO technical specification, and pass the The first preset configuration port and the second preset configuration port configure the LPC address determined in step 1 to the register corresponding to the SIO UART, and enable it, so that the SIO UART outputs serial port information through the output port. It can be understood that when the hardware chip select signal is low, it needs to select 0x2E or 0x2F to configure the port. When the hardware chip select signal is high, it needs to select 0x4E or 0x4F to configure the port. In this application, the BIOS passes the first The preset configuration port and the second preset configuration port are configured with SIO UART, and the LPC address corresponding to the first preset configuration port is set to 0x2E or 0x2F, and the LPC address corresponding to the second preset configuration port is 0x4E or 0x4F. When the chip select signal When it is low level, the configuration of the SIO UART through the first preset configuration port takes effect. When the chip select signal is at a high level, the configuration of the SIO UART through the second preset configuration port takes effect. Therefore, the application is not affected by the hardware chip select signal. , no matter the chip select signal is high level or low level, it can ensure that the configuration of the SIO UART is valid, so that the serial port information can be output normally.

It is understandable that the LPC address can be fixed for certain functions, such as 0x2E/0x2F,

These two groups of 0x2E/0x2F will only be used as the configuration address of SIO, and will not be used for other purposes.

The present application provides a SIO UART configuration method, including: determining information of an output port, where the information includes an LPC address corresponding to the output port; and in the SEC stage of the BIOS POST process, passing the LPC address through the first preset configuration port and the first preset configuration port respectively. The second preset configuration port is configured to the corresponding register in the SIO UART, so that the SIO UART outputs serial information through the output port; wherein, the LPC address corresponding to the first preset configuration port is 0x2E or 0x2F, and the LPC corresponding to the second preset configuration port The address is 0x4E or 0x4F.

It can be seen that, in practical applications, the solution of the present application is adopted to configure the SIO UART through the first preset configuration port and the second preset configuration port respectively in the SEC stage of the BIOS POST process, which is not affected by hardware and does not need to be selected by chip selection. The signal determines the configuration port in advance. Therefore, when the configuration port is changed, there is no need to recompile and burn the BIOS. The configuration process is simple, and at the same time, the serial port information can be output normally during the SEC stage, so as to monitor each running stage of the BIOS.

On the basis of the above-mentioned embodiment:

As a preferred embodiment, the process of configuring the LPC address to the corresponding register in the SIO UART through the first preset configuration port and the second preset configuration port respectively is as follows:

Configuring the LPC address to the corresponding register in the SIO UART through the first preset configuration port and the second preset configuration port in turn;

Or configure the LPC address through the second preset configuration port and the first preset configuration port to

The corresponding register in the SIO UART.

Specifically, when the BIOS configures the SIO UART through the first preset configuration port and the second preset configuration port, it can be configured first through the 0x2E/0x2F configuration port and then through the 0x4E/0x4F configuration port, or it can be configured first. Configure through the 0x4E/0x4F configuration port and then pass

0x2E/0x2F configure the port for configuration, and this application does not limit the configuration sequence.

As a preferred embodiment, the LPC address corresponding to the output port is any one of 0x3F8, 0x3E8, 0x2F8 or 0x2E8.

As a preferred embodiment, the LPC address is configured to the corresponding register in the SIO UART through the first preset configuration port and the second preset configuration port respectively, so that after the SIO UART outputs serial information through the output port, the SIO UART is configured with Methods also include:

Send the serial port information to the terminal so that the terminal can display the BIOS information corresponding to the serial port information.

As a preferred embodiment, the process of sending serial port information to the terminal is as follows:

Send the serial port information to the terminal in the preset format.

Specifically, after configuring the LPC address determined in step 1 to the register corresponding to the SIO UART through the first preset configuration port and the second preset configuration port, and enabling it, the serial port information can be output normally. The location of the BIOS error can be quickly located through the serial port information. In order to facilitate the engineer to view it at any time, the serial port information can be transmitted to the terminal in a preset format through IPMI and other methods, and the corresponding serial port information can be displayed on the terminal, thereby improving the reliability of this application. and convenience.

Please refer to FIG. 2, which is a schematic structural diagram of a SIO UART configuration system provided by the application, including:

Determining module 1, for determining the information of the output port, the information includes the LPC address corresponding to the output port;

The configuration module 2 is used to configure the LPC address to the corresponding register in the SIO UART through the first preset configuration port and the second preset configuration port respectively in the SEC stage of the BIOS POST process, so that the SIO UART outputs serial port information through the output port ;

The LPC address corresponding to the first preset configuration port is 0x2E or 0x2F, and the LPC address corresponding to the second preset configuration port is 0x4E or 0x4F.

As a preferred embodiment, the process of configuring the LPC address to the corresponding register in the SIO UART through the first preset configuration port and the second preset configuration port respectively is as follows:

Configuring the LPC address to the corresponding register in the SIO UART through the first preset configuration port and the second preset configuration port in turn;

Or configure the LPC address through the second preset configuration port and the first preset configuration port to

The corresponding register in the SIO UART.

As a preferred embodiment, the LPC address corresponding to the output port is any one of 0x3F8, 0x3E8, 0x2F8 or 0x2E8.

As a preferred embodiment, the SIO UART configuration system further includes:

The transmission module is used to send the serial port information to the terminal, so that the terminal can display the BIOS information corresponding to the serial port information.

As a preferred embodiment, the transmission module is specifically used for:

Send the serial port information to the terminal in the preset format.

The SIO UART configuration system provided by the present application has the same beneficial effects as the above-mentioned SIO UART configuration method.

For the introduction of an SIO UART configuration system provided by the present application, please refer to the above-mentioned embodiments, which will not be repeated in the present application.

Correspondingly, the present application also provides a SIO UART configuration device, including:

memory for storing computer programs;

The processor is configured to implement the steps of any one of the above SIO UART configuration methods when executing the computer program.

The SIO UART configuration device provided by the present application has the same beneficial effects as the above-mentioned SIO UART configuration method.

For the introduction of an SIO UART configuration device provided in the present application, please refer to the above-mentioned embodiments, which will not be repeated in the present application.

Correspondingly, the present application also provides a readable storage medium, where a computer program is stored on the readable storage medium, and when the computer program is executed by a processor, the steps of any of the above SIO UART configuration methods are implemented.

A readable storage medium provided by the present application has the same beneficial effects as the above-mentioned SIO UART configuration method.

For the introduction of a readable storage medium provided by the present application, please refer to the above-mentioned embodiments, which will not be repeated in the present application.

The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments, and the same and similar parts between the various embodiments can be referred to each other. As for the device disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is relatively simple, and the relevant part can be referred to the description of the method.

The above description of the disclosed embodiments enables any person skilled in the art to make or use the present application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present application. Therefore, this application is not intended to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims (8)

1. a SIO UART configuration method, is characterized in that, comprises: determining the information of the output port, the information including the LPC address corresponding to the output port; In the SEC stage of the BIOS POST process, the LPC address is configured to the corresponding register in the SIO UART through the first preset configuration port and the second preset configuration port respectively, so that the SIO UART outputs serial port information through the output port ; Wherein, the LPC address corresponding to the first preset configuration port is 0x2E or 0x2F, and the LPC address corresponding to the second preset configuration port is 0x4E or 0x4F; The process of configuring the LPC address to the corresponding register in the SIO UART through the first preset configuration port and the second preset configuration port respectively is as follows: Configuring the LPC address to the corresponding register in the SIO UART through the first preset configuration port and the second preset configuration port in turn; Or the LPC address is sequentially configured to the corresponding register in the SIO UART through the second preset configuration port and the first preset configuration port. 2 . The SIO UART configuration method according to claim 1 , wherein the LPC address corresponding to the output port is any one of 0x3F8, 0x3E8, 0x2F8 or 0x2E8. 3 . 3. The SIO UART configuration method according to claim 1, wherein the LPC address is configured to a corresponding register in the SIO UART through the first preset configuration port and the second preset configuration port respectively, so that After the SIOUART outputs serial port information through the output port, the SIO UART configuration method further includes: The serial port information is sent to the terminal, so that the terminal displays BIOS information corresponding to the serial port information. 4. SIO UART configuration method according to claim 3, is characterized in that, the described process that described serial port information is sent to terminal is specifically: Send the serial port information to the terminal in a preset format. 5. a SIO UART configuration system, is characterized in that, comprises: a determining module, configured to determine the information of the output port, the information including the LPC address corresponding to the output port; A configuration module, configured to configure the LPC address to the corresponding register in the SIO UART through the first preset configuration port and the second preset configuration port respectively in the SEC stage of the BIOS POST process, so that the SIO UART passes the The output port outputs serial information; Wherein, the LPC address corresponding to the first preset configuration port is 0x2E or 0x2F, and the LPC address corresponding to the second preset configuration port is 0x4E or 0x4F; The process of configuring the LPC address to the corresponding register in the SIO UART through the first preset configuration port and the second preset configuration port respectively is as follows: Configuring the LPC address to the corresponding register in the SIO UART through the first preset configuration port and the second preset configuration port in turn; Or the LPC address is sequentially configured to the corresponding register in the SIO UART through the second preset configuration port and the first preset configuration port. 6 . The SIO UART configuration system according to claim 5 , wherein the LPC address corresponding to the output port is any one of 0x3F8, 0x3E8, 0x2F8 or 0x2E8. 7 . 7. A SIO UART configuration device, comprising: memory for storing computer programs; The processor is configured to implement the steps of the SIO UART configuration method according to any one of claims 1-4 when executing the computer program. 8. A readable storage medium, characterized in that, a computer program is stored on the readable storage medium, and when the computer program is executed by a processor, the SIO UART configuration method according to any one of claims 1-4 is realized A step of.

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