CN109493778B

CN109493778B - Pre-charging method of display panel, display panel and display device

Info

Publication number: CN109493778B
Application number: CN201811283161.0A
Authority: CN
Inventors: 黄笑宇
Original assignee: HKC Co Ltd
Current assignee: HKC Co Ltd
Priority date: 2018-10-31
Filing date: 2018-10-31
Publication date: 2020-10-16
Anticipated expiration: 2038-10-31
Also published as: CN109493778A; WO2020087603A1

Abstract

The invention discloses a pre-charging method of a display panel, the display panel and a display device, wherein the display panel comprises a pre-charging circuit, the pre-charging circuit comprises a grid driving module and a first pre-charging circuit, and the first pre-charging circuit comprises a first trigger switch module; the grid driving module outputs a grid starting signal; the Nth row of scanning lines receive the Nth row of gate starting signals and charge the pixels in the Nth row; a first trigger switch module of the first pre-charging circuit controls the conduction of a first pre-charging switch according to the Nth row gate starting signal; the first pre-charging switch synchronously outputs the N row of grid starting signals received by the N row of scanning lines to the (N +1) th row of scanning lines; n is a natural number more than or equal to 1, the scheme does not need the participation of a grid driving module, and the limitation of the prior pre-charging technology is solved, so that the pre-charging technology can be applied to wider use conditions.

Description

Pre-charging method of display panel, display panel and display device

Technical Field

The invention belongs to the technical field of display, and particularly relates to a display panel pre-charging method, a display panel and a display device.

Background

With the development and progress of science and technology, flat panel displays have become mainstream products of displays due to thin bodies, power saving, low radiation and other hot spots, and are widely used. The flat panel Display includes a thin film Transistor-Liquid Crystal Display (TFT-LCD), an Organic Light-Emitting Diode (OLED) Display, and the like. The thin film transistor liquid crystal display refracts light rays of the backlight module to generate pictures by controlling the rotation direction of liquid crystal molecules, and has the advantages of thin body, electricity saving, no radiation and the like. The organic light emitting diode display is made of organic light emitting diodes and has the advantages of self luminescence, short response time, high definition and contrast, flexible display, large-area full color display and the like.

The resolution of the liquid crystal display is higher and higher, but the charging time of each row of pixels is very short, and it is difficult to adjust the charging voltage to a higher level to ensure the display effect.

Disclosure of Invention

The invention aims to provide a pre-charging method of a display panel, the display panel and a display device, which can realize the pre-charging function without the participation of a Gate-Chip on film (G-COF) module and have no limitation.

To achieve the above object, the present invention provides a precharge method of a display panel, the display panel including:

a pre-charge circuit comprising a gate drive module and a first pre-charge circuit, the first pre-charge circuit comprising a first toggle switch module, the first toggle switch module comprising a first pre-charge switch, comprising the steps of:

the grid driving module outputs a grid starting signal;

the Nth row of scanning lines receive the Nth row of gate starting signals and charge the pixels in the Nth row;

a first trigger switch module of the first pre-charging circuit controls the first pre-charging switch to be conducted according to the Nth row gate starting signal;

the first pre-charging switch synchronously outputs the N row of grid starting signals received by the N row of scanning lines to the (N +1) th row of scanning lines;

and N is a natural number greater than or equal to 1.

Optionally, the first trigger switch module includes a first trigger module and a first switch module; the control end of the first trigger module is respectively connected to the Nth row of scanning lines and the (N +1) th row of scanning lines;

the step that the first pre-charge switch synchronously outputs the N row of grid starting signals received by the N row of scanning lines to the (N +1) th row of scanning lines comprises the following steps:

when the nth row of scanning lines receives an nth row of gate starting signals, the first trigger module controls the first switch module to output control signals to the first pre-charging switch;

the first pre-charge switch is conducted under the control of the control signal; the first pre-charging switch synchronously outputs the Nth row of grid starting signals to the (N +1) th row of scanning lines;

the step of synchronously outputting the nth row gate starting signal received by the nth row scanning line to the (N +1) th row scanning line by the first pre-charging switch further comprises the following steps:

when the N +1 th row of scanning lines receives the N +1 th row of gate starting signals, the first trigger module controls the first switch module to output a turn-off signal to the first pre-charging switch;

the first pre-charge switch is turned off under the control of the turn-off signal.

The invention also discloses a display panel, comprising a pre-charging circuit, wherein the pre-charging circuit comprises:

the grid driving module is used for outputting a grid starting signal;

the plurality of scanning lines are respectively connected with the grid driving module;

a first precharge circuit connecting the nth row scan line and the (N +1) th row scan line;

n is a natural number more than or equal to 1;

the first precharge circuit includes:

a first trigger switch module;

the control end of the first pre-charging switch is connected to the output end of the first trigger switch module;

when the Nth row of scanning lines receive the Nth row of gate starting signals, the first trigger switch module controls the first pre-charging switch to be switched on; the first pre-charge switch synchronously outputs the Nth row of gate starting signals to the (N +1) th row of scanning lines.

when the nth row of scanning lines receives an nth row of gate starting signals, the first trigger module controls the first switch module to output control signals to the first pre-charging switch; the first pre-charge switch is conducted under the control of the control signal; the first pre-charging switch synchronously outputs the Nth row of grid starting signals to the (N +1) th row of scanning lines;

when the N +1 th row of scanning lines receives the N +1 th row of gate starting signals, the first trigger module controls the first switch module to output a turn-off signal to the first pre-charging switch; the first pre-charge switch is turned off under the control of the turn-off signal.

Optionally, the first trigger module includes a first trigger;

the first switch module comprises a power supply voltage, a first resistor, a first switch tube and a second switch tube;

the first pre-charging switch comprises a fifth switch tube;

the control end of the first switching tube is conducted in a negative polarity mode, and the control ends of the second switching tube and the fifth switching tube are conducted in a positive polarity mode;

the source end of the fifth switching tube is connected to the Nth row of scanning lines, the drain end of the fifth switching tube is connected to the (N +1) th row of scanning lines, and the gate end of the fifth switching tube is connected to the input pin of the first trigger and is grounded through the first resistor;

a source end of the first switch tube is connected to the power supply voltage, a drain end of the first switch tube is connected to a grid end of the fifth switch tube, and a grid end of the first switch tube is connected to an output pin of the first trigger;

the source end of the second switch tube is connected with the drain end of the first switch tube, the drain end of the second switch tube is grounded, and the grid end of the second switch tube is connected with the output pin of the first trigger;

and when the control pin of the first trigger receives a rising edge signal, the first trigger assigns the logic level of the input pin to the output pin.

Optionally, the first precharge circuit further includes:

the input end of the first diode is connected to the Nth row of scanning lines, and the output end of the first diode is connected to the control pin of the first trigger;

and the second diode is connected with the (N +1) th row of scanning lines, and the output end of the second diode is connected with the output end of the first diode and the control pin of the first trigger.

Optionally, the precharge circuit further includes:

a second precharge circuit provided corresponding to the first precharge circuit, the second precharge circuit connecting the (N +1) th scan line and the (N + 2) th scan line;

the second precharge circuit includes:

the second trigger switch module comprises a second trigger module and a second switch module;

the control end of the second pre-charging switch is connected to the output end of the second switch module;

when the N +1 th row of scanning lines receive the N +1 th row of gate starting signals, the second trigger module controls the second switch module to output high level; the second pre-charge switch is controlled to be turned on by a high level, and synchronously outputs the (N +1) th grid starting signal of the (N +1) th row to the (N + 2) th row scanning line.

Optionally, the second trigger module includes a second trigger;

the second switch module comprises a power supply voltage, a second resistor, a third switch tube and a fourth switch tube;

the second pre-charge switch comprises a sixth switch tube;

the control end of the third switching tube is in negative polarity conduction, and the control ends of the fourth switching tube and the sixth switching tube are in positive polarity conduction;

the source end of the sixth switching tube is connected to the (N +1) th row scanning line, the drain end of the sixth switching tube is connected to the (N + 2) th row scanning line, and the gate end of the sixth switching tube is connected to the input pin of the second trigger and is grounded through the second resistor;

the source end of the third switching tube is connected to the power supply voltage, the drain end of the third switching tube is connected to the grid end of the sixth switching tube, and the grid end of the third switching tube is connected to the output pin of the second trigger;

the source end of the fourth switching tube is connected with the drain end of the third switching tube, the drain end of the fourth switching tube is grounded, and the grid end of the fourth switching tube is connected with the output pin of the second trigger;

and when the control pin of the second trigger receives a rising edge signal, the second trigger assigns the logic level of the input pin to the output pin.

Optionally, the second precharge circuit further includes:

the input end of the third diode is connected to the (N +1) th row of scanning lines, and the output end of the third diode is connected to the control pin of the second trigger;

and the input end of the fourth diode is connected to the (N + 2) th row of scanning lines, and the output end of the fourth diode is connected to the output end of the third diode and the control pin of the second trigger.

The invention also discloses a display device comprising the display panel.

At present, people have higher and higher requirements on a display picture, hope that the picture can be clear and stable, in order to achieve a clear effect, technicians continuously improve the resolution, along with the improvement of the resolution, the scanning time of each row of scanning lines is short, so that the charging time of pixels corresponding to each row of scanning lines is short, the charging voltage is generally low, the brightness is insufficient, and the display effect of a display panel is influenced, in the scheme, in order to improve the charging time, the display of the picture is improved by arranging a pre-charging circuit which is directly connected with the Nth row of scanning lines and the (N +1) th row of scanning lines, so that the Nth row of gate starting signals can be synchronously output to the (N +1) th row of scanning lines by controlling the switch of the pre-charging circuit when the Nth row of scanning lines receive the Nth row of gate starting signals, the pixels in the (N +1) th row can be charged in advance, so that the pixels in the (N +1) th row are charged to reach a higher charging voltage at the next time, and the preset charging voltage can be better reached, so that a brighter and better display effect is obtained; in addition, some grid driving modules do not support the function of outputting two rows of grid starting signals simultaneously, the definition of the function by the grid driving modules of different suppliers is possibly different, the participation of the grid driving modules is not needed in the process, the problem is avoided, even if the grid driving modules which do not output two groups of grid starting signals simultaneously are used, the pixels corresponding to two rows of scanning lines can be charged simultaneously, and the pre-charging technology can be widely applied.

Drawings

The accompanying drawings, which are included to provide a further understanding of the embodiments of the application, are incorporated in and constitute a part of this specification, illustrate embodiments of the application and together with the description serve to explain the principles of the application. It is obvious that the drawings in the following description are only some embodiments of the application, and that for a person skilled in the art, other drawings can be derived from them without inventive effort. In the drawings:

FIG. 1 is a diagram illustrating steps of a pre-charging method according to an embodiment of the present invention;

FIG. 2 is a schematic diagram of a display panel according to an embodiment of the invention;

FIG. 3 is a block diagram of a pre-charge circuit according to an embodiment of the present invention;

FIG. 4 is a schematic diagram of a first pre-charge circuit of the pre-charge circuit according to an embodiment of the present invention;

FIG. 5 is a diagram of a second precharge circuit of the precharge circuit according to an embodiment of the present invention;

FIG. 6 is a schematic diagram of a precharge circuit according to an embodiment of the present invention;

FIG. 7 is a diagram illustrating waveforms corresponding to a precharge circuit according to an embodiment of the present invention;

fig. 8 is a schematic diagram of a display device according to an embodiment of the invention.

Detailed Description

Specific structural and functional details disclosed herein are merely representative and are provided for purposes of describing example embodiments of the present application. This application may, however, be embodied in many alternate forms and should not be construed as limited to only the embodiments set forth herein.

In the description of the present application, it is to be understood that the terms "center," "lateral," "upper," "lower," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," and the like are used in the orientation or positional relationship indicated in the drawings for convenience in describing the present application and for simplicity in description, and are not intended to indicate or imply that the referenced device or element must have a particular orientation, be constructed in a particular orientation, and be operated in a particular manner, and therefore should not be construed as limiting the present application. Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the present application, "a plurality" means two or more unless otherwise specified. Furthermore, the term "comprises" and any variations thereof is intended to cover non-exclusive inclusions.

In the description of the present application, it is to be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; can be mechanically or electrically connected; they may be connected directly or indirectly through intervening media, or they may be interconnected between two elements. The specific meaning of the above terms in the present application can be understood in a specific case by those of ordinary skill in the art.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of example embodiments. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used herein, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.

The invention will be further described with reference to the drawings and preferred embodiments.

An undisclosed technical scheme:

a TFT-LCD (Thin Film Transistor Liquid Crystal Display) is one of the main varieties of the current flat panel Display, and has become an important Display platform in modern IT and video products. In the main driving principle of TFT-LCD, a system main Board connects an R/G/B compression signal, a control signal and a power supply to a connector (connector) on a PCB (Printed Circuit Board) Board 21 through wires, data is processed by a Timing Controller (TCON) IC on the PCB Board, and then is connected to a display area panel through a Source-Chip on Film (S-COF) Chip 22 and a Gate-Chip on Film (G-COF) Chip 23 through the PCB Board, so that the display panel obtains the required power supply and signal, for example, fig. 2 is used to increase charging time, a Pre-charge (Pre-charge) technique is adopted in the existing architecture, that is, a Gate of an N +1 th row is turned on while a Gate of an N th row is turned on for charging in advance, so that a pixel of an N +1 th row can be charged in advance, and then a pixel of an N +1 th row is charged to a target voltage at the next time, thereby achieving a longer charging time. The commonly used technology mainly realizes the function by controlling G-COF through TCON, and has more limitations.

As shown in fig. 1, the embodiment of the present invention discloses a pre-charging method for a display panel 2, the display panel includes a pre-charging circuit 100, the pre-charging circuit 100 includes a gate driving module 101 and a first pre-charging circuit 102, the first pre-charging circuit 102 includes a first trigger switch module 103, the first trigger switch module 103 includes a first pre-charging switch 104, including the steps of:

s11: the gate driving module 101 outputs a gate start signal;

s12: the Nth row of scanning lines receive the Nth row of gate starting signals and charge the pixels in the Nth row;

s13: the first trigger switch module of the first pre-charge circuit 102 controls the first pre-charge switch to be turned on according to the nth row gate start signal;

s14: the first pre-charging switch synchronously outputs the N row of grid starting signals received by the N row of scanning lines to the (N +1) th row of scanning lines;

n is a natural number of 1 or more.

In the scheme, N is a natural number greater than or equal to 1, when the gate driving module 101 outputs a gate start signal, the nth row of scan lines receives the gate start signal, and the first triggering module 105 controls the first switch module 106 to output a control signal to the first precharge switch 104; the first pre-charge switch 104 is turned on under the control of the control signal, and the first pre-charge switch 104 synchronously outputs the gate start signal to the (N +1) th row of scan lines to achieve a better pre-charge effect; the first pre-charging circuit 102 designed in the invention synchronously outputs the gate start signal received by the nth row scanning line to the (N +1) th row scanning line and pre-charges the (N +1) th row pixels, the first pre-charging switch 104 is turned off under the control of the turn-off signal, so as to ensure that the control end of the first pre-charging switch 104 is reset to the initial state, so as to receive the next frame signal and complete the pre-charging work corresponding to the next frame, and ensure the stable pre-charging, thereby achieving better display effect; meanwhile, the influence of parasitic capacitance and the like generated between each scanning line and each data line on the pre-charging switch can be reduced, and the problems that the parasitic current is charged to a pixel in non-scanning time to cause display errors and the like are avoided.

Optionally in this embodiment, the first trigger switch module includes a first trigger module and a first switch module; the control end of the first trigger module is respectively connected with the Nth row of scanning lines and the (N +1) th row of scanning lines;

the step that the first pre-charge switch synchronously outputs the N row of gate starting signals received by the N row of scanning lines to the (N +1) th row of scanning lines comprises the following steps:

when the Nth row of scanning lines receive the Nth row of gate starting signals, the first trigger module controls the first switch module to output control signals to the first pre-charging switch;

the first pre-charging switch is conducted under the control of the control signal; the first pre-charge switch synchronously outputs the Nth row of grid starting signals to the (N +1) th row of scanning lines;

when the (N +1) th row of scanning lines receive the (N +1) th row of gate starting signals, the first trigger module controls the first switch module to output a turn-off signal to the first pre-charging switch;

In this scheme, when the nth row scan line receives a gate start signal, the first trigger module controls the first switch module 106 to output a control signal to the first precharge switch 104, at this time, the first precharge switch 104 is turned on under the control of the control signal, and the first precharge switch 104 synchronously outputs the gate start signal to the (N +1) th row scan line; when the N +1 th row of scan lines receives a gate start signal, the first trigger module controls the first switch module 106 to output a turn-off signal to the first precharge switch 104; the first pre-charging switch 104 is turned off under the control of the turn-off signal, and different modules respectively control and output different control signals, so that the disordered work is avoided, and the whole pre-charging circuit is not influenced.

Another embodiment of the present invention, as shown in fig. 2 to 7, discloses a display panel, which includes a pre-charge circuit, the pre-charge circuit includes:

the Gate driving module 101 is configured to output a Gate enable signal (Gate), and the Gate driving module 101 may be an independent chip or a Gate driving circuit directly formed on an Array substrate.

A plurality of scan lines respectively connected to the gate driving module 101;

a first precharge circuit 102 connecting the nth row scanning line and the (N +1) th row scanning line;

n is a natural number more than or equal to 1;

the first precharge circuit 102 includes:

a first trigger switch module 103;

a first pre-charge switch 104, a control end of which is connected to the output end of the first trigger switch module 103;

when the nth row of scanning lines receives the nth row of Gate start signals (Gate N), the first trigger switch module 103 controls the first precharge switch 104 to be turned on; the first precharge switch 104 synchronously outputs the nth row gate start signal to the (N +1) th row scan line.

In the scheme, in order to improve the charging time, a pre-charging circuit is arranged to improve the display of the picture, the pre-charging circuit is directly connected to the Nth row scanning line and the (N +1) th row scanning line, so that the N-th row gate starting signal can be synchronously output to the (N +1) th row scanning line by controlling the switch of the pre-charging circuit when the N-th row scanning line receives the N-th row gate starting signal, the pixels in the (N +1) th row can be charged in advance, so that the pixels in the (N +1) th row are charged to reach a higher charging voltage at the next time, and the preset charging voltage can be better reached, so that a brighter and better display effect is obtained; in addition, some gate driving modules 101 do not support the function of outputting two rows of gate start signals simultaneously, the gate driving modules 101 of different suppliers may have different definitions for the function, and the gate driving modules 101 do not need to participate in the process, so that the above problem is avoided, and even if the gate driving modules 101 which do not output two groups of gate start signals simultaneously are used, the pixels corresponding to two rows of scanning lines can be charged simultaneously, so that the pre-charging technology can be applied to wider use conditions.

Optionally, in this embodiment, the first trigger switch module 103 includes a first trigger module 105 and a first switch module 106; the control end of the first trigger module 105 is respectively connected to the nth row scanning line and the (N +1) th row scanning line;

when the nth row of scan lines receives the nth row of Gate start signals (Gate N +1), the first trigger module 105 controls the first switch module 106 to output control signals to the first precharge switch 104; the first precharge switch 104 is turned on under the control of the control signal; the first pre-charge switch 104 synchronously outputs the nth row gate start signal to the (N +1) th row scan line;

when the (N +1) th row of scanning lines receives the (N +1) th row of gate start signals, the first trigger module 105 controls the first switch module 106 to output turn-off signals to the first precharge switch 104; the first precharge switch 104 is turned off under the control of the off signal.

In this scheme, when the nth row of scanning lines receives the nth row of gate start signals, the first trigger module 105 controls the first switch module 106 to output control signals to the first precharge switch 104; the first precharge switch 104 is turned on under the control of the control signal, and synchronously outputs the nth row of gate start signals to the (N +1) th row of scanning lines, so as to achieve a better precharge effect; when the N +1 th row of scanning lines receives the nth row of gate start signals, the first trigger module 105 controls the first switch module 106 to output a turn-off signal to the first pre-charge switch 104, and the first pre-charge switch 104 is turned off under the control of the turn-off signal, so as to ensure that the control end of the first pre-charge switch 104 is reset to an initial state, so as to receive a next frame of signals and complete pre-charge work corresponding to a next frame, and ensure that pre-charge is stably performed, thereby achieving a better display effect; meanwhile, the influence of parasitic capacitance and the like generated between each scanning line and each data line on the pre-charging switch can be reduced, and the problems of display errors and the like caused by that parasitic current and other signals are charged to the pixels in non-scanning time are reduced or even avoided.

Optionally, in this embodiment, the first trigger module 105 includes a first trigger D1;

the first flip-flop D1 is a rising edge flip-flop;

the first switch module 106 includes a supply voltage VDD, a first resistor R1, a first switch tube M1, and a second switch tube M2;

the first precharge switch 104 includes a fifth switch tube M5;

the switching tube is generally a Metal oxide semiconductor field effect transistor (MOS), the switching tube whose control end is positive polarity generally refers to a P-MOS tube, the switching tube whose control end is negative polarity generally refers to an N-MOS tube, and certainly, other devices capable of achieving similar functions may be used;

the control end of the first switch tube is conducted in negative polarity, and the control ends of the second switch tube and the fifth switch tube are conducted in positive polarity;

the source end of the fifth switching tube is connected to the Nth row of scanning lines, the drain end of the fifth switching tube is connected to the (N +1) th row of scanning lines, and the gate end of the fifth switching tube is connected to the input pin D of the first trigger and is grounded GND through the first resistor;

the source end of the first switch tube is connected to the power supply voltage, the drain end of the first switch tube is connected to the grid end of the fifth switch tube, and the grid end of the first switch tube is connected to the output pin Q of the first trigger;

the source end of the second switch tube is connected with the drain end of the first switch tube, the drain end is grounded, and the grid end is connected with the output pin Q of the first trigger;

the control pin C of the first trigger is respectively connected with the Nth row of scanning lines and the (N +1) th row of scanning lines, and when the first trigger receives the rising edge signal, the logic level of the D end of the input pin of the first trigger is assigned to the output pin Q.

In the scheme, in the first pre-charge circuit 102, the power supply voltage is at a logic high level, a resistance is grounded to obtain a logic low level, the second switching tube and the fifth switching tube are N-MOS tubes, when the gate start signal is at a logic low level L, M2 and M5 are turned off, and when the gate start signal is at a logic high level H, M2 and M5 are turned on; the first switch tube is a P-MOS tube, when the starting signal is L, M1 is conducted, and when the gate starting signal is H, M1 is turned off; in an initial state, because of the grounding effect of the first resistor, the output voltage at the first resistor is a logic low level, at this time, M5 is turned off, and the D value of the first flip-flop is a logic low level; at this time, the Q value of the first trigger is not output, and M1 and M2 are both closed; when the rising edge of the scanning line of the Nth row arrives: when the control pin C of the first flip-flop receives a rising edge, D1 assigns L to the value of D to Q, at which time M1 turns on, M2 turns off, and at which time the logic level at point A is H. D1 has a D value of H; at this time, M5 is turned on, and Output N is Output N +1, so that the pixels in the N +1 th row can be precharged while scanning the pixels in the N th row, thereby ensuring a higher voltage value and achieving a higher display effect. Meanwhile, the pre-charging switch is kept to be turned off during the non-scanning period, so that the corresponding pre-charging switch can complete stable pre-charging work without the problem that the display panel cannot work normally or even is damaged due to the fact that all the pre-charging switches are in a conducting state; and the condition that the pre-charging switch is not turned off can be avoided, so that the influence of parasitic capacitance and the like generated between each scanning line and the data line on the pre-charging switch and the pixels of the corresponding row can be reduced, and the problems that the parasitic current is charged to the pixels in non-scanning time to cause display errors and the like are avoided.

Optionally in this embodiment, the first precharge circuit 102 further includes:

the input end of the first diode D3 is connected to the Nth row of scanning lines, and the output end of the first diode D3 is connected to the control pin C of the first trigger;

and the input end of the second diode D4 is connected to the (N +1) th row of scanning lines, and the output end of the second diode D4 is connected to the output end of the first diode and the control pin C of the first trigger.

In the scheme, the first diode 107 is arranged to control the first trigger to be turned on, so that the first switch module 106 outputs a high level to control the first pre-charge switch 104 to be turned on, and further, when the nth row of scanning lines is charged, the (N +1) th row is charged at the same time, so that each row can have longer charging time, and a better charging effect is achieved; the second diode 108 turns on the first trigger through the second diode 108 when the gate start signal scans the (N +1) th row of scan lines, so that the first switch module 106 outputs a low level to control the turning off of the first precharge switch 104, thereby preventing the (N +1) th row of scan lines from simultaneously charging the (N) th row of scan lines, and preventing the precharge switches corresponding to all the scan lines from being turned on during the non-scanning period, thereby preventing the scan lines of all rows from being charged and working normally, even being burnt out completely; and through the second diode 108, the pre-charge circuit can autonomously control and pull down the potential of the control end of the pre-charge switch in the previous row, the potential pull-down effect is better, and the pre-charge switch can be ensured to keep a low-level potential in a non-scanning period (for example, for an N +1 th row of scanning lines, the scanning period of the pre-charge switch, namely the scanning time when the scanning period of the pre-charge switch receives a gate start signal in the nth row and the scanning period of the pre-charge switch, namely the non-scanning period of the pre-charge switch in other rows) so as to ensure turn-off, which is favorable for the stability of the circuit, avoids parasitic current or other signal interference generated by parasitic capacitance, and is charged into a corresponding pixel, thereby avoiding the display error.

As another embodiment of the present invention, a display panel is disclosed, the display panel including a precharge circuit, as shown with reference to fig. 2 to 7, the precharge circuit including:

a second precharge circuit 109 provided corresponding to the first precharge circuit 102, the second precharge circuit 109 connecting the (N +1) th scan line and the (N + 2) th scan line;

the second precharge circuit 109 includes:

a second trigger switch module 115 including a second trigger module 111 and a second switch module 112;

a second pre-charge switch 110, a control terminal of which is connected to an output terminal of the second switch module 112;

when the (N +1) th row of scanning lines receives the (N +1) th row of gate start signals, the second trigger module 111 controls the second switch module 112 to output a high level; the second precharge switch 110 is turned on by the high level control, and synchronously outputs the (N +1) th gate start signal of the (N +1) th row to the (N + 2) th row scan line.

In the scheme, when the (N +1) th row of scanning lines receive a gate starting signal, the pre-charging circuit synchronously outputs the gate starting signal to the (N + 2) th row of scanning lines, so that the pixels in the (N + 2) th row can be charged in advance, and the pixels in the (N + 2) th row are charged to a target voltage at the next time, thereby obtaining longer charging time; so, according to this scheme, alright in order to carry out the setting of precharge circuit to whole panel to can reach the purpose that all scanning lines of whole panel can both carry out precharge, and the time of precharging is almost equivalent to original twice, like this, alright reach higher charging voltage in order to guarantee the pixel that each scanning line corresponds, be favorable to reducing the consumption.

In an optional embodiment of the present invention, the second triggering module 111 includes a second trigger;

the second trigger is a rising edge trigger;

the second switch module 112 includes a supply voltage VDD, a second resistor R2, a third switch tube M3, and a fourth switch tube M4;

the second pre-charge switch 110 includes a sixth switch tube M6;

the switching tube is generally a Metal oxide semiconductor field effect transistor (MOS), the switching tube whose control end is positive polarity is generally a P-MOS tube, the switching tube whose control end is negative polarity is generally an N-MOS tube, and of course, other devices capable of realizing similar functions may be used as well

The control end of the third switching tube is conducted in negative polarity, and the fourth switching tube and the sixth switching tube are conducted in positive polarity;

the source terminal of the sixth switching tube is connected to the (N +1) th row scan line, the drain terminal is connected to the (N + 2) th row scan line, and the gate terminal is connected to the input pin D of the second trigger and grounded through the second resistor;

the source end of the third switching tube is connected to the power supply voltage, the drain end of the third switching tube is connected to the grid end of the sixth switching tube, and the grid end of the third switching tube is connected to the output pin Q of the second trigger;

the source end of the fourth switching tube is connected with the drain end of the third switching tube, the drain end of the fourth switching tube is grounded, and the grid end of the fourth switching tube is connected with an output pin Q of the second trigger;

the control pin C of the second trigger is respectively connected with the N +1 th row scanning line and the N +2 th row scanning line, and when the control pin of the second trigger receives the rising edge signal, the logic level of the input pin D of the second trigger is assigned to the output pin Q.

In the scheme, the power supply voltage in the second pre-charge circuit 109 is at a logic high level H, the second pre-charge circuit 109 obtains a logic low level L by grounding a resistor, the fourth switching tube and the sixth switching tube are N-MOS tubes, when the gate start signal is H, M4 and M6 are turned on, and when the gate start signal is L, M4 and M6 are turned off; the third switching tube is a P-MOS tube, when the grid starting signal is L, M3 is turned on, and when the grid starting signal is H, M3 is turned off; in the initial state, because of the grounding effect of the third resistor, the output voltage at the second resistor is at a logic low level, at this time, M6 is turned off, and the D value of the second flip-flop D2 is at a logic low level; at this time, the Q value of the first trigger is not output, and M3 and M4 are both closed; when the rising edge of the scanning line of the (N +1) th row arrives: when the control pin C of the second flip-flop receives the rising edge, D2 assigns L of the D value to Q, at which time M3 is turned on, M4 is turned off, and at which time the logic level at point B is H. D2 has a D value of H; at this time, M6 is turned on, and Output N +1 is equal to Output N +2, so that the pixels in the N +2 th row can be precharged while the pixels in the N +1 th row are scanned, thereby ensuring a higher voltage value and achieving a higher display effect. Meanwhile, the pre-charging switch is kept to be turned off in the non-scanning period, so that the pre-charging switch is prevented from being turned off, the influence of parasitic capacitance and the like generated between each scanning line and each data line on the pre-charging switch can be reduced, and the problems that the parasitic current is charged to a pixel in the non-scanning time to cause display errors and the like are avoided.

This embodiment is optional, and the second precharge circuit further includes:

the input end of the third diode D5 is connected to the (N +1) th row of scanning lines, and the output end of the third diode D5 is connected to the control pin C of the first trigger;

and the input end of the fourth diode D6 is connected to the (N + 2) th row of scanning lines, and the output end of the fourth diode D6 is connected to the output end of the first diode and the control pin C of the first trigger.

In the scheme, the third diode 113 is arranged to control the first trigger to be turned on, so that the second switch module 112 outputs a high level to control the second precharge switch 110 to be turned on, and further, when the N +1 th row of scanning lines is charged, the N +2 th row is charged at the same time, so that each row can have longer charging time, and a better charging effect is achieved; the fourth diode 114 turns on the second trigger through the fourth diode 114 when the gate start signal scans the (N + 2) th row of scan lines, so that the second switch module 112 outputs a low level to control the turning off of the second precharge switch 110, thereby preventing the (N + 2) th row of scan lines from simultaneously charging the (N +1) th row of scan lines, and preventing the precharge switches corresponding to all the scan lines from being turned on during the non-scanning period, thereby preventing the scan lines of all rows from being charged and being incapable of working normally, even being burnt out completely; and through the fourth diode, the pre-charge circuit can autonomously control and pull down the potential of the control end of the pre-charge switch in the previous row, the potential pull-down effect is better, and the pre-charge switch can be ensured to keep a low-level potential in a non-scanning period (for example, for an N +2 th row of scanning lines, the scanning period of the pre-charge switch, namely the scanning time of receiving a gate starting signal in the N +1 th row and the N +2 th row, and the scanning period of other rows, namely the non-scanning period of the pre-charge switch), so that the turn-off is ensured.

As another embodiment of the present invention, a display panel is disclosed, the display panel including a precharge circuit, as shown with reference to fig. 2 and 7, the precharge circuit including:

a gate driving module 101 configured to output a gate start signal;

the second pre-charging circuit is connected with the scanning line of the (N +1) th row and the scanning line of the (N + 2) th row;

the first pre-charging circuit comprises a supply voltage VDD, a first resistor R1, a first trigger D1, a first diode D3, a second diode D4, a first switch tube M1, a second switch tube M2 and a fifth switch tube M5;

the second pre-charging circuit comprises a second resistor R2, a second trigger D2, a third diode D5, a fourth diode D6, a third switching tube M3, a fourth switching tube M4 and a sixth switching tube M6;

the source end of the fifth switching tube is connected to the Nth row of scanning lines, the drain end of the fifth switching tube is connected to the (N +1) th row of scanning lines, and the grid end of the fifth switching tube is connected to the input pin D of the first trigger and is grounded through the first resistor;

a control pin C of the first trigger is respectively connected with the Nth scanning line and the (N +1) th scanning line, and when the control pin C receives a signal rising edge, the first trigger assigns the logic level of an input pin D of the first trigger to an output pin Q;

the input end of the first diode 107 is connected to the Nth row of scanning lines, and the output end of the first diode is connected to the control pin C of the first trigger;

the input end of the second diode 108 is connected to the (N +1) th row of scanning lines, and the output end of the second diode 108 is connected to the output end of the first diode 107 and the control pin C of the first trigger;

the source terminal of the sixth switching tube is connected to the (N +1) th row scanning line, the drain terminal of the sixth switching tube is connected to the (N + 2) th row scanning line, and the gate terminal of the sixth switching tube is connected to the input pin of the second trigger and is grounded through the second resistor;

the source end of the third switching tube is connected with the power supply voltage, the drain end of the third switching tube is connected with the grid end of the sixth switching tube, and the grid end of the third switching tube is connected with the output pin of the second trigger;

the control pin of the second trigger is respectively connected with the (N +1) th row scanning line and the (N + 2) th row scanning line, the second trigger is a rising edge D trigger, and the function of the second trigger is to assign the logic level of the D end to Q when the C end of the control end receives the rising edge of a signal.

The input end of the third diode 113 is connected to the (N +1) th row of scanning lines, and the output end of the third diode 113 is connected to the control pin of the second trigger;

the input end of the fourth diode 114 is connected to the (N + 2) th row of scan lines, and the output end is connected to the output end of the third diode 113 and the control pin of the second trigger;

the first switching tube and the third switching tube are P-MOS tubes, and the second switching tube, the fourth switching tube, the fifth switching tube and the sixth switching tube are N-MOS tubes;

in the scheme, VDD is a logic high level, namely H, and GND is a logic low level, namely L; r1 and R2 are ground resistors. M2, M4, M5 and M6 are P-MOS, when a gate start signal is H, M2, M4, M5 and M6 are turned on, and when the gate start signal is L, M2, M4, M5 and M6 are turned off; m1 and M3 are N-MOS, when the gate start signal is L, M1 and M3 are turned on, and when the gate start signal is H, M1 and M3 are turned off; d1 and D2 are rising edge D flip-flops, and function to assign the logic level of the D terminal to Q when the C terminal of the control terminal receives the rising edge of the signal; d3, D4, D5 and D6 are diodes having unidirectional conductivity; the Gate N, the Gate N +1 and the Gate N +2 are G-COF actual outputs; output N, Output N +1, and Output N +2 are the actual turn-on signals input to the panel. In practical application, the initial state is as follows: because of the grounding resistance of R1 and R2, the A, B output is L, at the moment, M5 and M6 are turned off, the D value of D1 is L, and the D value of D2 is L; at this time, no Q values of D1 and D2 are output, and M1, M2, M3 and M4 are all closed; when the rising edge of Gate N arrives: when C of D1 receives a rising edge, D1 assigns L to Q the value of D, at which time M1 is turned on and M2 is turned off, at which time the logic level at point A is H. D1 has a D value of H. At this time, M5 is turned on, Output N ═ Output N + 1. When the rising edge of Gate N +1 arrives: when C of D1 and D2 both receive rising edges, D1 assigns H of D value to Q, D2 assigns L of D value to Q, M1 and M4 are closed, M2 and M3 are opened, the logic level at A point is L, and the logic level at B point is H. D is L for D1 and H for D2. At this time, M5 is turned off, M6 is turned on, and Output N +1 is Output N + 2. The same analysis can be obtained: when the rising edge of Gate N +2 arrives, B is L and M6 is off. Therefore, the N +1 th pixel can be precharged while the N-th row of pixels is scanned, a higher voltage value is ensured, and a higher display effect is achieved. Meanwhile, the pre-charging switch is kept to be turned off in the non-scanning period, so that the pre-charging switch is prevented from being turned off, the influence of parasitic capacitance and the like generated between each scanning line and each data line on the pre-charging switch can be reduced, and the problems that the parasitic current is charged to a pixel in the non-scanning time to cause display errors and the like are avoided.

As another embodiment of the present invention, referring to fig. 8, a display device 1 is disclosed, comprising the display panel 2 as described in any of the above.

The technical scheme of the invention can be widely applied to flat panel displays such as Thin film transistor-Liquid Crystal displays (TFT-LCDs) and Organic Light-Emitting diodes (OLED) displays.

The foregoing is a more detailed description of the invention in connection with specific preferred embodiments and it is not intended that the invention be limited to these specific details. For those skilled in the art to which the invention pertains, several simple deductions or substitutions can be made without departing from the spirit of the invention, and all shall be considered as belonging to the protection scope of the invention.

Claims

1. A pre-charging method of a display panel, the display panel comprising a pre-charging circuit, the pre-charging circuit comprising a gate driving module and a first pre-charging circuit, the first pre-charging circuit comprising a first trigger switch module and a first pre-charging switch, the method comprising the steps of:

the grid driving module outputs a grid starting signal;

n is a natural number more than or equal to 1;

the first trigger switch module comprises a first trigger module and a first switch module; the control end of the first trigger module is respectively connected to the Nth row of scanning lines and the (N +1) th row of scanning lines;

the first pre-charge switch is turned off under the control of the turn-off signal;

the first trigger module comprises a first trigger;

the first pre-charging switch comprises a fifth switch tube;

2. A display panel comprising a precharge circuit, the precharge circuit comprising:

the grid driving module is used for outputting a grid starting signal;

n is a natural number more than or equal to 1;

the first precharge circuit includes:

a first trigger switch module;

when the Nth row of scanning lines receive the Nth row of gate starting signals, the first trigger switch module controls the first pre-charging switch to be switched on; the first pre-charging switch synchronously outputs the Nth row of gate starting signals to the (N +1) th row of scanning lines;

when the N +1 th row of scanning lines receives the N +1 th row of gate starting signals, the first trigger module controls the first switch module to output a turn-off signal to the first pre-charging switch; the first pre-charge switch is turned off under the control of the turn-off signal;

the first trigger module comprises a first trigger;

the first pre-charging switch comprises a fifth switch tube;

3. The display panel according to claim 2, wherein the first precharge circuit further comprises:

4. The display panel according to claim 2, wherein the precharge circuit further comprises:

the second precharge circuit includes:

5. The display panel according to claim 4, wherein the second trigger module comprises a second trigger;

the second pre-charge switch comprises a sixth switch tube;

6. The display panel according to claim 5, wherein the second precharge circuit further comprises:

7. A display device comprising the display panel according to any one of claims 2 to 6.