CN109326575B - Manufacturing method of low-cost rewiring bump packaging structure - Google Patents
Manufacturing method of low-cost rewiring bump packaging structure Download PDFInfo
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- CN109326575B CN109326575B CN201811124910.5A CN201811124910A CN109326575B CN 109326575 B CN109326575 B CN 109326575B CN 201811124910 A CN201811124910 A CN 201811124910A CN 109326575 B CN109326575 B CN 109326575B
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- 238000004806 packaging method and process Methods 0.000 title claims abstract description 14
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 12
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 81
- 238000000034 method Methods 0.000 claims abstract description 63
- 238000009713 electroplating Methods 0.000 claims abstract description 27
- 238000003384 imaging method Methods 0.000 claims abstract description 5
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 16
- 229910052802 copper Inorganic materials 0.000 claims description 16
- 239000010949 copper Substances 0.000 claims description 16
- 229910000679 solder Inorganic materials 0.000 claims description 8
- QCEUXSAXTBNJGO-UHFFFAOYSA-N [Ag].[Sn] Chemical compound [Ag].[Sn] QCEUXSAXTBNJGO-UHFFFAOYSA-N 0.000 claims description 7
- PQIJHIWFHSVPMH-UHFFFAOYSA-N [Cu].[Ag].[Sn] Chemical compound [Cu].[Ag].[Sn] PQIJHIWFHSVPMH-UHFFFAOYSA-N 0.000 claims description 7
- 229910000969 tin-silver-copper Inorganic materials 0.000 claims description 7
- 239000002184 metal Substances 0.000 claims 4
- 229910052751 metal Inorganic materials 0.000 claims 4
- 239000000463 material Substances 0.000 abstract description 10
- 238000001259 photo etching Methods 0.000 abstract description 3
- 238000005530 etching Methods 0.000 description 6
- 238000007747 plating Methods 0.000 description 6
- 230000008021 deposition Effects 0.000 description 4
- 238000004026 adhesive bonding Methods 0.000 description 3
- 239000004065 semiconductor Substances 0.000 description 3
- 239000000758 substrate Substances 0.000 description 3
- 230000001680 brushing effect Effects 0.000 description 2
- 238000004140 cleaning Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000012536 packaging technology Methods 0.000 description 2
- 238000001039 wet etching Methods 0.000 description 2
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- 229910052804 chromium Inorganic materials 0.000 description 1
- 239000011651 chromium Substances 0.000 description 1
- ZTXONRUJVYXVTJ-UHFFFAOYSA-N chromium copper Chemical compound [Cr][Cu][Cr] ZTXONRUJVYXVTJ-UHFFFAOYSA-N 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- IUYOGGFTLHZHEG-UHFFFAOYSA-N copper titanium Chemical group [Ti].[Cu] IUYOGGFTLHZHEG-UHFFFAOYSA-N 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 230000017525 heat dissipation Effects 0.000 description 1
- 238000005459 micromachining Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000004904 shortening Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 1
- 229910010271 silicon carbide Inorganic materials 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
- 230000001360 synchronised effect Effects 0.000 description 1
- 239000010936 titanium Substances 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
Images
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
- H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
The invention discloses a manufacturing method of a low-cost rewiring bump packaging structure, which comprises the following steps: forming a PVD seed layer on the wafer; forming an RDL layer photoresist on the surface of the PVD seed layer; carrying out graphical exposure on the formed photoresist of the RDL layer to form an RDL exposure area; forming Bump layer photoresist on the exposed RDL layer photoresist; carrying out imaging exposure on the Bump layer photoresist to form a Bump exposure area; developing to form Bump and RDL electroplating windows; electroplating to form RDL and Bump structures; and removing the photoresist and the outer PVD seed layer. The method combines two photoetching processes, can complete two processes of rewiring and salient points through one electroplating process, reduces the process steps, shortens the process time, can save the equipment and material cost, and improves the productivity.
Description
Technical Field
The invention relates to the technical field of semiconductor or MEMS (micro electro mechanical system) packaging, in particular to a manufacturing method of a low-cost rewiring bump packaging structure.
Background
With the development of semiconductor technology, especially semiconductor packaging technology, Bump-based (Bump) BGA packaging technology has smaller volume, better heat dissipation performance and electrical performance than conventional pin-based mounting and mounting. In addition, the packaging of the sensor and the radio frequency device adopts a bump process, so that the process adaptability, the thermal performance and the electrical performance are better.
The conventional Bumping process usually includes a re-layout wiring process and a Bumping process, and this process involves two sets of photolithography processes, namely: firstly, forming a re-layout wiring (RDL) layer by PVD seed layer deposition, gluing, exposure, development, electroplating, degumming, removing the PVD seed layer and coating an insulating layer (such as PI); and then, forming the salient points through PVD seed layer deposition, gluing, exposure, development, electroplating, degumming, PVD seed layer removal and reflow soldering again.
The existing bump process has the defects of long process flow, high process cost and the like, and two sets of photoetching processes need to be completed. Particularly, when the MEMS device package and other sensing devices are packaged, the requirement for cost is high, and the requirement for the accuracy of the electroplating process is not high for the relatively large-sized redistribution Routing (RDL) layer, it is desirable to simplify the bump process.
In order to at least partially overcome the problems of long process flow, high cost and the like of the bump process in the prior art, the invention provides a manufacturing method of a low-cost rewiring bump packaging structure, which combines two photoetching processes and can finish two processes of rewiring and bump through one electroplating process, thereby reducing the process steps, shortening the process time, saving the equipment and material cost and improving the productivity.
Disclosure of Invention
Aiming at the problems of long process flow, high cost and the like of a bump process in the prior art, according to one embodiment of the invention, a manufacturing method of a low-cost rewiring bump packaging structure is provided, which comprises the following steps: forming a PVD seed layer on the wafer; forming an RDL layer photoresist on the surface of the PVD seed layer; carrying out graphical exposure on the formed photoresist of the RDL layer to form an RDL exposure area; forming Bump layer photoresist on the exposed RDL layer photoresist; carrying out imaging exposure on the Bump layer photoresist to form a Bump exposure area; developing to form Bump and RDL electroplating windows; electroplating to form RDL and Bump structures; and removing the photoresist and the outer PVD seed layer.
In one embodiment of the invention, the thickness of the Bump layer photoresist is larger than that of the RDL layer photoresist, and both the Bump layer photoresist and the RDL layer photoresist are positive photoresists.
In one embodiment of the invention, the Bump that is electroplated to form the RDL and Bump structures is a conductive copper pillar.
In one embodiment of the invention, the Bump formed by electroplating to form the RDL and Bump structure is a tin-silver solder ball or a tin-silver-copper solder ball.
In one embodiment of the invention, the method further comprises reflowing the Bump structure.
According to another embodiment of the present invention, there is provided a method for manufacturing a low-cost redistribution bump package structure, including:
forming a PVD seed layer on the wafer;
forming an RDL layer photoresist on the surface of the PVD seed layer;
carrying out graphical exposure on the formed photoresist of the RDL layer to form an RDL exposure area;
developing the photoresist on the RDL layer to form an RDL electroplating window;
forming Bump layer photoresist on the developed RDL layer photoresist;
carrying out imaging exposure on the Bump layer photoresist to form a Bump exposure area;
developing to form a Bump electroplating window;
electroplating to form RDL and Bump structures; and
and removing the photoresist and the outer PVD seed layer.
In another embodiment of the present invention, the Bump layer photoresist is an attached dry photoresist film, and the thickness of the attached dry photoresist film is greater than that of the RDL layer photoresist.
In another embodiment of the present invention, the Bump that is electroplated to form the RDL and Bump structure is a conductive copper pillar.
In another embodiment of the present invention, the Bump formed by electroplating to form the RDL and Bump structure is a tin-silver solder ball or a tin-silver-copper pillar.
In another embodiment of the present invention, the method further comprises reflowing the Bump structure.
The invention provides a manufacturing method of a low-cost rewiring Bump packaging structure. The steps of the existing process are reduced, the process time is shortened, the equipment and material costs can be saved, and the productivity is improved.
Drawings
To further clarify the above and other advantages and features of embodiments of the present invention, a more particular description of embodiments of the invention will be rendered by reference to the appended drawings. It is appreciated that these drawings depict only typical embodiments of the invention and are therefore not to be considered limiting of its scope. In the drawings, the same or corresponding parts will be denoted by the same or similar reference numerals for clarity.
Fig. 1 illustrates a cross-sectional view of a low-cost redistribution bump package 100.
Fig. 2A-2I illustrate cross-sectional views of a process for forming a low-cost redistribution bump package structure 100 according to an embodiment of the invention.
Fig. 3 illustrates a flow diagram 300 for forming a low cost rerouted bump package structure 100 in accordance with one embodiment of the present invention.
Fig. 4A-4J are cross-sectional views illustrating a process of forming a low-cost redistribution bump package structure 100 according to yet another embodiment of the present invention.
Fig. 5 illustrates a flow chart 500 for forming a low cost rerouted bump package structure 100 in accordance with yet another embodiment of the present invention.
Detailed Description
In the following description, the invention is described with reference to various embodiments. One skilled in the relevant art will recognize, however, that the embodiments may be practiced without one or more of the specific details, or with other alternative and/or additional methods, materials, or components. In other instances, well-known structures, materials, or operations are not shown or described in detail to avoid obscuring aspects of embodiments of the invention. Similarly, for purposes of explanation, specific numbers, materials and configurations are set forth in order to provide a thorough understanding of the embodiments of the invention. However, the invention may be practiced without specific details. Further, it should be understood that the embodiments shown in the figures are illustrative representations and are not necessarily drawn to scale.
Reference in the specification to "one embodiment" or "the embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the invention. The appearances of the phrase "in one embodiment" in various places in the specification are not necessarily all referring to the same embodiment.
It should be noted that, in the embodiments of the present invention, the process steps are described in a specific order, however, this is only for convenience of distinguishing the steps, and the order of the steps is not limited, and in different embodiments of the present invention, the order of the steps may be adjusted according to the adjustment of the process.
The invention provides a manufacturing method of a low-cost rewiring Bump packaging structure. The steps of the existing process are reduced, the process time is shortened, the equipment and material costs can be saved, and the productivity is improved.
A low-cost rewiring bump package structure according to one embodiment of the present invention is described in detail below with reference to fig. 1. Fig. 1 illustrates a cross-sectional view of a low-cost redistribution bump package 100. As shown in fig. 1, the low-cost redistribution Bump package 100 further includes a wafer 101, a chip pad 102, a redistribution trace (RDL)103, and a Bump (Bump) 104.
Wafer 101 is a wafer on which devices such as chips or sensors have been fabricated. In one embodiment of the present invention, wafer 101 may be a MEMS device that has completed a three-dimensional micromachining process. The wafer 101 may be a silicon wafer or a wafer of other substrates, such as a glass substrate, a silicon carbide substrate, and the like.
The re-placement of the wiring (RDL)103 is used to reset the die pad 102 to other positions, resulting in better electrical, thermal and mechanical performance of the packaged die. A re-placement wiring (RDL)103 has one end electrically interconnected with the chip pad 102 and the other end electrically interconnected with a Bump (Bump). The redistribution Routing (RDL)103 is typically a copper material.
Bumps (Bump)104 serve as an interface for external power and/or signals from the chip. The Bump (Bump)104 may be a conductive Copper pillar (Copper pillar) or a solder ball.
The process of forming such a low-cost redistribution bump package structure 100 is described in detail below with reference to fig. 2A-2I and fig. 3. FIGS. 2A-2I are schematic cross-sectional views illustrating a process of forming a low-cost redistribution bump package structure 100 according to an embodiment of the invention; fig. 3 illustrates a flow diagram 300 for forming a low cost rerouted bump package structure 100 in accordance with one embodiment of the present invention.
First, in step 301, as shown in fig. 2A, a PVD seed layer 202 is formed on a wafer 201. In one embodiment of the present invention, PVD seed layer 202 is formed by PVD deposition with a material of chromium copper, wherein the chromium layer is about 500 angstroms thick and the copper layer is about 1000 angstroms to 3000 angstroms thick.
Next, in step 302, as shown in fig. 2B, an RDL layer photoresist 203 is formed on the surface of PVD seed layer 202 of wafer 201. The specific steps of forming the RDL layer photoresist 203 further include dropping, brushing, and baking. In one embodiment of the present invention, the RDL layer photoresist 203 is a positive photoresist having a thickness of about 3 microns to about 10 microns.
Then, in step 303, as shown in fig. 2C, the formed RDL layer photoresist 203 is exposed in a patterning manner to form an RDL exposure region 204.
Next, at step 304, Bump layer photoresist 205 is formed on the exposed RDL layer photoresist 203, as shown in fig. 2D. Bump layer photoresist 205 is typically thicker than RDL layer photoresist 203 as required for Bump design. In order to achieve simultaneous development and stripping of Bump layer photoresist 205 and RDL layer photoresist 203, Bump layer photoresist 205 is also positive.
Then, in step 305, as shown in fig. 2E, imagewise exposure of the Bump layer photoresist 205 is performed to form Bump exposure regions 206.
Next, at step 306, as shown in FIG. 2F, development forms Bump and RDL plating window 207. After development, Bump and RDL plating window 207 exposes PVD seed layer 202.
Then, at step 307, as shown in FIG. 2G, the RDL and Bump structures 208 are formed by electroplating. In one embodiment of the present invention, the RDL layer is a Copper layer, the Bump is a Copper Pillar (Copper Pillar), and the specific electroplating process can be performed by one-time simultaneous Copper electroplating. In yet another embodiment of the present invention, the RDL layer is a copper layer and the Bump is a tin-silver or tin-silver-copper solder ball, and the RDL and underlying copper pad of the Bump are formed by electroplating in a copper electroplating bath, followed by electroplating of the subsequent Bump in another tin-silver or tin-silver-copper electroplating bath.
Finally, in step 308, as shown in FIG. 2H, the PVD seed layer 202 of the outer drain and the photoresists 203, 205 are removed. In one embodiment of the present invention, the photoresist 203, 205 is removed by a photoresist stripper, and after cleaning, the PVD seed layer 202 is removed by a wet etching process. In order to protect the bonding force of the RDL layer, the etching process needs to be controlled during etching to prevent excessive lateral etching.
Also optionally included is step 309, where at step 309, Bump is reflowed as shown in FIG. 2I.
Still another process for forming such a low-cost redistribution bump package structure 100 is described in detail below with reference to fig. 4A-4J and fig. 5. FIGS. 4A-4J are cross-sectional views illustrating a process for forming a low-cost redistribution bump package structure 100 according to yet another embodiment of the present invention; fig. 5 illustrates a flow chart 500 for forming a low cost rerouted bump package structure 100 in accordance with yet another embodiment of the present invention.
First, in step 501, as shown in fig. 4A, a PVD seed layer 402 is formed on a wafer 401, similar to step 301. In one embodiment of the present invention, the PVD seed layer 402 is formed by PVD deposition of titanium copper, wherein the titanium layer is about 500 angstroms thick and the copper layer is about 1000 to 3000 angstroms thick.
Next, in step 502, as shown in fig. 4B, an RDL layer photoresist 403 is formed on the surface of the PVD seed layer 402 of the wafer 401. The specific steps of forming the RDL layer photoresist 403 further include dropping, brushing, and baking. In one embodiment of the present invention, the RDL layer photoresist 403 is a positive photoresist and has a thickness of about 3 microns to about 10 microns.
Then, in step 503, as shown in fig. 4C, the formed RDL layer photoresist 403 is exposed in a patterned manner to form an RDL exposure region 404.
Next, at step 504, the RDL layer photoresist 403 is developed to form the RDL plating window 405, as shown in fig. 4D.
Then, in step 505, Bump layer photoresist 406 is formed on the developed RDL layer photoresist 403, as shown in fig. 4E. In one embodiment of the present invention, the Bump layer photoresist 406 is formed by attaching a photoresist dry film.
Next, in step 506, as shown in fig. 4F, imagewise exposure of the Bump layer photoresist 406 is performed to form Bump exposure regions 407.
Then, at step 507, as shown in FIG. 4G, development forms Bump plating windows 408. After development, Bump plating window 408 and RDL plating window 405 are opened and PVD seed layer 402 is exposed.
Next, at step 508, as shown in FIG. 4H, the RDL and Bump structures 409 are formed by electroplating. In one embodiment of the invention, the RDL layer is a Copper layer and the Bump is a Copper Pillar (Copper Pillar). In yet another embodiment of the present invention, the RDL layer is a copper layer and the Bump is a tin-silver or tin-silver-copper pillar.
Finally, in step 509, as shown in FIG. 4I, the photoresists 403, 406 and the PVD seed layer 402 of the outer drain are removed. In one embodiment of the present invention, the photoresist 403, 406 is removed by a photoresist stripper, and after cleaning, the PVD seed layer 402 is removed by a wet etching process. In order to protect the bonding force of the RDL layer, the etching process needs to be controlled during etching to prevent excessive lateral etching.
Also optionally included is step 510, and at step 510, Bump is reflowed as shown in fig. 4J.
According to the manufacturing method of the low-cost rewiring Bump packaging structure, provided by the invention, the processes of Bump layer photoresist gluing and exposure are directly carried out on the exposed rewiring photoresist layer, and then the processes of one-time synchronous development, electroplating, photoresist removing, PVD seed layer removing and the like are carried out to form the RDL and the Bump. The steps of the existing process are reduced, the process time is shortened, the equipment and material costs can be saved, and the productivity is improved.
While various embodiments of the present invention have been described above, it should be understood that they have been presented by way of example only, and not limitation. It will be apparent to persons skilled in the relevant art that various combinations, modifications, and changes can be made thereto without departing from the spirit and scope of the invention. Thus, the breadth and scope of the present invention disclosed herein should not be limited by any of the above-described exemplary embodiments, but should be defined only in accordance with the following claims and their equivalents.
Claims (10)
1. A manufacturing method of a low-cost rewiring bump packaging structure comprises the following steps:
forming a PVD seed layer on the wafer;
forming an RDL layer photoresist on the surface of the PVD seed layer;
carrying out graphical exposure on the formed photoresist of the RDL layer to form an RDL exposure area;
forming Bump layer photoresist on the exposed RDL layer photoresist;
carrying out imaging exposure on the Bump layer photoresist to form a Bump exposure area;
developing, removing the RDL exposure area and the Bump exposure area, and forming Bump and RDL electroplating windows;
electroplating, wherein metal is filled in the RDL exposure area to form an RDL structure, and metal is filled in the Bump exposure area to form a Bump structure; and
and removing the photoresist and the exposed PVD seed layer.
2. The method of claim 1, wherein the Bump layer photoresist is thicker than the RDL layer photoresist, and both the Bump layer photoresist and the RDL layer photoresist are positive.
3. The method of claim 1, wherein the Bump electroplated to form the RDL and Bump structures is a conductive copper pillar.
4. The method of claim 1, wherein the Bump electroplated to form the RDL and Bump structures is a solder ball of tin-silver or a solder ball of tin-silver-copper.
5. The method of claim 4, further comprising reflowing the Bump structure.
6. A manufacturing method of a low-cost rewiring bump packaging structure comprises the following steps:
forming a PVD seed layer on the wafer;
forming an RDL layer photoresist on the surface of the PVD seed layer;
carrying out graphical exposure on the formed photoresist of the RDL layer to form an RDL exposure area;
developing the photoresist of the RDL layer, and removing the RDL exposure area;
forming Bump layer photoresist on the developed RDL layer photoresist;
carrying out imaging exposure on the Bump layer photoresist to form a Bump exposure area;
developing, removing the Bump exposure area to form a Bump electroplating window;
electroplating, wherein metal is filled in the RDL exposure area to form an RDL structure, and metal is filled in the Bump exposure area to form a Bump structure; and
and removing the photoresist and the exposed PVD seed layer.
7. The method of claim 6, wherein the Bump layer photoresist is a dry film photoresist paste having a thickness greater than the thickness of the RDL layer photoresist.
8. The method of claim 6, wherein the Bump electroplated to form the RDL and Bump structures is a conductive copper pillar.
9. The method of claim 6, wherein the Bump electroplated to form the RDL and Bump structures is a solder ball of tin-silver or a pillar of tin-silver-copper.
10. The method of claim 9, further comprising reflowing the Bump structure.
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| CN201811124910.5A CN109326575B (en) | 2018-09-26 | 2018-09-26 | Manufacturing method of low-cost rewiring bump packaging structure |
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| CN201811124910.5A CN109326575B (en) | 2018-09-26 | 2018-09-26 | Manufacturing method of low-cost rewiring bump packaging structure |
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| US7855452B2 (en) * | 2007-01-31 | 2010-12-21 | Sanyo Electric Co., Ltd. | Semiconductor module, method of manufacturing semiconductor module, and mobile device |
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