CN109300900B - Three-dimensional memory and method for forming three-dimensional memory - Google Patents

Abstract

The invention provides a three-dimensional memory, which comprises a memory layer arranged in a channel hole, wherein the memory layer comprises a barrier layer and a composite functional layer which are sequentially arranged along the outward and inward directions of the channel hole, the composite functional layer comprises a charge trapping part and a tunneling part, and the charge trapping part and the tunneling part are sequentially arranged along the outward and inward directions of the channel hole; the composite functional layer is obtained by partially oxidizing a charge trapping layer, wherein an oxidized portion of the charge trapping layer constitutes the tunneling portion, and an unoxidized portion of the charge trapping layer constitutes the charge trapping portion.

Description

Three-dimensional memory and method of forming three-dimensional memory

technical field

The present invention mainly relates to the field of semiconductors, and in particular, to a three-dimensional memory and a method for forming a three-dimensional memory.

Background technique

With the continuous improvement of storage density requirements in the market, the reduction of the critical dimension of two-dimensional memory has reached the limit of mass production technology. In order to further increase the storage capacity and reduce the cost, a three-dimensional structure memory is proposed.

For the charge trapping three-dimensional memory, the memory layer composed of the tunneling layer, the charge trapping layer and the blocking layer is its key structure. Among them, the tunneling layer is the key structure that determines the storage function of the three-dimensional memory, which has an important influence on the erasing and writing speed and the retention characteristics of the three-dimensional memory. The tunneling layer is usually deposited and formed by a process such as chemical vapor deposition (Chemical Vapor Deposition, CVD), atomic layer deposition (Atomic Layer Depostion, ALD). Due to gas source selection and process characteristics, the tunneling layer formed by this method has many defects, and there are many parasitic charges at the interface between the tunneling layer and the charge trapping layer, which reduces the retention characteristics and usage stability of the three-dimensional memory.

SUMMARY OF THE INVENTION

The technical problem to be solved by the present invention is to provide a three-dimensional memory and a method for forming a three-dimensional memory, wherein the three-dimensional memory has good retention characteristics.

In order to solve the above technical problems, an aspect of the present invention provides a three-dimensional memory, comprising a memory layer disposed in a channel hole, the memory layer including a barrier layer and a A composite functional layer, the composite functional layer includes a charge trapping portion and a tunneling portion, and the charge trapping portion and the tunneling portion are sequentially arranged along the direction from the outside to the inside of the channel hole; the composite functional layer is formed by pairing The charge trapping layer is obtained by performing partial oxidation, wherein the oxidized portion of the charge trapping layer constitutes the tunneling portion, and the unoxidized portion of the charge trapping layer constitutes the charge trapping portion.

In an embodiment of the present invention, the tunneling portion includes a band-engineered tunneling sub-portion.

In an embodiment of the present invention, along the thickness direction of the composite functional layer, the band-engineered tunneling sub-section includes a plurality of regions with different doping concentrations.

In an embodiment of the present invention, along a direction from the inside to the outside of the channel hole, the energy band engineering tunneling sub-section includes a first region, a second region and a third region arranged in sequence, the first region The forbidden band width of a region is larger than the forbidden band widths of the second region and the third region, and the forbidden band width of the third region is larger than the forbidden band width of the second region.

In an embodiment of the present invention, along a direction from the inside to the outside of the channel hole, the energy band engineering tunneling subsection includes a first region, a second region, a fourth region and a third region arranged in sequence , the forbidden band width of the first region is larger than the forbidden band width of the second region, the fourth region and the third region, and the forbidden band width of the third region is larger than that of the second region and the third region. The forbidden band width of the fourth region, and the forbidden band width of the second region is greater than the forbidden band width of the fourth region.

In an embodiment of the present invention, the thickness of the composite functional layer is 5-50 nm.

In an embodiment of the present invention, the three-dimensional memory further includes a channel layer located inside the composite functional layer.

Another aspect of the present invention provides a method of forming a three-dimensional memory, comprising the steps of: providing a semiconductor structure having a channel hole; forming a barrier layer within the channel hole; and forming a barrier layer in the barrier layer A composite functional layer is formed on the inner side of the composite functional layer, and the composite functional layer includes a charge trapping part and a tunneling part, and the charge trapping part and the tunneling part are sequentially arranged along the direction from the outside to the inside of the channel hole; wherein, the The step of forming a composite functional layer on the inner side of the blocking layer includes: forming a charge trapping layer on the inner side of the blocking layer; and oxidizing the charge trapping layer to an oxide thickness to form the tunneling portion; wherein the charge The portion of the trapping layer that is not oxidized forms the charge trapping portion.

In an embodiment of the present invention, in the process of forming the charge trapping layer, a plurality of regions with different element doping concentrations are formed in the regions corresponding to the oxide thickness by adjusting the doping concentration.

In an embodiment of the present invention, in the process of forming the charge trapping layer, the tunneling portion having a plurality of different forbidden band widths is generated by adjusting the oxidation temperature and/or the oxidation intensity.

In one embodiment of the present invention, the charge trapping layer is oxidized to an oxide thickness by wet oxidation and/or in situ steam generation techniques.

In an embodiment of the present invention, the thickness of the composite functional layer is 5-50 nm.

In an embodiment of the present invention, the method further includes: forming a channel layer inside the composite functional layer.

Compared with the prior art, the present invention has the following advantages:

In the three-dimensional memory of the present invention, the tunneling part and the charge trapping part of the composite functional layer are continuous, there is no obvious interface, the parasitic charge between the interface between the tunneling part and the charge trapping part is reduced, and the three-dimensional memory is improved. retention characteristics and stability.

Description of drawings

FIG. 1 is a partial cross-sectional schematic diagram of an intermediate structure of a three-dimensional memory.

FIG. 2 is a partial cross-sectional schematic diagram of an intermediate structure of a three-dimensional memory according to some embodiments of the present invention.

3A-3C are schematic cross-sectional views of memory layers with band-engineered tunneling subsections according to some embodiments of the present invention.

FIG. 4 is a flowchart of a method of forming a three-dimensional memory according to some embodiments of the present invention.

5A-5E are schematic cross-sectional views in an exemplary process of forming a three-dimensional memory according to some embodiments of the present invention.

6 is a flowchart of a method for forming a composite functional layer according to some embodiments of the present invention.

7A-7C are schematic cross-sectional views in an exemplary process of forming a composite functional layer according to some embodiments of the present invention.

8A-8B3 are schematic cross-sectional views during an exemplary process of forming a band-engineered tunneling subsection according to some embodiments of the present invention.

Detailed ways

In order to make the above objects, features and advantages of the present invention more clearly understood, the specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

Numerous specific details are set forth in the following description to facilitate a full understanding of the present invention, but the present invention may also be implemented in other ways than those described herein, and thus the present invention is not limited by the specific embodiments disclosed below.

As shown in this application and in the claims, unless the context clearly dictates otherwise, the words "a", "an", "an" and/or "the" are not intended to be specific in the singular and may include the plural. Generally speaking, the terms "comprising" and "comprising" only imply that the clearly identified steps and elements are included, and these steps and elements do not constitute an exclusive list, and the method or apparatus may also include other steps or elements.

When describing the embodiments of the present invention in detail, for the convenience of description, the cross-sectional views showing the device structure will not be partially enlarged according to the general scale, and the schematic diagrams are only examples, which should not limit the protection scope of the present invention. In addition, the three-dimensional spatial dimensions of length, width and depth should be included in the actual production.

For convenience of description, spatially relative terms such as "below", "below", "below", "below", "above", "on", etc. may be used herein to describe an element shown in the figures or the relationship of a feature to other elements or features. It will be understood that these spatially relative terms are intended to encompass other directions of the device in use or operation than those depicted in the figures. For example, if the device in the figures is turned over, elements described as "below" or "beneath" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary words "below" and "below" can encompass both an orientation of above and below. Devices may also have other orientations (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein should be interpreted accordingly. In addition, it will also be understood that when a layer is referred to as being 'between' two layers, it can be the only layer between the two layers, or one or more intervening layers may also be present.

In the context of this application, descriptions of structures where a first feature is "on" a second feature can include embodiments in which the first and second features are formed in direct contact, as well as further features formed on the first and second features. Embodiments between the second features such that the first and second features may not be in direct contact.

FIG. 1 is a partial cross-sectional schematic diagram of an intermediate structure of a three-dimensional memory. Referring to FIG. 1 , the three-dimensional memory 100 may include a substrate 110 and a stacked layer 120 in a core region. The stacked layer 120 may include gate layers 121 and spacer layers 122 alternately stacked in a direction perpendicular to the substrate 110 . The stacked layer 120 has a channel hole 130 perpendicular to the substrate, and a memory layer 140 and a channel layer 150 are sequentially disposed therein along the direction of the channel hole 130 from the outside to the inside. Here, the memory layer 140 may include a charge blocking layer 141 , a charge trapping layer 142 and a tunneling layer 143 .

For the tunneling layer 143 deposited by CVD, ALD and other processes, due to gas source selection and process characteristics, the tunneling layer 143 formed by this method has many defects, and the interface between the tunneling layer 143 and the charge trapping layer 143 There are many parasitic charges between the three-dimensional memory 100 , which reduces the retention characteristics and the use stability of the three-dimensional memory 100 .

Embodiments of the present invention describe three-dimensional memories with good retention properties and methods of forming three-dimensional memories.

The three-dimensional memory may include an array area, and the array area may include a core area and a word line connection area. The core region is a region including memory cells, and the word line connection region is a region including word line connection circuits. The word line connection region is typically a staircase (SS) structure. However, it can be understood that this is not a limitation of the present invention. The word line connection region can completely adopt other structures, such as a flat structure. Viewed from a vertical direction, the array region may have a substrate and stacked layers, and an array of channel structures is formed on the stacked layers of the core region.

FIG. 2 is a partial cross-sectional schematic diagram of an intermediate structure of a three-dimensional memory according to some embodiments of the present invention. Referring to FIG. 2 , the three-dimensional memory 200 may include a substrate 210 and a stacked layer 220 in a core region. The stacked layer 220 may include gate layers 221 and spacer layers 222 alternately stacked in a direction perpendicular to the substrate 210 . The number of layers of the gate layer 222 is related to the number of layers of the three-dimensional memory 200 .

In this embodiment, the substrate 210 is typically a silicon-containing substrate, such as Si, SOI (silicon-on-insulator), SiGe, Si:C, etc., although this is not a limitation. Some doped wells, such as N wells or P wells, may be provided on the substrate 210 as required. The material of the gate layer 221 is, for example, metal (eg, tungsten, aluminum). The material of the spacer layer 222 is, for example, silicon oxide. The material of the spacer layer 222 is not limited to this, and other insulating materials may also be used.

The three-dimensional memory 200 further includes one or more channel holes 230 penetrating the stack layer 220 in a direction perpendicular to the substrate 210 . In an embodiment of the present invention, the channel hole 230 may be a cylindrical hole, although not by way of limitation. A memory layer 240 may be disposed within the channel hole 230 .

The memory layer 240 may include a barrier layer 241 and a composite functional layer 242 disposed from the outside to the inside along the radial direction of the channel hole 230 . The composite functional layer 242 may include a charge trapping portion 242 a and a tunneling portion 242 b that are sequentially arranged from the outside to the inside along the radial direction of the channel hole 230 . There is continuity between the charge trapping portion 242a and the tunneling portion 242b. That is, there is no obvious interface between the charge trapping portion 242a and the tunneling portion 242b

The tunneling portion 242b and the charge trapping portion 242a of the composite functional layer 242 in the three-dimensional memory 200 are continuous, there is no obvious interface, and the parasitic charge between the contact interface between the tunneling portion 242b and the charge trapping portion 242a is reduced, The retention characteristics of the three-dimensional memory 200 are improved.

In some embodiments, the composite functional layer 242 may be obtained by partially oxidizing the charge trapping layer, wherein the oxidized portion of the charge trapping layer constitutes the tunneling portion 242b, and the unoxidized portion of the charge trapping layer constitutes the charge trapping portion 242a. In some embodiments, the tunneling portion 242b may be gradient oxidized. Specifically, along the radial direction of the channel hole 230 from the inside to the outside, the oxidation strength of the tunneling portion 242b gradually decreases. In this embodiment, the tunneling portion 242b is obtained by oxidizing the charge trapping layer, and the tunneling portion 242b has better quality and fewer defects, thereby improving the retention characteristics of the three-dimensional memory 200 .

In some embodiments, the thickness of the composite functional layer 242 may be 5 to 50 nanometers (nm), preferably about 10 nanometers. In some embodiments, an exemplary material for the blocking layer 241 and the tunneling portion 242b is silicon oxide, silicon oxynitride, or a mixture of the two, and an exemplary material for the charge trapping portion 242a is silicon nitride or silicon nitride and oxynitride Multilayer structure of silicon. The blocking layer 241, the charge trapping portion 242a, and the tunneling portion 242b may form, for example, a multi-layered structure having silicon oxynitride-silicon nitride-silicon oxide (SiON/SiN/SiO).

In some embodiments, the tunneling portion 242b may include a band-engineered tunneling sub-portion. Energy band engineering refers to changing the energy band composition of a semiconductor material by engineering means, such as the design and growth of the physical and geometric parameters of the material. In the embodiments of the present invention, the energy band-engineered tunneling sub-portion refers to a structure obtained by changing the energy band composition of the tunneling portion by engineering means. In some embodiments, along the thickness direction of the composite functional layer 242, the band-engineered tunneling sub-section includes a plurality of regions with different doping concentrations. Since different doping concentrations make each region have different forbidden band widths, the erase performance and retention characteristics of the device can be effectively adjusted, and the overall performance of the device can be improved.

3A-3C are schematic cross-sectional views of memory layers with band-engineered tunneling subsections according to some embodiments of the present invention.

Referring to FIG. 3A , along the radial direction from the inside to the outside of the channel hole 230 , the energy band engineering tunneling sub-section 242b1 includes a first region 242b1a, a second region 242b1b and a third region 242b1c which are arranged in sequence. The forbidden band width of the first region 242b1a is larger than that of the second region 242b1b and the third region 242b1c. The forbidden band width of the third region 242b1c is larger than that of the second region 242b1b. In some embodiments, the first region 242b1a includes silicon oxide ( _SiO2 ), the second region 242b1b includes highly doped silicon oxynitride (SiON), and the third region 242b1c includes low doped silicon oxynitride. Wherein, the doped element may be nitrogen (N).

Referring to FIG. 3B , along the radial direction from the inside to the outside of the channel hole 230 , the energy band engineering tunneling sub-section 242b1 includes a first region 242b1a, a second region 242b1b, a fourth region 242b1d and a third region 242b1c which are arranged in sequence . The forbidden band width of the first region 242b1a is larger than that of the second region 242b1b, the fourth region 242b1d, and the third region 242b1c. The forbidden band width of the third region 242b1c is larger than that of the second region 242b1b and the fourth region 242b1d. The forbidden band width of the second region 242b1b is larger than that of the fourth region 242b1d. In some embodiments, the first region 242b1a includes silicon oxide ( _SiO2 ), the second region 242b1b includes highly doped silicon oxynitride (SiON), the third region 242b1c includes low doped silicon oxynitride, and the fourth region 242b1d includes silicon nitride (SiN). Wherein, the doped element may be nitrogen (N).

The tape-engineered tunneling sub-portion 242b1 shown in FIG. 3C is substantially the same as the tape-engineered tunneling sub-portion 242b1 shown in FIG. 3B, except that the widths of the first region 242b1a and the fourth region 242b1d are different. Specifically, the width of the first region 242b1a in FIG. 3C is smaller than that of the first region 242b1a in FIG. 3B ; the width of the fourth region 242b1d in FIG. 3C is larger than that of the fourth region 242b1d in FIG. 3B . It should be noted that, the widths of the second region 242b1b and/or the third region 242b1c in FIG. 3B and FIG. 3C may be the same or different, which is not limited in the present invention.

In the embodiment where the tunneling portion 242b has the band-engineered tunneling sub-portion 242b1, the three-dimensional memory 200 can have different erasing and writing speeds and retention characteristics by adjusting the structure and parameters of the band-engineering tunneling sub-portion 242b1. In the example shown in FIG. 3A , the three-dimensional memory 200 has a slower erasing and writing speed, but has better retention characteristics. In the embodiment shown in FIG. 3B , the three-dimensional memory 200 has an intermediate erasing and writing speed, and an intermediate retention characteristic. In the embodiment shown in FIG. 3C , the three-dimensional memory 200 has a fast erasing and writing speed, but has a poor retention characteristic.

In some embodiments, a channel layer 250 may also be disposed within the memory layer 240 in the channel hole 230 . An exemplary material for the channel layer 250 is polysilicon. It can be understood that other materials can be selected for the channel layer 250 . For example, single crystal silicon, single crystal germanium, SiGe, Si:C, SiGe:C, SiGe:H and other semiconductor materials may be included. For another example, materials such as Group III metal oxides, Group III metal sulfides, Group V metal oxides, Group V metal sulfides, and carbon nanotubes with semiconductor properties may be included.

FIG. 4 is a flowchart of a method of forming a three-dimensional memory according to some embodiments of the present invention. 5A-5E are schematic cross-sectional views in an exemplary process of forming a three-dimensional memory according to some embodiments of the present invention. The method 300 of forming a three-dimensional memory of this embodiment will be described below with reference to FIGS. 4-5E .

At step 302, a semiconductor structure is provided.

This semiconductor structure is at least a part of which will be used in subsequent processes to ultimately form a three-dimensional memory device. The semiconductor structure may include a core region. Viewed from a vertical direction, the core region may have a substrate, alternately stacked dummy gate layers and spacer layers on the substrate, and channel holes penetrating the alternately stacked dummy gate layers and spacer layers in a direction perpendicular to the substrate .

In the cross-sectional view of the semiconductor structure illustrated in FIG. 5A , the semiconductor structure 400 a may include a substrate 410 and a stacked layer 420 on the substrate 410 . The stacked layer 420 may be a stack in which the first material layers 421 and the second material layers 422 are alternately stacked. The first material layer 421 may be a dummy gate layer or a gate layer. . The second material layer 422 is a spacer layer (or insulating layer). The stacked layer 420 is provided with a channel hole 430 penetrating the stacked layer 420 in a direction perpendicular to the substrate.

In the embodiment of the present invention, the material of the substrate 410 is, for example, silicon. The first material layer 421 and the second material layer 422 are, for example, a combination of silicon nitride and silicon oxide. Taking the combination of silicon nitride and silicon oxide as an example, chemical vapor deposition (CVD), atomic layer deposition (ALD) or other suitable deposition methods can be used to sequentially deposit silicon nitride and silicon oxide on the substrate 410 alternately to form Layer 420 is stacked.

The bottom of the channel hole 430 may have an epitaxial structure 490 . The material of the epitaxial structure 490 is silicon, for example.

Although an example composition of an initial semiconductor structure is described herein, it will be appreciated that one or more features may be omitted from, substituted for, or added to this semiconductor structure. For example, various well regions may be formed in the substrate as desired. In addition, the exemplified materials of each layer are only exemplary, for example, the substrate 410 may also be other silicon-containing substrates, such as SOI (silicon-on-insulator), SiGe, Si:C, and the like.

At step 304, a barrier layer is formed within the channel hole.

In the cross-sectional view of the semiconductor structure shown in FIG. 5B , the semiconductor structure 400 b has a barrier layer 441 formed in the channel hole 430 . Exemplary materials for barrier layer 441 are silicon oxide, silicon oxynitride, or high dielectric constant (High K, HK) materials, or mixtures thereof. The high dielectric constant material may include aluminum oxide (Al ₂ O ₃ ), hafnium oxide (HfO ₂ ), and the like. The method of forming the barrier layer 441 may adopt chemical vapor deposition (CVD), atomic layer deposition (ALD) or other suitable deposition methods.

At step 306, a composite functional layer is formed within the barrier layer.

The composite functional layer includes a charge trapping portion and a tunneling portion sequentially arranged in a direction from the outside to the inside of the channel hole. There is continuity between the charge trapping portion and the tunneling portion. After the composite functional layer is formed, the blocking layer, the charge trapping portion and the tunneling portion together constitute a memory layer.

In the cross-sectional view of the semiconductor structure shown in FIG. 5C , the semiconductor structure 400 c forms a composite functional layer 442 within the barrier layer 441 . The composite functional layer 442 may include a charge trapping portion 442 a and a tunneling portion 442 b that are sequentially arranged from the outside to the inside along the radial direction of the channel hole 430 . There is continuity between the charge trapping portion 442a and the tunneling portion 442b.

In some embodiments, the thickness of the composite functional layer 442 may be 5 to 50 nanometers (nm), preferably about 10 nanometers. In some embodiments, an exemplary material for the barrier layer 441 and the tunneling portion 442b is silicon oxide, silicon oxynitride, or a mixture of the two, and an exemplary material for the charge trapping portion 442a is silicon nitride or silicon nitride and oxynitride Multilayer structure of silicon. The blocking layer 441, the charge trapping portion 442a, and the tunneling portion 442b may form, for example, a multi-layered structure having silicon oxynitride-silicon nitride-silicon oxide (SiON/SiN/SiO). The blocking layer 441 , the charge trapping portion 442 a and the tunneling portion 442 b together constitute the memory layer 440 .

6 is a flowchart of a method for forming a composite functional layer according to some embodiments of the present invention. 7A-7C are schematic cross-sectional views in an exemplary process of forming a composite functional layer according to some embodiments of the present invention. The step 306 of forming the composite functional layer in this embodiment will be described below with reference to FIGS. 6-7C .

At step 306a, a charge trapping layer is formed inside the blocking layer.

In this step, a thicker charge trapping layer is formed inside the blocking layer. The thickness of the charge trapping layer may be, for example, the sum of the thicknesses of the charge trapping layer and the tunneling layer in a conventional three-dimensional memory. The thickness of the charge trapping layer may be 5 to 50 nanometers (nm), preferably about 10 nanometers.

In the cross-sectional view of the semiconductor structure shown in FIG. 7A, the semiconductor structure 400c1 forms a charge trapping layer 442' The charge trapping layer 442' may be, for example, a composite layer of silicon nitride (SiN) and silicon oxynitride (SiON). The method of forming the charge trapping layer 442' may employ chemical vapor deposition (CVD), atomic layer deposition (ALD), or other suitable deposition methods.

At step 306b, the charge trapping layer is oxidized to an oxide thickness, forming the tunneling portion.

In this step, the charge trapping layer is oxidized to a thickness of one oxide, the oxidized portion forms the tunneling portion, and the unoxidized portion forms the charge trapping portion.

In Figure 7B, the charge trapping layer 442' in the semiconductor structure 400c2 is oxidized. The method for oxidizing the charge trapping layer 442 ′ can be, for example, wet oxidation, In-Situ Steam Generation (ISSG), or the like. During the oxidation process, oxygen (O ₂ ) and/or hydrogen (H ₂ ) may be introduced to oxidize the charge trapping layer 442 ′.

Since the oxidation reaction is gradually reacted from the outside to the inside (ie, from the inside to the outside along the radial direction of the channel hole 430 ), the tunneling portion 442b is gradedly oxidized. For embodiments in which the charge trapping layer 442' is silicon nitride (SiN), since the oxidation reaction is a gradual reaction from the outside to the inside (ie, from the inside to the outside along the radial direction of the channel hole 430), the charge trapping layer 442' The surface of the charge trapping layer 442' will be oxidized by silicon dioxide (SiO ₂ ), and the inner side of the charge trapping layer 442' will form silicon oxynitride (SiON) due to insufficient oxidation. Large, still silicon nitride (SiN).

In this embodiment, the charge trapping layer is deposited once, and the tunneling portion and the charge trapping portion are obtained by oxidizing the charge trapping layer, which simplifies the film deposition process and avoids the waiting time (queue time, Q-time) for interlayer deposition. The interface states of the tunneling part and the charge trapping part are reduced, the stability degradation of the three-dimensional memory caused by the parasitic charge on the interface is reduced, and the stability of the three-dimensional memory is improved.

After the charge trapping layer 442' in the semiconductor structure 400c2 is oxidized as shown in FIG. 7B, the semiconductor structure 400c3 shown in FIG. 7C can be obtained. The semiconductor structure 400c3 shown in FIG. 7C is also the semiconductor structure 400c shown in FIG. 5C , so the description is not repeated here.

Continuing to refer to FIGS. 4-5E , the method 300 for forming a three-dimensional memory may further include step 307 after step 306 : high temperature annealing.

Referring to FIG. 5D , high temperature annealing may be performed on the semiconductor structure 400c to obtain the semiconductor structure 400d. The high temperature annealing can improve the interface structure between the tunneling portion 442a and the charge trapping portion 442b. In some embodiments, high temperature annealing may be performed in a nitrogen-containing atmosphere to adjust the distribution of nitrogen and oxygen elements in the memory layer 440, thereby adjusting the programming, erasing and writing performance of the three-dimensional memory. The nitrogen-containing atmosphere refers to an atmosphere including one or more of nitrogen (N ₂ ), ammonia (NH ₃ ), nitric oxide (NO), and the like.

In some embodiments, the method 300 of forming a three-dimensional memory may further include step 309 : forming a channel layer inside the composite functional layer.

In the cross-sectional view of the semiconductor structure shown in FIG. 5E , the channel layer 450 is located in the channel hole 430 in the semiconductor structure 400e. The channel layer 440 , the composite functional layer 442 and the barrier layer 441 are sequentially arranged along the radially outward direction of the channel hole 430 . The method of forming the channel layer 450 may adopt chemical vapor deposition (CVD), atomic layer deposition (ALD) or other suitable deposition methods. An exemplary material for the channel layer 450 is polysilicon. It can be understood that other materials can be selected for the channel layer 450 . For example, single crystal silicon, single crystal germanium, SiGe, Si:C, SiGe:C, SiGe:H and other semiconductor materials may be included. For another example, materials such as Group III metal oxides, Group III metal sulfides, Group V metal oxides, Group V metal sulfides, and carbon nanotubes with semiconductor properties may be included.

In some embodiments, in the method 300 of forming a three-dimensional memory, in the process of forming the charge trapping layer, regions with a plurality of different doping concentrations may be formed in the oxide thickness region by adjusting the doping concentration. Specifically, in the process of depositing the charge trapping layer, the feeding time and/or the feeding amount of ammonia (NH ₃ ) and oxygen (O ₂ ) can be adjusted to intercalate nitrogen oxides with different nitrogen concentrations during the deposition process Silicon (SiON) layer.

Referring to FIG. 8A , the charge trapping layer includes three regions with different doping concentrations of a first region 442b1a', a second region 442b1b' and a third region 442b1c'. In some embodiments, the doping concentration of the second region 442b1b' is greater than the doping concentration of the first region 442b1a' and the third region 442b1c', and the doping concentration of the first region 442b1a' is greater than the doping concentration of the third region 442b1c' concentration. In some embodiments, the first region 442b1a' may include high nitrogen (N) silicon oxynitride (SiON), the second region 442b1b' may include silicon nitride (SiN), and the third region 442b1c' may include low nitrogen ( N) of silicon oxynitride (SiON).

In the step of oxidizing the charge trapping layer (for example, step 306b), tunneling parts with multiple different forbidden band widths can be generated by adjusting the oxidation temperature and/or the oxidation intensity, so as to obtain energy band engineered tunnelers with different structures section, as shown in Figures 8B1-8B3.

FIG. 8B1 shows a schematic cross-sectional view of a composite functional layer obtained by moderately oxidizing the charge trapping layer. Referring to FIG. 8B1 , along the inside-outward direction of the channel hole 430 , the band-engineered tunneling sub-portion 442b1 includes a first region 442b1a , a second region 442b1b , and a third region 442b1c arranged in sequence. The forbidden band width of the first region 442b1a is larger than that of the second region 442b1b and the third region 442b1c. The forbidden band width of the third region 442b1c is larger than that of the second region 442b1b. In some embodiments, the first region 442b1a includes silicon oxide ( _SiO2 ), the second region 442b1b includes highly doped silicon oxynitride (SiON), and the third region 442b1c includes low doped silicon oxynitride. Wherein, the doped element may be nitrogen (N).

FIG. 8B2 shows a schematic cross-sectional view of the composite functional layer obtained by strongly oxidizing the charge trapping layer. Referring to FIG. 8B2 , along the inside-outward direction of the channel hole 430 , the band-engineered tunneling sub-portion 442b1 includes a first region 442b1a , a second region 442b1b , a fourth region 442b1d and a third region 442b1c arranged in sequence. The forbidden band width of the first region 442b1a is larger than that of the second region 442b1b, the fourth region 442b1d, and the third region 442b1c. The forbidden band width of the third region 442b1c is larger than that of the second region 442b1b and the fourth region 442b1d. The forbidden band width of the second region 442b1b is larger than that of the fourth region 442b1d. In some embodiments, the first region 442b1a includes silicon oxide ( _SiO2 ), the second region 442b1b includes highly doped silicon oxynitride (SiON), the third region 442b1c includes low doped silicon oxynitride, and the fourth region 442b1d includes silicon nitride (SiN). Wherein, the doped element may be nitrogen (N).

FIG. 8B3 shows a schematic cross-sectional view of the composite functional layer obtained by weakly oxidizing the charge trapping layer. The band-engineered tunneling sub-portion 442b1 shown in FIG. 8B3 is substantially the same as the band-engineered tunneling sub-portion 442b1 shown in FIG. 8B2, except that the widths of the first region 442b1a and the fourth region 442b1d are different. Specifically, the width of the first area 442b1a in FIG. 8B3 is smaller than that of the first area 442b1a in FIG. 8B2 ; the width of the fourth area 442b1d in FIG. 8B3 is larger than that of the fourth area 442b1d in FIG. 8B2 . It should be noted that the widths of the second region 442b1b and/or the third region 442b1c in FIGS. 8B2 and 8B3 may be the same or different, which are not limited in the present invention.

Other details of the three-dimensional memory device, such as word line connection regions, peripheral interconnections, etc., are not the focus of the present invention, and will not be described here.

In the context of the present invention, the three-dimensional storage device may be a 3D flash memory, such as a 3D NAND flash memory.

This application uses specific terms to describe the embodiments of the application. Such as "one embodiment," "an embodiment," and/or "some embodiments" means a certain feature, structure, or characteristic associated with at least one embodiment of the present application. Therefore, it should be emphasized and noted that two or more references to "an embodiment" or "one embodiment" or "an alternative embodiment" in different places in this specification are not necessarily referring to the same embodiment . Furthermore, certain features, structures or characteristics of the one or more embodiments of the present application may be combined as appropriate.

Although the present invention has been described with reference to the present specific embodiments, those of ordinary skill in the art will recognize that the above embodiments are only used to illustrate the present invention, and can be made without departing from the spirit of the present invention Various equivalent changes or substitutions, therefore, as long as the changes and modifications to the above-mentioned embodiments within the spirit and scope of the present invention will fall within the scope of the claims of the present application.

Claims (16)

1. A three-dimensional memory comprising a memory layer disposed within a channel hole, the memory layer comprising a barrier layer and a composite functional layer disposed sequentially along an outward-inward direction from the channel hole, the composite functional layer comprising a charge-trapping moiety and a tunneling moiety, the charge-trapping moiety and the tunneling moiety being disposed sequentially along the outward-inward direction from the channel hole; the composite functional layer is obtained by partially oxidizing the charge trapping layer, wherein the oxidation gradually reacts from inside to outside along the radial direction of the aperture of the channel; the oxidation strength of the tunneling part is gradually reduced along the radial direction of the channel hole from the inside to the outside; the oxidized portion of the charge-trapping layer constitutes the tunneling portion, and the unoxidized portion of the charge-trapping layer constitutes the charge-trapping portion; the tunneling part comprises an energy band engineering tunneling sub-part, and the energy band engineering tunneling sub-part comprises a plurality of regions with different doping concentrations along the thickness direction of the composite functional layer;

the energy band engineering tunneling subsection comprises a first region, a second region and a third region which are sequentially arranged, the forbidden bandwidth of the first region is larger than that of the second region and that of the third region, the forbidden bandwidth of the third region is larger than that of the second region, and the third region comprises silicon oxynitride.

2. The three-dimensional memory according to claim 1, wherein the composite functional layer has a thickness of 5-50 nm.

3. The three-dimensional memory according to claim 1, further comprising a channel layer located inside the composite functional layer.

4. A three-dimensional memory comprising a memory layer disposed within a channel hole, the memory layer comprising a barrier layer and a composite functional layer disposed sequentially along an outward-inward direction from the channel hole, the composite functional layer comprising a charge-trapping moiety and a tunneling moiety, the charge-trapping moiety and the tunneling moiety being disposed sequentially along the outward-inward direction from the channel hole; the composite functional layer is obtained by partially oxidizing the charge trapping layer, wherein the oxidation gradually reacts from inside to outside along the radial direction of the aperture of the channel; the oxidation strength of the tunneling part is gradually reduced along the radial direction of the channel hole from the inside to the outside; the oxidized portion of the charge-trapping layer constitutes the tunneling portion, and the unoxidized portion of the charge-trapping layer constitutes the charge-trapping portion; the tunneling part comprises an energy band engineering tunneling sub-part, and the energy band engineering tunneling sub-part comprises a plurality of regions with different doping concentrations along the thickness direction of the composite functional layer;

the energy band engineering tunneling subsection comprises a first region, a second region, a fourth region and a third region which are sequentially arranged, the forbidden bandwidth of the first region is larger than that of the second region, that of the fourth region and that of the third region, the forbidden bandwidth of the third region is larger than that of the second region and that of the fourth region, the forbidden bandwidth of the second region is larger than that of the fourth region, and the third region comprises silicon oxynitride.

5. The three-dimensional memory according to claim 4, wherein the composite functional layer has a thickness of 5-50 nm.

6. The three-dimensional memory according to claim 4, further comprising a channel layer located inside the composite functional layer.

7. A method of forming a three-dimensional memory, comprising the steps of:

providing a semiconductor structure, wherein the semiconductor structure is provided with a channel hole;

forming a barrier layer in the channel hole; and

forming a composite functional layer on the inner side of the barrier layer, wherein the composite functional layer comprises a charge trapping part and a tunneling part which are sequentially arranged along the outward and inward directions of the channel hole;

wherein the step of forming a composite functional layer on the inner side of the barrier layer comprises:

forming a charge trapping layer on an inner side of the blocking layer; and

oxidizing the charge-trapping layer to an oxidized thickness to form the tunneling portion;

wherein, the oxidation is gradually reacted from the inside to the outside along the aperture direction of the channel; the oxidation strength of the tunneling part is gradually reduced along the radial direction of the channel hole from the inside to the outside; the portion of the charge-trapping layer that is not oxidized forms the charge-trapping portion;

forming a plurality of regions with different element doping concentrations in the region corresponding to the oxidation thickness by adjusting the doping concentration in the process of forming the charge trapping layer;

the trench structure comprises a trench hole, a first region, a second region and a third region, wherein the trench hole comprises a first region, a second region and a third region which are sequentially arranged along the radial direction from inside to outside, the forbidden bandwidth of the first region is larger than that of the second region and that of the third region, the forbidden bandwidth of the third region is larger than that of the second region, and the third region comprises silicon oxynitride.

8. The method of claim 7, wherein the tunneling sections having a plurality of different forbidden band widths are generated by adjusting an oxidation temperature and/or an oxidation intensity during the forming of the charge trapping layer.

9. The method of claim 7, wherein the charge trapping layer is oxidized to an oxidized thickness by wet oxidation and/or in-situ steam generation techniques.

10. The method of claim 7, wherein the composite functional layer has a thickness of 5-50 nm.

11. The method of forming a three-dimensional memory of claim 7, further comprising: and forming a channel layer on the inner side of the composite functional layer.

12. A method of forming a three-dimensional memory, comprising the steps of:

providing a semiconductor structure, wherein the semiconductor structure is provided with a channel hole;

forming a barrier layer in the channel hole; and

forming a composite functional layer on the inner side of the barrier layer, wherein the composite functional layer comprises a charge trapping part and a tunneling part which are sequentially arranged along the outward and inward directions of the channel hole;

wherein the step of forming a composite functional layer on the inner side of the barrier layer comprises:

forming a charge trapping layer on an inner side of the blocking layer; and

oxidizing the charge-trapping layer to an oxidized thickness to form the tunneling portion;

wherein, the oxidation is gradually reacted from the inside to the outside along the aperture direction of the channel; the oxidation strength of the tunneling part is gradually reduced along the radial direction of the channel hole from the inside to the outside; the portion of the charge-trapping layer that is not oxidized forms the charge-trapping portion;

forming a plurality of regions with different element doping concentrations in the region corresponding to the oxidation thickness by adjusting the doping concentration in the process of forming the charge trapping layer;

the trench structure comprises a channel hole, a first region, a second region, a fourth region and a third region, wherein the channel hole comprises the first region, the second region, the fourth region and the third region which are sequentially arranged along the radial direction from inside to outside, the forbidden bandwidth of the first region is larger than that of the second region, that of the fourth region and that of the third region, the forbidden bandwidth of the third region is larger than that of the second region and that of the fourth region, the forbidden bandwidth of the second region is larger than that of the fourth region, and the third region comprises silicon oxynitride.

13. The method of claim 12, wherein the tunneling sections having a plurality of different forbidden band widths are generated by adjusting an oxidation temperature and/or an oxidation intensity during the forming of the charge trapping layer.

14. The method of claim 12, wherein the charge trapping layer is oxidized to an oxidized thickness by wet oxidation and/or in-situ steam generation techniques.

15. The method of claim 12, wherein the composite functional layer has a thickness of 5 nm to 50 nm.

16. The method of forming a three-dimensional memory of claim 12, further comprising: and forming a channel layer on the inner side of the composite functional layer.

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