CN109148273A - The production method of semiconductor structure - Google Patents
The production method of semiconductor structure Download PDFInfo
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- CN109148273A CN109148273A CN201710508177.6A CN201710508177A CN109148273A CN 109148273 A CN109148273 A CN 109148273A CN 201710508177 A CN201710508177 A CN 201710508177A CN 109148273 A CN109148273 A CN 109148273A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 43
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 40
- 238000000034 method Methods 0.000 claims abstract description 34
- 239000000463 material Substances 0.000 claims description 18
- 229910052751 metal Inorganic materials 0.000 claims description 12
- 239000002184 metal Substances 0.000 claims description 12
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 10
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 claims description 5
- 229910052799 carbon Inorganic materials 0.000 claims description 5
- 239000000377 silicon dioxide Substances 0.000 claims description 5
- 238000001039 wet etching Methods 0.000 claims description 5
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 claims description 4
- 229910052731 fluorine Inorganic materials 0.000 claims description 4
- 239000011737 fluorine Substances 0.000 claims description 4
- 229910052739 hydrogen Inorganic materials 0.000 claims description 4
- 239000001257 hydrogen Substances 0.000 claims description 4
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 claims description 3
- 150000004767 nitrides Chemical group 0.000 claims description 3
- 229920000620 organic polymer Polymers 0.000 claims description 3
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 claims description 2
- PXGOKWXKJXAPGV-UHFFFAOYSA-N Fluorine Chemical compound FF PXGOKWXKJXAPGV-UHFFFAOYSA-N 0.000 claims 1
- 229910003978 SiClx Inorganic materials 0.000 claims 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims 1
- 239000007789 gas Substances 0.000 claims 1
- 150000002500 ions Chemical group 0.000 claims 1
- 239000010936 titanium Substances 0.000 claims 1
- 229910052719 titanium Inorganic materials 0.000 claims 1
- 238000005530 etching Methods 0.000 abstract description 14
- 238000000101 transmission high energy electron diffraction Methods 0.000 abstract description 12
- 230000007547 defect Effects 0.000 abstract description 6
- 238000000059 patterning Methods 0.000 abstract description 5
- 238000010586 diagram Methods 0.000 description 9
- 238000005516 engineering process Methods 0.000 description 7
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 230000003628 erosive effect Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical group [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000010276 construction Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- XYIBRDXRRQCHLP-UHFFFAOYSA-N ethyl acetoacetate Chemical compound CCOC(=O)CC(C)=O XYIBRDXRRQCHLP-UHFFFAOYSA-N 0.000 description 1
- 238000003384 imaging method Methods 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 229910010271 silicon carbide Inorganic materials 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 125000006850 spacer group Chemical group 0.000 description 1
- 229910052715 tantalum Inorganic materials 0.000 description 1
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
- H01L21/0332—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their composition, e.g. multilayer masks, materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
- H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
- H01L21/0337—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/31051—Planarisation of the insulating layers
- H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/31058—After-treatment of organic layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Inorganic Chemistry (AREA)
- General Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Drying Of Semiconductors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Present invention discloses a kind of production methods of semiconductor structure, comprising: provides front-end architecture, the front-end architecture includes mask layer and the first medium layer on the mask layer, and the first medium layer includes multiple spaced first medium blocks；Second dielectric layer is formed on the mask layer and the first medium layer, the second dielectric layer, which is located between the adjacent first medium block, forms groove；Third dielectric layer is formed in the groove；Part of the second dielectric layer between the third dielectric layer and first medium layer is removed, the mask layer is exposed；It etches the mask layer and forms opening；And removal first medium layer, remaining second dielectric layer and third dielectric layer.The above process provides a kind of new ASQP (Anti-Self-aligned Quadra Patterning, anti- autoregistration quadruple figure) process, it can be effectively improved the defects of pattern is unstable, etching depth is inconsistent in SADP technique, can be adapted for critical size is in 5nm even smaller size of process node.
Description
Technical field
The present invention relates to technical field of semiconductors, more particularly to a kind of production method of semiconductor structure.
Background technique
With the continuous development of IC industry, the size of semiconductor devices is smaller and smaller, and integrated level is higher and higher.And
In order to integrate more, the smaller transistor of number on chip, need not turning off the new technology of sending constantly to contract
Subtract transistor size.Wherein, a developing direction is self-alignment type double-pattern technology (SADP, Self-Aligned Double
Patterning), also referred to as side wall graph technology (SPT, Spacer Patterning Technology), which can have
Effect realizes doubling for line density, forms the high density parallel lines of line width and the equal very little of spacing.It is to machine alignment precision
It is required that it is lower than other secondary imaging technologies, therefore pursued by people.
But the technology also has certain defect, in SADP technique, needs to the performance (performance) of core (core)
Ask extremely harsh, it is easy to the situation for causing final pattern, etching depth etc. as one wishes not to the utmost, to influence the property of final products
Energy.
Summary of the invention
The purpose of the present invention is to provide a kind of production methods of semiconductor structure, to optimize lacking for SADP technical process
It falls into.
In order to solve the above technical problems, the present invention provides a kind of production method of semiconductor structure, comprising:
Front-end architecture is provided, the front-end architecture includes mask layer and the first medium layer on the mask layer, institute
Stating first medium layer includes multiple spaced first medium blocks；
Second dielectric layer is formed on the mask layer and the first medium layer, the second dielectric layer is located at adjacent institute
It states and forms groove between first medium block；
Third dielectric layer is formed in the groove；
Part of the second dielectric layer between the third dielectric layer and first medium layer is removed, is exposed described
Mask layer；
It etches the mask layer and forms opening；And
Remove the first medium layer, remaining second dielectric layer and the third dielectric layer.
Optionally, for the production method of the semiconductor structure, the material of the first medium layer is nitride.
Optionally, for the production method of the semiconductor structure, the material of the second dielectric layer is oxide.
Optionally, for the production method of the semiconductor structure, the material of the third dielectric layer is organic polymer
Object.
Optionally, it for the production method of the semiconductor structure, is formed using the plasma containing carbon, hydrogen and fluorine
The third dielectric layer.
Optionally, for the production method of the semiconductor structure, forming third dielectric layer in the groove includes:
Third dielectric layer is formed, the third dielectric layer covers the second dielectric layer and is full of the groove；
Flatening process is executed, part third dielectric layer and second dielectric layer are removed, so that the first medium layer, second
Dielectric layer and third dielectric layer upper surface flush.
Optionally, for the production method of the semiconductor structure, the mask layer is metal mask layer.
Optionally, for the production method of the semiconductor structure, the material of the mask layer is titanium nitride or nitridation
Tantalum.
Optionally, for the production method of the semiconductor structure, the front-end architecture further includes metal layer and is located at
Laying on the metal layer, the mask layer are located on the laying.
Optionally, for the production method of the semiconductor structure, the material of the laying is silicon carbide or positive silicon
The silica that acetoacetic ester is formed.
Optionally, for the production method of the semiconductor structure, the cross-sectional width of the first medium block is 10nm-
80nm。
Optionally, for the production method of the semiconductor structure, the second dielectric layer with a thickness of 10nm-
80nm。
Optionally, for the production method of the semiconductor structure, the cross-sectional width of the groove is 10nm-80nm.
Optionally, for the production method of the semiconductor structure, using wet etching remove the first medium layer,
Remaining second dielectric layer and the third dielectric layer.
In the production method of semiconductor structure provided by the invention, comprising: provide front-end architecture, the front-end architecture includes
Mask layer and the first medium layer on the mask layer, the first medium layer include multiple spaced first mediums
Block；Form second dielectric layer on the mask layer and the first medium layer, the second dielectric layer is located at adjacent described the
Groove is formed between one medium block；Third dielectric layer is formed in the groove；The second dielectric layer is removed positioned at described
Part between third dielectric layer and first medium layer exposes the mask layer；It etches the mask layer and forms opening；And
Remove the first medium layer, remaining second dielectric layer and the third dielectric layer.The above process provides a kind of new
ASQP (Anti-Self-aligned Quadra Patterning, anti-autoregistration quadruple figure) process, can be effectively improved
The defects of pattern is unstable in SADP technique, etching depth is inconsistent, can be adapted for critical size is 5nm even smaller szie
Process node in.
Detailed description of the invention
Fig. 1 is a kind of schematic diagram of semiconductor structure made from SADP technique；
Fig. 2 is the flow chart of the production method of semiconductor structure of the present invention；
Fig. 3-Fig. 4 is to provide the schematic diagram of front-end architecture in one embodiment of the invention；
Fig. 5 is the schematic diagram that second dielectric layer is formed in one embodiment of the invention；
Fig. 6 is the schematic diagram that third dielectric layer is formed in one embodiment of the invention；
Fig. 7 is that the schematic diagram after flatening process is executed in one embodiment of the invention；
Fig. 8 is the schematic diagram that the mask layer is exposed in one embodiment of the invention；
Fig. 9 is the schematic diagram that etching mask layer forms opening in one embodiment of the invention；
Figure 10 is after removing first medium layer, remaining second dielectric layer and third dielectric layer in one embodiment of the invention
Schematic diagram.
Specific embodiment
It is described in more detail below in conjunction with production method of the schematic diagram to semiconductor structure of the invention, wherein table
Showing the preferred embodiment of the present invention, it should be appreciated that those skilled in the art can modify invention described herein, and still
Realize advantageous effects of the invention.Therefore, following description should be understood as the widely known of those skilled in the art, and
It is not intended as limitation of the present invention.
The present invention is more specifically described by way of example referring to attached drawing in the following passage.It is wanted according to following explanation and right
Book is sought, advantages and features of the invention will become apparent from.It should be noted that attached drawing is all made of very simplified form and using non-
Accurately ratio, only for the purpose of facilitating and clarifying the purpose of the embodiments of the invention.
Inventor has studied a kind of SADP technique.As shown in Figure 1, including front end knot via the structure obtained after SADP technique
Structure 100, multiple graphic structures 200 on front-end architecture 100.However, as shown in Figure 1, there is ditch between graphic structure 200
Slot 300, but the depth of groove 300 is not consistent, having deeply has shallowly；In addition, the sidewall profile of graphic structure 200 is unstable.Cause
This it is found that SADP technique have the defects that it is certain.
The main reason for inventor's discovery leads to the above problem is SADP when forming final multiple graphic structures 200,
It is the graphic structure 200 of formation by multiple etching (such as mask layer).
Then, inventor provides a kind of production method of new semiconductor structure, and being used to prepare has smaller critical size
Figure, this method be ASQP process, specifically include:
Step S11, provides front-end architecture, and the front-end architecture includes mask layer and first Jie on the mask layer
Matter layer, the first medium layer include multiple spaced first medium blocks；
Step S12 forms second dielectric layer, the second dielectric layer position on the mask layer and the first medium layer
Groove is formed between the adjacent first medium block；
Step S13 forms third dielectric layer in the groove；
Step S14 removes part of the second dielectric layer between the third dielectric layer and first medium layer, cruelly
Expose the mask layer；
Step S15 etches the mask layer and forms opening；And
Step S16 removes the first medium layer, remaining second dielectric layer and the third dielectric layer.
It is described in detail below with reference to production method of Fig. 2-Figure 10 to semiconductor structure of the invention.
For step S11, as shown in figure 3, providing substrate 1, in one embodiment, the substrate 1 includes metal layer, tool
Body, the metal layer e.g. formed on active device is located on the metal layer 1 it is of course also possible to be passive device etc.
Laying 2, the mask layer 3 is located on the laying 2.
For including the case where metal layer, the mask layer 3 is metal mask layer, for example, the material of the mask layer 3 is
Titanium nitride (TiN) or tantalum nitride (TaN).
In one embodiment, the material of the laying 2 is silicon carbide (SiC) or ethyl orthosilicate (TEOS) is formed
Silica.
Referring to FIG. 4, forming core 4 on the mask layer 3, in one embodiment, the core 4 is polysilicon material
Matter, such as multiple cores 4 can be formed by chemical wet etching, a core 4 is illustrated only in Fig. 4.Then in 4 two sides shape of core
At side wall, specifically, multiple side walls are first medium layer 5 herein, each side wall is first medium block namely described
First medium layer 5 includes multiple spaced first medium blocks.
In one embodiment, the cross-sectional width of the first medium block is 10nm-80nm, the first medium layer 5
Material can be nitride, such as silicon nitride etc..
Then, the core is removed, that is, obtains the front-end architecture in the present invention.
For step S12, referring to FIG. 5, forming second dielectric layer on the mask layer 3 and the first medium layer 5
61, the second dielectric layer 61 is located at formation groove 62 between the adjacent first medium block.In one embodiment, described
The material of second dielectric layer 61 is oxide, such as silica, can be formed using chemical vapor deposition process.Implement at one
Example in, the second dielectric layer 61 with a thickness of 10nm-80nm, the width of the groove 62 may be 10nm-80nm.
For step S13, Fig. 6-Fig. 7 is please referred to, forms third dielectric layer 7 in the groove 62；In one embodiment
In, the material of the third dielectric layer 7 is organic polymer, specifically, such as can be using containing carbon, hydrogen and fluorine from
Daughter forms the third dielectric layer 7, i.e., the described third dielectric layer 7 can be the material containing three kinds of carbon, hydrogen and fluorine elements.
It is understood that the third dielectric layer 71 is covered in entire second dielectric layer 61 when being formed, i.e., such as Fig. 6
It is shown, third dielectric layer 71 is formed, the third dielectric layer 71 covers the second dielectric layer 61 and full of the groove 62；It connects
As shown in fig. 7, execute flatening process, part third dielectric layer and second dielectric layer are removed, so that the first medium layer
5, second dielectric layer 6 and 7 upper surface of third dielectric layer flush.After flatening process, part film layer is changed,
In text for the ease of difference, to after flatening process second dielectric layer 6 and third dielectric layer 7 replaced label.
In one embodiment, the flatening process can for example use chemical mechanical grinding (CMP) technique, alternatively,
It can be carried out using being etched back to.
For step S14, it is situated between referring to FIG. 8, removing the second dielectric layer 6 and being located at the third dielectric layer 7 and first
Part between matter layer 5 exposes the mask layer 3；The second dielectric layer 6 is oxide layer, such as silica, therefore can be with
Going the method for silicon carries out this step using existing usually, this is well known to those skilled in the art, herein without
It is described in detail.
As seen from Figure 8, after removing part second dielectric layer 6, remaining first medium layer 5, third dielectric layer 7 and second
The stepped construction of dielectric layer 6 is successively evenly distributed, can be used as the exposure mask of etching mask layer 3；I.e. existing remaining first
The mask layer 3 exposed between dielectric layer 5, third dielectric layer 7 and the stepped construction of second dielectric layer 6 is the portion for needing to be etched
Point, and the mask layer 3 not being exposed does not need then to be etched；That is it only needs once to carve mask layer 3 after
Erosion.
For step S15, referring to FIG. 9, etching the mask layer 3 forms opening 8；Here it can usually be gone using existing
Carry out this step except the method for mask layer, such as metal mask layer, this is well known to those skilled in the art, herein without
It is described in detail.
It is understood that carry out the etching of mask layer 3 for example, by using wet etching, first medium layer 5 during this,
Second dielectric layer 6 and third dielectric layer 7 will receive a degree of erosion, such as show third dielectric layer 7 in Fig. 9 and be removed
The case where, but this can't have an impact the etching of mask layer 3.Since 3 each section of mask layer is in identical etched rings
It under border, and is the etching carried out simultaneously, therefore 8 depth of opening formed is consistent, and pattern is preferable.
For step S16, the first medium layer, remaining second dielectric layer and the third dielectric layer are removed.For example,
This step can be completed using wet etching.As above illustrated the material of each film layer, therefore can be by quarter
The selection of erosion selection ratio, using substantially will not to the etching liquid that mask layer has an impact, thus realize the first medium layer,
When the complete removal of remaining second dielectric layer and the third dielectric layer, it is ensured that the pattern of mask layer is unaffected.
So far, the production method of semiconductor structure of the invention is completed, and as seen from Figure 10, method of the invention is evaded
SADP technique is easy to produce the inconsistent defect of etching depth, and 3 pattern of mask layer after etching is smooth.
In conclusion in the production method of semiconductor structure provided by the invention, comprising: front-end architecture is provided, before described
End structure includes mask layer and the first medium layer on the mask layer, and the first medium layer includes multiple interval settings
First medium block；Second dielectric layer is formed on the mask layer and the first medium layer, the second dielectric layer is located at
Groove is formed between the adjacent first medium block；Third dielectric layer is formed in the groove；Remove the second medium
Part of the layer between the third dielectric layer and first medium layer, exposes the mask layer；Etch the mask layer shape
At opening；And the above-mentioned first medium layer of removal, remaining second dielectric layer and the third dielectric layer.The above process provides
A kind of new ASQP (Anti-Self-aligned Quadra Patterning, anti-autoregistration quadruple figure) process, Neng Gouyou
Effect improves the defects of pattern is unstable, etching depth is inconsistent in SADP technique, can be adapted for critical size be 5nm even more
In the process node of small size.
Obviously, various changes and modifications can be made to the invention without departing from essence of the invention by those skilled in the art
Mind and range.In this way, if these modifications and changes of the present invention belongs to the range of the claims in the present invention and its equivalent technologies
Within, then the present invention is also intended to include these modifications and variations.
Claims (14)
1. a kind of production method of semiconductor structure characterized by comprising
Front-end architecture is provided, the front-end architecture includes mask layer and the first medium layer on the mask layer, and described the
One dielectric layer includes multiple spaced first medium blocks；
Form second dielectric layer on the mask layer and the first medium layer, the second dielectric layer is located at adjacent described the
Groove is formed between one medium block；
Third dielectric layer is formed in the groove；
Part of the second dielectric layer between the third dielectric layer and first medium layer is removed, the exposure mask is exposed
Layer；
It etches the mask layer and forms opening；And
Remove the first medium layer, remaining second dielectric layer and the third dielectric layer.
2. the production method of semiconductor structure as described in claim 1, which is characterized in that the material of the first medium layer is
Nitride.
3. the production method of semiconductor structure as described in claim 1, which is characterized in that the material of the second dielectric layer is
Oxide.
4. the production method of semiconductor structure as described in claim 1, which is characterized in that the material of the third dielectric layer is
Organic polymer.
5. the production method of semiconductor structure as claimed in claim 4, which is characterized in that using containing carbon, hydrogen and fluorine etc.
Gas ions form the third dielectric layer.
6. the production method of semiconductor structure as described in claim 1, which is characterized in that form third in the groove and be situated between
Matter layer includes:
Third dielectric layer is formed, the third dielectric layer covers the second dielectric layer and is full of the groove；
Flatening process is executed, part third dielectric layer and second dielectric layer are removed, so that the first medium layer, second medium
Layer and third dielectric layer upper surface flush.
7. the production method of semiconductor structure as described in claim 1, which is characterized in that the mask layer is metal mask
Layer.
8. the production method of semiconductor structure as claimed in claim 7, which is characterized in that the material of the mask layer is nitridation
Titanium or tantalum nitride.
9. the production method of semiconductor structure as described in claim 1, which is characterized in that the front-end architecture further includes metal
Layer and the laying on the metal layer, the mask layer are located on the laying.
10. the production method of semiconductor structure as claimed in claim 9, which is characterized in that the material of the laying is carbon
The silica that SiClx or ethyl orthosilicate are formed.
11. the production method of semiconductor structure as described in claim 1, which is characterized in that the section of the first medium block
Width is 10nm-80nm.
12. the production method of semiconductor structure as described in claim 1, which is characterized in that the thickness of the second dielectric layer
For 10nm-80nm.
13. the production method of semiconductor structure as described in claim 1, which is characterized in that the cross-sectional width of the groove is
10nm-80nm。
14. the production method of semiconductor structure as described in claim 1, which is characterized in that using described in wet etching removal
First medium layer, remaining second dielectric layer and the third dielectric layer.
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| US11792973B2 (en) | 2020-07-28 | 2023-10-17 | Changxin Memory Technologies, Inc. | Storage device and forming method having a strip-shaped bitline contact structure |
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