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CN109104187B - Full-digital broadband frequency synthesizer - Google Patents

Full-digital broadband frequency synthesizer Download PDF

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CN109104187B
CN109104187B CN201811075900.7A CN201811075900A CN109104187B CN 109104187 B CN109104187 B CN 109104187B CN 201811075900 A CN201811075900 A CN 201811075900A CN 109104187 B CN109104187 B CN 109104187B
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frequency
phase
digital
loop filter
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CN109104187A (en
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王�锋
刘鹏远
柳鹏
韩翠娥
刘昉
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PLA University of Science and Technology
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    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03LAUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00Automatic control of frequency or phase; Synchronisation
    • H03L7/06Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/16Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
    • H03L7/18Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
    • H03L7/1803Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop the counter or frequency divider being connected to a cycle or pulse swallowing circuit

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Abstract

本发明在频率综合器的电路中设置了可编程逻辑控制器,可以根据频率综合器的实际输入信号情况来调整环路滤波器的参数,进而丰富传统的频率综合器的功能和适应范围。其次,本发明还设置了相位/频率判决器来对输入信号进行相位和频率的判决,可以避免算数运算和代码转换,有效降低了电路的复杂度和功耗。

Figure 201811075900

The invention sets the programmable logic controller in the circuit of the frequency synthesizer, and can adjust the parameters of the loop filter according to the actual input signal condition of the frequency synthesizer, thereby enriching the function and adaptability of the traditional frequency synthesizer. Secondly, the present invention also sets a phase/frequency decider to decide the phase and frequency of the input signal, which can avoid arithmetic operation and code conversion, and effectively reduce the complexity and power consumption of the circuit.

Figure 201811075900

Description

一种全数字宽带频率综合器An all-digital broadband frequency synthesizer

技术领域technical field

本发明涉及一种频率综合器,尤其涉及一种全数字的宽带频率综合器。The invention relates to a frequency synthesizer, in particular to an all-digital wideband frequency synthesizer.

背景技术Background technique

带宽是超宽带雷达区别于窄带雷达的标志,超宽带雷达相对于窄带雷达能够提供更多的目标信息,也就能进行更有效的目标识别。随着雷达信号处理技术的进步,能处理的视频信号带宽越来越宽,使得雷达频率综合器原有的工作频率和带宽已经不能满足超宽带有源相控阵雷达的技术要求。Bandwidth is a sign that UWB radar is different from narrowband radar. Compared with narrowband radar, UWB radar can provide more target information, and it can also carry out more effective target recognition. With the advancement of radar signal processing technology, the bandwidth of the video signal that can be processed is getting wider and wider, so that the original operating frequency and bandwidth of the radar frequency synthesizer can no longer meet the technical requirements of ultra-wideband active phased array radar.

频率综合器是现代通信系统、雷达、测试设备中的关键器件,能够提供高精度、高稳定度的频率。从20世纪30年代首次提出频率合成的概念以来,已经形成了3种基本的频率合成方法:(1)直接频率合成;(2)锁相频率合成;(3)直接数字频率合成(DDS)。早期的频率综合器使用直接频率合成方式,它们结构简单,易于实现,但体积大、成本高。Frequency synthesizers are key components in modern communication systems, radars, and test equipment, which can provide high-precision and high-stability frequencies. Since the concept of frequency synthesis was first proposed in the 1930s, three basic frequency synthesis methods have been formed: (1) direct frequency synthesis; (2) phase-locked frequency synthesis; (3) direct digital frequency synthesis (DDS). Early frequency synthesizers use direct frequency synthesis, which is simple in structure and easy to implement, but large in size and high in cost.

专利文献CN201320570307.6中提出了一种频率综合器。本发明的跳频采用DDS激励PLL的方法来实现频率合成的方案,低频频率采用DDS直接产生方式,充分体现软件无线电的灵活性和可移植性,频率合成器拥有很快的锁定时间,而又保证较小的杂散、准确的频率精度、低的噪位噪声、优良频谱纯度和宽的跳频范围,达到了较高的技术指标。然而该发明的设备中,电路结构固定僵化,灵活性不够,可扩展性不够,无法根据不同的实际需要进行调整。A frequency synthesizer is proposed in the patent document CN201320570307.6. The frequency hopping of the present invention adopts the DDS excitation PLL method to realize the frequency synthesis scheme, and the low frequency frequency adopts the DDS direct generation method, which fully reflects the flexibility and portability of the software radio, and the frequency synthesizer has a fast locking time, and Guaranteed small spurious, accurate frequency accuracy, low noise, excellent spectral purity and wide frequency hopping range, reaching high technical indicators. However, in the device of the invention, the circuit structure is fixed and rigid, the flexibility is not enough, and the expandability is not enough, so it cannot be adjusted according to different actual needs.

发明内容SUMMARY OF THE INVENTION

本发明的目的是克服上述现有技术的不足,提供一种结构新颖、构思巧妙的频率综合器,可以通过可编程逻辑控制模块和相位判决模块来根据需要灵活设置频率综合器的各项属性,进而丰富传统的频率综合器的功能和适应范围,大大提升频率综合器的灵活性和跟踪性能。The purpose of the present invention is to overcome the deficiencies of the above-mentioned prior art, and to provide a frequency synthesizer with a novel structure and ingenious conception, which can flexibly set various attributes of the frequency synthesizer as required through a programmable logic control module and a phase judgment module, Further, the functions and adaptability of the traditional frequency synthesizer are enriched, and the flexibility and tracking performance of the frequency synthesizer are greatly improved.

本发明通过以下的方案来实现:The present invention realizes through the following scheme:

一种全数字宽带频率综合器,其具体包括:数字鉴频鉴相器、环路滤波器、数字压控振荡器、数字分频器、环路参数控制器、相位/频率判决器、可编程逻辑控制器;数字鉴频鉴相器的输出与相位/频率判决器相连,相位/频率判决器分别与环路滤波器和可编程逻辑控制器相连,环路滤波器与数字压控振荡器相连,压控振动器的输出与分频器相连,分频器的输出作为数字鉴频鉴相器的一路输入信号;同时所述数字可编程逻辑控制器与环路参数控制器相连,环路参数控制器与环路滤波器相连。An all-digital broadband frequency synthesizer, which specifically includes: a digital frequency and phase detector, a loop filter, a digital voltage-controlled oscillator, a digital frequency divider, a loop parameter controller, a phase/frequency decider, a programmable Logic controller; the output of the digital frequency discriminator is connected with the phase/frequency decider, the phase/frequency decider is respectively connected with the loop filter and the programmable logic controller, and the loop filter is connected with the digital voltage controlled oscillator , the output of the voltage-controlled vibrator is connected with the frequency divider, and the output of the frequency divider is used as an input signal of the digital frequency and phase detector; at the same time, the digital programmable logic controller is connected with the loop parameter controller, and the loop parameter The controller is connected to the loop filter.

进一步,所述数字鉴频鉴相器对输入参考信号和分频器的输出进行频率和相位的比较,然后得到一个代表相位/频率误差的信号给相位/频率判决器;相位/频率判决器根据误差信号进性判决,得到相位和频率的判决结果,并分别发送给环路滤波器和可编程逻辑控制器;可编程逻辑控制器根据相位/频率判决器的判决结果,进行环路滤波器的参数调整,并将调整的结果发送给环路参数控制器,环路参数控制器根据结果对环路滤波器进行控制。Further, the digital frequency and phase detector compares the input reference signal and the output of the frequency divider with frequency and phase, and then obtains a signal representing the phase/frequency error to the phase/frequency decider; the phase/frequency decider is based on The error signal is progressively judged, and the judgment results of phase and frequency are obtained, and sent to the loop filter and the programmable logic controller respectively; the programmable logic controller performs the loop filter according to the judgment results of the phase/frequency decider. The parameters are adjusted, and the adjusted result is sent to the loop parameter controller, and the loop parameter controller controls the loop filter according to the result.

进一步,所述环路滤波器中设置有可调谐电阻,所述环路参数控制器通过调节环路滤波器中的可调谐电阻来调节环路滤波器的性能。Further, a tunable resistor is provided in the loop filter, and the loop parameter controller adjusts the performance of the loop filter by adjusting the tunable resistor in the loop filter.

进一步,所述数字鉴频鉴相器包括时钟预分频模块、多位计数器模块、多位寄存器模块、边沿检测模块,同时时钟预分频模块接收固定晶振时钟输入的时钟信号,然后经过偶数、奇数、半整数级联分频来输出参考时钟信号,然后将参考时钟信号输出给边沿检测模块和多位计数器模块,边沿检测接收反馈时钟信号,然后检测参考时钟信号和反馈时钟信号的边沿,根据二者的边沿情况得到所述相位/频率误差的信号。Further, the digital frequency discriminator and phase discriminator includes a clock prescaler module, a multi-bit counter module, a multi-bit register module, and an edge detection module, and the clock prescaler module receives the clock signal input by the fixed crystal oscillator clock, and then passes through even numbers, Odd and half-integer cascade frequency division to output the reference clock signal, and then output the reference clock signal to the edge detection module and the multi-bit counter module, the edge detection receives the feedback clock signal, and then detects the edge of the reference clock signal and the feedback clock signal, according to The edge cases of the two give the signal of the phase/frequency error.

进一步,相位/频率判决器的电路中具体包括四个或非门和两个D型触发器。Further, the circuit of the phase/frequency decider specifically includes four NOR gates and two D-type flip-flops.

进一步,所述相位/频率判决器包含两个逻辑电路,所述两个逻辑电路包含两个或非门电路,其中或非门的一个输入端接收数字鉴频鉴相器输出的正负误差信号,另外一个输入端接收一个判决时钟用来确定相位/频率判决的判决周期;所述逻辑电路的输出端作为D型触发器的输入端,D型触发器的另外一个输入端连接判决时钟信号,D型触发器输出高低电平来得到跟踪补偿后的信号。Further, the phase/frequency decider includes two logic circuits, and the two logic circuits include two NOR gate circuits, wherein an input end of the NOR gate receives the positive and negative error signals output by the digital frequency discriminator , the other input terminal receives a decision clock to determine the decision cycle of the phase/frequency decision; the output terminal of the logic circuit is used as the input terminal of the D-type flip-flop, and the other input terminal of the D-type flip-flop is connected to the decision clock signal, The D-type flip-flop outputs high and low levels to obtain the signal after tracking compensation.

进一步,所述可编程逻辑控制器可以为西门子S7-200或者三菱FX2N或者ABB的AC500。Further, the programmable logic controller may be Siemens S7-200 or Mitsubishi FX2N or ABB's AC500.

进一步,所述频率综合器可应用于机载雷达、车载雷达、航空雷达和卫星雷达。Further, the frequency synthesizer can be applied to airborne radar, vehicle radar, aviation radar and satellite radar.

进一步,所述数字分频器可以为偶数分频器、奇数分频器、小数分频器。Further, the digital frequency divider may be an even frequency divider, an odd frequency divider, or a fractional frequency divider.

本发明与现有技术相比,其有益效果在于:Compared with the prior art, the present invention has the following beneficial effects:

首先,本发明在频率综合器的电路中设置了可编程逻辑控制器,可以根据频率综合器的实际输入信号情况来调整环路滤波器的参数,进而丰富传统的频率综合器的功能和适应范围。First of all, the present invention sets a programmable logic controller in the circuit of the frequency synthesizer, which can adjust the parameters of the loop filter according to the actual input signal of the frequency synthesizer, thereby enriching the functions and adaptability of the traditional frequency synthesizer. .

其次,本发明还设置了相位/频率判决器来对输入信号进行相位和频率的判决,可以避免算数运算和代码转换,有效降低了电路的复杂度和功耗。Secondly, the present invention also sets a phase/frequency decider to decide the phase and frequency of the input signal, which can avoid arithmetic operation and code conversion, and effectively reduce the complexity and power consumption of the circuit.

最后,本发明提供的频率综合器结构灵活,复杂度低,功耗低,全数字处理,具有广阔的应用优势和经济前景。Finally, the frequency synthesizer provided by the present invention is flexible in structure, low in complexity, low in power consumption, fully digitally processed, and has broad application advantages and economic prospects.

附图说明Description of drawings

图1为本发明频率综合器的电路结构图。Fig. 1 is the circuit structure diagram of the frequency synthesizer of the present invention.

图2为本发明频率综合器中的数字鉴频鉴相器的电路结构图。FIG. 2 is a circuit structure diagram of a digital frequency and phase detector in the frequency synthesizer of the present invention.

图3为本发明频率综合器中的相位/频率判决器的电路结构图。Fig. 3 is the circuit structure diagram of the phase/frequency decider in the frequency synthesizer of the present invention.

具体实施方式Detailed ways

下面结合附图对本发明进一步说明。这些附图均为简化的示意图,仅以示意的方式说明本发明的基本结构,因此其仅显示与本发明有关的构成。The present invention will be further described below in conjunction with the accompanying drawings. These drawings are all simplified schematic diagrams, and only illustrate the basic structure of the present invention in a schematic manner, so they only show the structures related to the present invention.

随着通信、数字电视、卫星定位、航空航天和遥控遥测技术的不断发展,对频率源的频率稳定度、频谱纯度、频率范围和输出频率个数的要求越来越高。为了提高频率稳定度,经常采用晶体振荡器等方法来解决,但它不能满足频率个数多的要求,因此,目前大量采用频率合成技术。通过对频率进行加、减、乘、除运算,可从一个高稳定度和高准确度的标准频率源,产生大量的具有同一稳定度和准确度的不同频率。频率综合器是从一个或多个参考频率中产生多种频率的器件。它是现代通讯系统必不可少的关键电路,广泛应用于数字通信、卫星通信、雷达、导航、航空航天、遥控遥测以及高速仪器仪表等领域。以通信为代表的信息产业是当代发展最快的行业,因此,频率合成器也得到了较快发展,形成了完善的系列品种,市场需求也特别大。With the continuous development of communication, digital television, satellite positioning, aerospace and remote control telemetry, the requirements for frequency stability, spectral purity, frequency range and output frequency of frequency sources are getting higher and higher. In order to improve the frequency stability, methods such as crystal oscillators are often used to solve the problem, but it cannot meet the requirement of a large number of frequencies. Therefore, a large number of frequency synthesis techniques are currently used. By adding, subtracting, multiplying and dividing the frequency, a large number of different frequencies with the same stability and accuracy can be generated from a standard frequency source with high stability and accuracy. A frequency synthesizer is a device that generates multiple frequencies from one or more reference frequencies. It is an indispensable key circuit in modern communication systems, and is widely used in digital communication, satellite communication, radar, navigation, aerospace, remote control telemetry and high-speed instrumentation and other fields. The information industry represented by communications is the fastest growing industry in contemporary times. Therefore, frequency synthesizers have also developed rapidly, forming a complete series of varieties, and the market demand is also particularly large.

频率综合器的技术复杂度很高,经过了直接合成模拟式频率综合器、锁相式频率综合器、直接数字式频率综合器三个发展阶段。而其中锁相式频率合成器和直接数字式频率综合器受到各界关注,并得到迅猛发展。The technical complexity of frequency synthesizer is very high, and it has gone through three development stages: direct synthesis analog frequency synthesizer, phase-locked frequency synthesizer, and direct digital frequency synthesizer. Among them, the phase-locked frequency synthesizer and the direct digital frequency synthesizer have received attention from all walks of life and have developed rapidly.

本发明基于当前的发展趋势和技术需要,提出了一种结构简单、功能丰富的频率综合器。下面结合具体的实施例来对本发明进行说明。Based on the current development trend and technical requirements, the present invention proposes a frequency synthesizer with a simple structure and rich functions. The present invention will be described below with reference to specific embodiments.

实施例一:Example 1:

如图1示出了本发明的频率综合器的电路结构图,具体为:数字鉴频鉴相器、环路滤波器、数字压控振荡器、数字分频器、环路参数控制器、相位/频率判决器、可编程逻辑控制器;数字鉴频鉴相器的输出与相位/频率判决器相连,相位/频率判决器分别与环路滤波器和可编程逻辑控制器相连,环路滤波器与数字压控振荡器相连,压控振动器的输出与分频器相连,分频器的输出作为数字鉴频鉴相器的一路输入信号;同时数字可编程逻辑控制器与环路参数控制器相连,环路参数控制器与环路滤波器相连。Figure 1 shows the circuit structure diagram of the frequency synthesizer of the present invention, specifically: a digital frequency and phase detector, a loop filter, a digital voltage-controlled oscillator, a digital frequency divider, a loop parameter controller, a phase /Frequency decider, programmable logic controller; the output of the digital frequency discriminator is connected to the phase/frequency decider, and the phase/frequency decider is connected to the loop filter and the programmable logic controller respectively. The loop filter It is connected with the digital voltage-controlled oscillator, the output of the voltage-controlled oscillator is connected with the frequency divider, and the output of the frequency divider is used as an input signal of the digital frequency and phase detector; at the same time, the digital programmable logic controller and the loop parameter controller connected, the loop parameter controller is connected with the loop filter.

在本发明中,相关的数字鉴频鉴相器、数字压控振荡器、数字分频器都具备高分辨率、高线性、高复杂度的特点,以提升信号的处理性能和精度,而增加相位/频率判决器可以避免算数运算和代码转换,显著降低了电路结构的复杂性和功耗。In the present invention, the related digital phase detector, digital voltage-controlled oscillator, and digital frequency divider have the characteristics of high resolution, high linearity, and high complexity, so as to improve the signal processing performance and accuracy, and increase the The phase/frequency decider can avoid arithmetic operations and code conversion, significantly reducing the complexity and power consumption of the circuit structure.

进一步,数字鉴频鉴相器对输入参考信号和分频器的输出进行频率和相位的比较,然后得到一个代表相位/频率误差的信号给相位/频率判决器;相位/频率判决器根据误差信号进性判决,得到相位和频率的判决结果,并分别发送给环路滤波器和可编程逻辑控制器;可编程逻辑控制器根据相位/频率判决器的判决结果,进行环路滤波器的参数调整,并将调整的结果发送给环路参数控制器,环路参数控制器根据结果对环路滤波器进行控制。Further, the digital frequency discriminator compares the frequency and phase of the input reference signal and the output of the frequency divider, and then obtains a signal representing the phase/frequency error to the phase/frequency decider; the phase/frequency decider is based on the error signal. Progressive judgment, the judgment results of phase and frequency are obtained, and sent to the loop filter and the programmable logic controller respectively; the programmable logic controller adjusts the parameters of the loop filter according to the judgment results of the phase/frequency decider , and send the adjusted result to the loop parameter controller, and the loop parameter controller controls the loop filter according to the result.

进一步,环路滤波器中设置有可调谐电阻,环路参数控制器通过调节环路滤波器中的可调谐电阻来调节环路滤波器的性能。Further, a tunable resistor is provided in the loop filter, and the loop parameter controller adjusts the performance of the loop filter by adjusting the tunable resistor in the loop filter.

对于不同的待处理信号来说,其带宽的覆盖范围可能会很大,对于传统的频率综合器来说,其可以处理的带宽范围往往受到环状滤波器的性能限制,而单纯的扩大环状滤波器的处理范围一方面会增加环状滤波器的成本,也会降低环状滤波器的处理精度,而本发明中通过在电路中增加可编程的逻辑控制器,可编程逻辑控制器通过接收环路滤波器的输入信号来实时的根据待处理信号对环状滤波器进行调整,这样可以扩大环状滤波器的处理带宽范围,提升了综合滤波器的灵活性。For different signals to be processed, the bandwidth coverage may be very large. For traditional frequency synthesizers, the bandwidth that can be processed is often limited by the performance of the ring filter, and simply expanding the ring On the one hand, the processing range of the filter will increase the cost of the ring filter, and it will also reduce the processing accuracy of the ring filter. In the present invention, by adding a programmable logic controller to the circuit, the programmable logic controller receives The input signal of the loop filter is used to adjust the loop filter in real time according to the signal to be processed, which can expand the processing bandwidth range of the loop filter and improve the flexibility of the synthesis filter.

图2示出了本发明中使用的数字鉴频鉴相器的电路结构,其具体包括时钟预分频模块、多位计数器模块、多位寄存器模块、边沿检测模块,同时时钟预分频模块接收固定晶振时钟输入的时钟信号,然后经过偶数、奇数、半整数级联分频来输出参考时钟信号,然后将参考时钟信号输出给边沿检测模块和多位计数器模块,边沿检测接收反馈时钟信号,然后检测参考时钟信号和反馈时钟信号的边沿,根据二者的边沿情况得到相位/频率误差的信号。Fig. 2 shows the circuit structure of the digital frequency and phase detector used in the present invention, which specifically includes a clock prescaler module, a multi-bit counter module, a multi-bit register module, and an edge detection module. At the same time, the clock prescaler module receives Fix the clock signal input by the crystal oscillator clock, and then output the reference clock signal through even, odd, and half-integer cascade frequency division, and then output the reference clock signal to the edge detection module and the multi-bit counter module. The edge detection receives the feedback clock signal, and then Detect the edge of the reference clock signal and the feedback clock signal, and obtain the phase/frequency error signal according to the edge conditions of the two.

对于数字鉴频鉴相器来说,参考的时钟信号的选取十分重要,在本发明的数字鉴频鉴相器中,采用偶数分频,等占空比奇数分频以及半整数分频器的级联实现对固定时钟的分频得到固定占空比的多位计数时钟输入。这样提升了控制精度,同时降低了实现难度。For the digital frequency discriminator, the selection of the reference clock signal is very important. The multi-bit counting clock input with fixed duty cycle is obtained by cascading the frequency division of the fixed clock. This improves the control accuracy and reduces the difficulty of implementation.

同时本发明的数字鉴频鉴相器中,还设置了边沿检测模块来检测参考时钟和反馈时钟的边沿,在频率未锁定时,对频差进行计数,输出频差数字量;当频率锁定时,对相差进行计数,并在每个参考时钟的上升沿完成对线性相差数字量的更新。At the same time, in the digital frequency and phase detector of the present invention, an edge detection module is also set to detect the edge of the reference clock and the feedback clock, when the frequency is not locked, the frequency difference is counted, and the frequency difference digital quantity is output; when the frequency is locked , count the phase difference, and complete the update of the linear phase difference digital quantity on the rising edge of each reference clock.

图3示出了本发明中使用的相位/频率判决器的电路结构,其电路中具体包括四个或非门和两个D型触发器。FIG. 3 shows the circuit structure of the phase/frequency decider used in the present invention, and the circuit specifically includes four NOR gates and two D-type flip-flops.

进一步,相位/频率判决器包含两个逻辑电路1和逻辑电路2,两个逻辑电路包含两个或非门电路,其中或非门的一个输入端接收数字鉴频鉴相器输出的正负误差信号,另外一个输入端接收一个判决时钟用来确定相位/频率判决的判决周期;逻辑电路的输出端作为D型触发器的输入端,D型触发器的另外一个输入端连接判决时钟信号,D型触发器输出高低电平来得到跟踪补偿后的信号。Further, the phase/frequency decider includes two logic circuits 1 and 2, and the two logic circuits include two NOR gate circuits, wherein one input end of the NOR gate receives the positive and negative errors output by the digital frequency discriminator. signal, the other input terminal receives a decision clock to determine the decision cycle of the phase/frequency decision; the output terminal of the logic circuit is used as the input terminal of the D-type flip-flop, and the other input terminal of the D-type flip-flop is connected to the decision clock signal, D The type flip-flop outputs high and low levels to obtain the signal after tracking compensation.

具体地,两个逻辑电路在每次判决后都会被判决时钟信号进行复位以保证在每个时钟周期开始时进行稳定的输出,当下一个更新周期时间没有下降信号,则逻辑电路1保持高电平,而当判决时钟信号到达上升沿时,判决电路则输出频率/相位上升的高电平;而如果在更新周期时间内只有下降信号,则判决电路最终输出频率/相位下降的高电平。Specifically, the two logic circuits will be reset by the decision clock signal after each decision to ensure stable output at the beginning of each clock cycle. When there is no falling signal in the next update cycle time, logic circuit 1 remains high. , and when the decision clock signal reaches the rising edge, the decision circuit outputs a high level with a rising frequency/phase; and if there is only a falling signal within the update cycle time, the decision circuit finally outputs a high level with a falling frequency/phase.

如果需要更改判决电路的更新周期,则只需要改变电路的分频比就可以修改更新周期了。这种设计,可以有效的降低电路的复杂度、且可以在任何更新周期内工作,方便、灵活、准确、高效。If the update cycle of the decision circuit needs to be changed, the update cycle can be modified only by changing the frequency division ratio of the circuit. This design can effectively reduce the complexity of the circuit, and can work in any update cycle, which is convenient, flexible, accurate and efficient.

同时,具体地,综合成本、质量、性能三方面的考虑,可编程逻辑控制器可以从西门子S7-200或者三菱FX2N或者ABB的AC500三个型号中选取。At the same time, specifically, considering the three aspects of cost, quality and performance, the programmable logic controller can be selected from three models of Siemens S7-200, Mitsubishi FX2N or ABB's AC500.

进一步,频率综合器可应用于机载雷达、车载雷达、航空雷达和卫星雷达。Further, the frequency synthesizer can be applied to airborne radar, vehicle radar, aviation radar and satellite radar.

进一步,数字分频器可以为偶数分频器、奇数分频器、小数分频器。Further, the digital frequency divider may be an even frequency divider, an odd frequency divider, or a fractional frequency divider.

以上描述了本发明的实施方式,但是本领域技术人员应当理解,这仅是举例说明,本领域的技术人员在不背离本发明的原理和实质的前提下,可以对实施方式做出多种变更或修改,但这些变更和修改均落入本发明的保护范围。The embodiments of the present invention have been described above, but those skilled in the art should understand that these are only examples, and those skilled in the art can make various changes to the embodiments without departing from the principles and essence of the present invention. or modification, but these changes and modifications all fall into the protection scope of the present invention.

Claims (7)

1.一种全数字宽带频率综合器,其特征在于包括:数字鉴频鉴相器、环路滤波器、数字压控振荡器、数字分频器、环路参数控制器、相位/频率判决器、可编程逻辑控制器;其中,所述相位/频率判决器包括D型触发器和两个逻辑电路,所述两个逻辑电路一共包含两个或非门电路;数字鉴频鉴相器的输出与相位/频率判决器相连,所述两个或非门电路的其中一个输入端接收数字鉴频鉴相器输出的正负误差信号,另外一个输入端接收一个判决时钟用来确定相位/频率判决的判决周期;所述逻辑电路的输出端作为D型触发器的输入端,D型触发器的另外一个输入端连接判决时钟信号,D型触发器输出高电平或低电平对信号进行跟踪补偿;相位/频率判决器分别与环路滤波器和可编程逻辑控制器相连,环路滤波器与数字压控振荡器相连,数字压控振荡器的输出与数字分频器相连,数字分频器的输出作为数字鉴频鉴相器的一路输入信号;同时所述可编程逻辑控制器与环路参数控制器相连,环路参数控制器与环路滤波器相连。1. an all-digital broadband frequency synthesizer, is characterized in that comprising: digital frequency and phase detector, loop filter, digital voltage-controlled oscillator, digital frequency divider, loop parameter controller, phase/frequency decision device , programmable logic controller; wherein, the phase/frequency decision device includes a D-type flip-flop and two logic circuits, the two logic circuits include two NOR gate circuits in total; the output of the digital frequency discriminator It is connected with the phase/frequency decider, one of the input terminals of the two NOR gate circuits receives the positive and negative error signals output by the digital frequency discriminator, and the other input terminal receives a decision clock to determine the phase/frequency decision The output of the logic circuit is used as the input of the D-type flip-flop, the other input of the D-type flip-flop is connected to the judgment clock signal, and the D-type flip-flop outputs a high level or a low level to track the signal Compensation; the phase/frequency decider is connected with the loop filter and the programmable logic controller respectively, the loop filter is connected with the digital voltage-controlled oscillator, the output of the digital voltage-controlled oscillator is connected with the digital frequency divider, the digital frequency division The output of the device is used as an input signal of the digital frequency and phase detector; meanwhile, the programmable logic controller is connected with the loop parameter controller, and the loop parameter controller is connected with the loop filter. 2.根据权利要求1所述的频率综合器,其特征在于:所述数字鉴频鉴相器对输入参考信号和数字分频器的输出进行频率和相位的比较,然后得到一个代表相位/频率误差的信号给相位/频率判决器;相位/频率判决器根据误差信号进性判决,得到相位和频率的判决结果,并分别发送给环路滤波器和可编程逻辑控制器;可编程逻辑控制器根据相位/频率判决器的判决结果,进行环路滤波器的参数调整,并将调整的结果发送给环路参数控制器,环路参数控制器根据结果对环路滤波器进行控制。2. frequency synthesizer according to claim 1, is characterized in that: described digital frequency discriminator phase discriminator carries out the comparison of frequency and phase to the output of input reference signal and digital frequency divider, then obtains a representative phase/frequency The error signal is sent to the phase/frequency decider; the phase/frequency decider makes a progressive decision according to the error signal, and obtains the decision results of phase and frequency, and sends them to the loop filter and programmable logic controller respectively; programmable logic controller According to the decision result of the phase/frequency decider, the parameters of the loop filter are adjusted, and the adjusted result is sent to the loop parameter controller, and the loop parameter controller controls the loop filter according to the result. 3.根据权利要求2所述的频率综合器,其特征在于:所述环路滤波器中设置有可调谐电阻,所述环路参数控制器通过调节环路滤波器中的可调谐电阻来调节环路滤波器的性能。3. The frequency synthesizer according to claim 2, characterized in that: the loop filter is provided with a tunable resistance, and the loop parameter controller is adjusted by adjusting the tunable resistance in the loop filter performance of the loop filter. 4.根据权利要求1所述的频率综合器,其特征在于:所述数字鉴频鉴相器包括时钟预分频模块、多位计数器模块、多位寄存器模块、边沿检测模块,同时时钟预分频模块接收固定晶振时钟输入的时钟信号,然后经过偶数、奇数、半整数级联分频来输出参考时钟信号,然后将参考时钟信号输出给边沿检测模块和多位计数器模块,边沿检测接收反馈时钟信号,然后检测参考时钟信号和反馈时钟信号的边沿,根据二者的边沿情况得到所述相位/频率误差的信号。4. frequency synthesizer according to claim 1, is characterized in that: described digital frequency discrimination phase discriminator comprises clock prescaler module, multi-bit counter module, multi-bit register module, edge detection module, and clock prescaler simultaneously The frequency module receives the clock signal input by the fixed crystal oscillator clock, and then outputs the reference clock signal through even, odd, and half-integer cascade frequency division, and then outputs the reference clock signal to the edge detection module and the multi-bit counter module, and the edge detection receives the feedback clock Then, the edges of the reference clock signal and the feedback clock signal are detected, and the signal of the phase/frequency error is obtained according to the edge conditions of the two. 5.根据权利要求1所述的频率综合器,其特征在于:所述可编程逻辑控制器可以为西门子S7-200或者三菱FX2N或者ABB的AC500。5 . The frequency synthesizer according to claim 1 , wherein the programmable logic controller can be Siemens S7-200 or Mitsubishi FX2N or AC500 of ABB. 6 . 6.根据权利要求1所述的频率综合器,其特征在于:所述频率综合器可应用于机载雷达、车载雷达、航空雷达和卫星雷达。6. The frequency synthesizer according to claim 1, wherein the frequency synthesizer can be applied to airborne radar, vehicle radar, aviation radar and satellite radar. 7.根据权利要求1所述的频率综合器,其特征在于:所述数字分频器可以为偶数分频器、奇数分频器、小数分频器。7. The frequency synthesizer according to claim 1, wherein the digital frequency divider can be an even frequency divider, an odd frequency divider, or a fractional frequency divider.
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