CN109037175A - power device and its packaging method - Google Patents

Abstract

The present invention provides a kind of power device, it includes the chip of substrate and setting on the substrate, the chip includes substrate and the heat-conductive assembly for being formed in the substrate, the heat-conductive assembly includes that multiple be spaced is formed in the groove of the substrate lower surface, forms the first metal layer in the groove, form the second metal layer being connected over the substrate with the substrate, the depth of the groove is less than the thickness of the substrate, and the first metal layer and the second metal layer form Ohmic contact with the substrate.The present invention also provides the packaging methods of power device, enhance the radiating efficiency and driveability of chip, and the size after reducing chip package reduces manufacturing cost.

Description

Power device and packaging method thereof

technical field

The invention relates to the technical field of power semiconductor chip packaging technology, in particular to a power device and a packaging method thereof.

Background technique

At present, power chips can have good electrical and thermal performance and work reliability, which lead to more and more high temperature or temperature drift of the chip during use. High temperature has a great impact on the reliability and rapid aging of power electronic products. Large impact, and excessive temperature and temperature cycle often directly lead to premature failure of the product.

The traditional power chip package is directly soldered to the copper-clad ceramic substrate, and then the copper-clad ceramic substrate with the chip attached is connected to the heat sink. This package is called single-sided package. The heat dissipation channel of the single-sided package is mainly generated by the chip. The heat is transferred to the copper-clad ceramic substrate through the adhesive layer, and then transferred to the heat sink through another adhesive layer. Finally, the heat sink and air convection heat transfer or water cooling will dissipate the heat. However, the heat transfer direction in the single-sided package is determined by One-way transmission from the chip to the heat sink, although the overall heat dissipation capacity of the structure can be increased by using a connection material with a higher thermal conductivity or designing a heat sink with better heat dissipation capacity, resulting in low thermal diffusion efficiency of the chip, without increasing the chip area In some cases, if the heat dissipation layer is added, the manufacturing cost will also be increased.

Contents of the invention

In view of the above-mentioned existing problems, in order to solve the heat dissipation problem of the power device chip from the heat source, the present invention provides a power device, which can realize the addition of heat-conducting components inside the chip and the installation of heat sinks on the back of the chip, increasing the heat dissipation of the power device and improving the performance of the power device. The reliability of the chip operation is improved.

In order to achieve the above object, the present invention adopts the following technical solutions to achieve.

In one aspect, the present invention provides a power device, which includes a substrate and a chip disposed on the substrate, the chip includes the substrate and a heat conduction component formed on the substrate, and the heat conduction component includes a plurality of intervals formed A groove in the substrate, a first metal layer formed in the groove, a second metal layer formed on the substrate and connected to the substrate, the depth of the groove is smaller than the thickness of the substrate, both the first metal layer and the second metal layer form ohmic contacts with the substrate.

In the present invention, a plurality of trenches arranged at intervals are formed on the substrate, and a metal with good thermal conductivity is filled in the trenches to form the first metal layer, and the first metal layer is formed on the substrate and the first metal layer is formed on the substrate. A second metal layer connected to the metal layer and a substrate connected to the second metal layer, wherein the first metal layer is used to conduct heat in the chip to the second metal layer, and the second The metal layer then conducts heat to the substrate, thereby improving the thermal diffusion efficiency and driving performance of the chip ground, without additionally increasing the area of the chip, improving the integration of the power device, and reducing the manufacturing cost of the power device package.

On the other hand, the present invention also provides a packaging method for power devices, including the following process steps:

S1: providing a chip, the chip including a substrate;

S2: forming a plurality of grooves arranged at intervals from the lower surface of the substrate to the upper surface of the substrate, the depth of the grooves being smaller than the thickness of the substrate;

S3: introducing a mixed gas into the trench for thermal annealing to form a first metal layer, and the first metal layer is in ohmic contact with the substrate;

S4: metallizing the backside of the chip to form a second metal layer in ohmic contact with the substrate;

S5: Connecting the chip to the substrate to complete packaging of the chip.

In the present invention, a plurality of trenches arranged at intervals are formed on the substrate, and a metal with good thermal conductivity is filled in the trenches to form the first metal layer, and the first metal layer is formed on the substrate and the first metal layer is formed on the substrate. A second metal layer connected to the metal layer and a substrate connected to the second metal layer, the first metal layer is used to conduct heat in the chip to the second metal layer, the second metal layer The heat is then conducted to the substrate, thereby improving the thermal diffusion efficiency and driving performance of the chip, achieving better packaging effects, without additionally increasing the area of the chip, and reducing manufacturing costs.

Description of drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following will briefly introduce the drawings that need to be used in the description of the embodiments. Obviously, the drawings in the following description are some embodiments of the present invention. For Those of ordinary skill in the art can also obtain other drawings based on these drawings without making creative efforts.

Fig. 1 is the structural representation of power device of the present invention;

2 to 8 are diagrams of the packaging process of the power device of the present invention;

FIG. 9 is a flowchart of a packaging method for a power device of the present invention.

In the figure: power device 1; substrate 10; chip 20; substrate 30; epitaxial layer 31; active region 32; heat conduction component 40; groove 41; first metal layer 42; layer 50; second adhesive layer 60; heat sink 70.

Detailed ways

In order to understand the specific technical solutions, features and advantages of the present invention more clearly, the present invention will be further described in detail below in conjunction with the accompanying drawings and specific embodiments.

In the description of the present invention, it should be noted that the terms "upper", "lower", "left", "right", "transverse", "longitudinal", "horizontal", "inner", "outer" etc. indicate The orientation or positional relationship is based on the orientation or positional relationship shown in the drawings, or the orientation or positional relationship that is usually placed when the product of the invention is used, and is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying the It should not be construed as limiting the invention that a device or element must have a particular orientation, be constructed, and operate in a particular orientation. In addition, the terms "first", "second", "third", etc. are only used for distinguishing descriptions, and should not be construed as indicating or implying relative importance.

The present invention provides a method for improving the thermal diffusion efficiency of the power device 1 , reducing the packaging size of the chip 1 and improving the driving performance of the power device 1 .

In order to solve the above technical problems, on the one hand, the present invention provides the following technical solutions.

Referring to FIG. 1 , the present invention provides a power device 1, which includes a substrate 20 and a chip 20 disposed on the substrate 10, the chip 20 includes a substrate 30 and a heat conduction component 40 formed on the substrate 30, The heat conduction component 40 includes a plurality of grooves 41 formed at intervals in the substrate 30 , a first metal layer 42 formed in the grooves 41 , formed on the substrate 30 and connected to the substrate 10 The second metal layer 43 is connected, the depth of the groove 41 is smaller than the thickness of the substrate 30 , and both the first metal layer 42 and the second metal layer 43 form an ohmic contact with the substrate 30 .

By setting the heat conduction component 40 on the chip 20 to transfer the heat generated by its internal components to the outside of the chip 20, the heat conduction component 40 is connected to the substrate 10 through the first adhesive layer 50, so The substrate 10 is used to absorb the heat conducted by the heat conducting component 40, and the heat sink 70 is connected to the substrate 10 to facilitate the effective dissipation of the heat absorbed by the substrate 10, thereby improving the driving performance and service life. Wherein, the contact between the first metal layer 42 and the substrate 30 has a linear current-voltage characteristic or its contact resistance is negligible relative to the chip 20 to form an ohmic contact, so that the first metal layer 42 It has low resistance and high stability with the substrate 30, so as to ensure that the contact point (not shown) between the first metal layer 42 and the substrate 30 does not produce obvious additional resistance, the The resistance does not change with changes in temperature, current, etc., so that the thermal stability of the chip 20 is high. Similarly, the second metal layer 43 forms an ohmic contact with the substrate 20, so that the adhesion strength between the second metal layer 43 and the substrate 20 is improved and the contact quality is good, and the strength of the chip 20 is enhanced. drive performance.

Further, the power device 1 further includes a first adhesive layer 50 , a second adhesive layer 60 and a heat sink 70 , and the second metal layer 43 is connected to the substrate 10 through the first adhesive layer 50 , the substrate 10 is connected to the heat sink 70 through the second adhesive layer 60 .

Further, the chip 20 also includes an epitaxial layer 31 formed on the substrate 30 of the same conductivity type as the substrate 30 and an active region 32 formed on the epitaxial layer 31, the trench 41 Opening from the lower surface of the substrate 30 to the upper surface of the substrate 30 , the distance between the bottom of the trench 41 and the lower surface of the epitaxial layer 31 is greater than the thickness of the epitaxial layer 31 .

It can be understood that the heat generated by the power device 1 mainly comes from the active region 32, which is the region on the silicon wafer where active devices are made, that is, some well regions or isolated regions. The active region 32 is mainly for MOS, and different doping can form the N or P type active region 32 . The groove 41 is formed on the lower surface of the substrate 30, and the distance between the bottom of the groove 41 and the small surface of the epitaxial layer 31 is greater than the thickness of the epitaxial layer 31, so as to ensure the durability of the chip 20. pressure performance.

Referring to FIG. 2 to FIG. 8 and FIG. 9, on the other hand, the present invention also provides a packaging method for a power device 1, including the following process steps:

S1: providing a chip 20, the chip 20 comprising a substrate 30;

Specifically, please refer to 2, provide a chip 20 that has completed the front process, wherein the complete process of making the chip 20 includes chip 20 design and wafer production, the raw material composition of the wafer of the chip 20 is silicon, and silicon is made of Refined from quartz sand, the wafer is purified silicon element (99.999%), and then part of the pure silicon is made into a silicon crystal rod, which becomes the material of quartz semiconductor for manufacturing integrated circuits, and slices it to make specific wafers . The thinner the wafer, the lower the cost of production; the wafer coating film, the wafer coating film can resist oxidation and temperature resistance, and its material is a kind of photoresist; wafer photolithography development and etching, the process uses Chemicals that are sensitive to ultraviolet light become soft when exposed to ultraviolet light. The shape of the chip 20 can be obtained by controlling the positions of the shading objects. Coat photoresist on the silicon wafer so that it will dissolve when exposed to ultraviolet light, and then use a light-shielding object to dissolve the part directly exposed to ultraviolet light, and then wash away the dissolved part with a solvent, so that the remaining part is consistent with the light-shielding object The shape is the same, so as to obtain the required silicon dioxide layer; doping impurities, implanting ions into the wafer, and generating corresponding P and N semiconductors. The specific process starts with the exposed area on the silicon wafer and puts it into a chemical ion mixture. This process will change the conduction mode of the doped area, so that each transistor can be turned on, off, or carry data. The chip 20 may only use one layer, or may have many layers. At this time, this process is repeated continuously, and different layers can be connected by opening windows. In this embodiment, the backside of the chip 20 is thinned to 200-300 microns.

It can be understood that in this embodiment, the material of the substrate 30 of the chip 20 is silicon, and the back side of the silicon chip is thinned so as to remove excess material on the back side of the silicon chip. There are many techniques for thinning the back side of the chip 20, such as grinding, Polishing, dry polishing, electrochemical etching, wet etching, plasma-assisted chemical etching, and atmospheric pressure plasma etching, etc., one or more of them are used according to the actual situation. By thinning the back of the chip 20 to effectively reduce the packaging volume of the chip 20, reduce thermal resistance, improve the heat dissipation performance of the chip 20, and reduce the risk of cracking of the chip 20 due to uneven heating after packaging, The reliability of the power device 1 is improved, and at the same time, the mechanical and electrical properties of the thinned chip 20 are also significantly improved.

S2: forming a plurality of grooves 41 arranged at intervals from the lower surface of the substrate 30 to the upper surface of the substrate 30, the depth of the grooves 41 being smaller than the thickness of the substrate 30;

Specifically, referring to FIG. 3, a plurality of grooves 41 are sequentially formed by photolithography on the substrate 30 on the back side of the chip 20. The commonly used preparation methods include wet etching and dry etching to form the grooves. The process of 41 is: forming an etch barrier layer (not shown) on the substrate 30, then forming a photoresist layer (not shown) on the etch barrier layer, and then adopting a pattern having the groove 41 A mask plate is used to expose the photoresist layer, and then develop it to obtain a photoresist layer with the groove 41 pattern. Using the photoresist layer with the pattern of the trench 41 as a mask, the opening of the pattern of the trench 41 is etched on the etching barrier layer by using an etching method such as reactive ion etching (not shown in the figure). Then use the etch barrier layer with the pattern opening of the groove 41 as a mask, and use methods such as wet etching or dry etching to remove the region of the substrate 30 not covered by the etch barrier layer, and then The trench 41 is formed in the substrate 30 , and the width of the trench 41 is generally between 1-2 microns. Thereafter, the photoresist layer and the etching barrier layer may be removed by chemical cleaning or the like. In the above process, in order to ensure the exposure accuracy, an anti-reflection layer may also be formed between the photoresist layer and the etching stopper layer.

It can be understood that due to the unsatisfactory pattern etching fidelity of wet etching and the difficulty of controlling the minimum line of the etched pattern, dry etching can achieve anisotropic etching, thereby ensuring the fidelity of fine patterns after transfer. In this embodiment, the groove 41 is etched and formed on the substrate 30 by means of dry etching. The shape of the groove 41 can be striped, circular or square, but the The grooves 41 are arranged at intervals, and the formed grooves 41 are bar-shaped and have the same size. In other ways, they can be prepared according to actual needs, and the grooves 41 that meet the requirements can be obtained, which is convenient for subsequent filling of metal to improve heat conduction efficiency. In other embodiments, the depth and shape of the grooves 41 may be the same or different. In addition, the thickness of the epitaxial layer 31 is smaller than the distance from the bottom of the groove 41 to the bottom of the epitaxial layer 31, so as to ensure the The withstand voltage performance of the chip 20.

It can be understood that, in another embodiment, a plurality of spaced trenches 41 are formed on the substrate 30, and the method for forming the trenches 41 further includes first forming the trenches 41 with a certain depth by dry etching, Then wet etching is used to introduce oxygen into the trench 41 for oxidation, and then one or more oxides are dissolved through chemical reaction, and selective etching is used within a certain period of time to obtain the trench that meets the requirements. 41, wherein the reagents used for chemical corrosion are generally hydrofluoric acid and nitric acid corrosion system, which can avoid the pollution of metal ions, thereby increasing the area of the top of the trench 41, facilitating the subsequent filling of metal, and improving the heat dissipation of the chip 20. diffusion. In other implementation manners, the method of forming the trenches 41 may only use wet etching, but it should be noted that the formation of the trenches 41 is arranged at intervals, and the bottom of the trenches 41 reaches the The distance of the epitaxial layer 31 is greater than the thickness of the epitaxial layer 31 , which will not affect the withstand voltage performance of the chip 20 and protect the stability of the power device 1 .

S3: Introducing a mixed gas into the trench 41 for thermal annealing to form a first metal layer 42, and the first metal layer 41 is in ohmic contact with the substrate 30;

Specifically, referring to Fig. 4 and Fig. 5, after the groove 41 is formed, it is filled with a metal with better thermal conductivity (such as silver or aluminum), and then a mixed gas is introduced into the groove 41. In this embodiment , the mixed gas is nitrogen and hydrogen, and then rapid thermal annealing is performed, wherein the flow ratio of nitrogen and hydrogen is within 2, that is, the nitrogen flow rate is 2L/min, the hydrogen flow rate is less than 4L/min, and the thermal annealing temperature is 350-450°C .

It can be understood that silver and aluminum are metals with high thermal conductivity and low stress in the metal itself. Stress refers to the concentration of internal forces that are equal in size but opposite in direction to resist external forces when the material is released and deformed. It is called stress, and the product of stress and micro-area is the internal force, or when an object is deformed due to external factors (force, temperature change, etc.), the internal force that interacts between the various parts of the object is generated to resist the effect of this external factor , and return the object from its deformed position to its pre-deformed position. After the metal is filled, a mixed gas of nitrogen and hydrogen is introduced, and the flow ratio of the two gases is within 2, so as to treat the surface state of the chip 20 and prevent the metal from being oxidized during the thermal annealing process. Because in the actual described power device 1, its semiconductor material cannot be infinite, and there is always a certain boundary, so the surface (boundary) effect has a very important influence on the characteristics of the semiconductor device, and in most cases the characteristics of the semiconductor device It is determined by the semiconductor surface effect rather than the internal effect (such as MOS). The ideal surface refers to the symmetry of the atomic arrangement in the surface layer is exactly the same as that of the atoms in the body, and the infinite crystal surface (that is, the free surface of the crystal) that does not attach any atoms or molecules to the surface. When the chip 20 is stopped suddenly, the ideal periodic lattice on the surface is interrupted, resulting in an electronic state (energy level) in the forbidden band, which is the surface state. Therefore, silver and aluminum are used as metal materials. The heat conduction efficiency inside the chip 20 can be enhanced, the mixed gas can be introduced to prevent the surface state of the chip 20 surface, so that the metal can be better filled in the groove 41, without affecting the stability of the chip 20, and improving The efficiency of forming the first metal layer 42 is improved.

S4: metallizing the back of the chip 20 to form a second metal layer 43 in ohmic contact with the substrate 30;

Specifically, please refer to FIG. 6, on the surface of the substrate 30 on the back of the chip 20, a non-noble metal is plated on the surface of the substrate 30 by evaporation or sputtering. In this embodiment, the non-noble metal can be aluminum, titanium or chromium, and then Alloying is carried out at a temperature of 300-400°C, nitrogen or hydrogen, and an atmosphere of 6.5L/min, so that non-noble metals and silicon are alloyed to form an adhesion layer; Non-precious metal titanium, nickel, tin-copper alloy, or vanadium, nickel, tin-copper alloy, or chromium, nickel, tin-copper alloy form a barrier layer; finally, the surface of the barrier layer is plated with precious metal gold by evaporation or sputtering , forming a conductive layer.

It can be understood that the backside metallization system of the chip 20 includes an ohmic contact layer, a diffusion barrier layer and a conductive layer (this layer may be a solderable layer and an anti-oxidation layer). Wherein the backside metallization material in this embodiment is nickel-gold double-layer metal, and nickel not only serves as the adhesive layer that contacts with silicon, but also serves as the barrier layer that prevents gold and silicon from forming an alloy, but the linear expansion coefficient of nickel is different from that of silicon. The difference in coefficient of linear expansion will cause great stress on the chip 20 , and the adhesion between metal nickel and silicon is average, which may cause the metal and silicon to fall off during the thermal cycle. Titanium and silicon have good adhesion, easy to form ohmic contact, relatively stable chemical properties and mechanical strength, and are not easy to form high-resistance compounds with silicon or the metal on it. The linear expansion coefficient of titanium is close to that of silicon, and is similar to that of silicon. There is a better thermal match. The metallized metal layer on the back side increases metal titanium as an adhesion layer, which is conducive to improving the adhesion between the metal on the back side and silicon, thereby ensuring the mechanical strength and electrical properties between the chip 20 and the solder, and improving the thermal conductivity of the chip 20. Fatigue life and product quality.

S5: Connect the chip 20 to the substrate 10 to complete the packaging of the chip 20 .

Specifically, referring to FIG. 7 , after the second metal layer 43 is formed on the chip 20, the second metal layer 43 is connected to the substrate 10 through the first adhesive layer 50. In this embodiment, the The substrate 10 is a copper-clad ceramic substrate (DBC), the lower surface of the second metal layer 43 is connected to the upper surface of the first adhesive layer 50, and the upper surface of the substrate 10 is connected to the first adhesive layer 50. The lower surface of layer 50 is connected.

It can be understood that the second metal layer 43 is connected to the substrate 10 through the first adhesive layer 50. In this embodiment, the copper-clad ceramic substrate has excellent thermal cycle performance, stable shape, and good rigidity. , high thermal conductivity, high reliability, the copper clad surface can be etched with various graphics characteristics, and it is a pollution-free, pollution-free green product, the use temperature is quite wide, from -55 ° C to 850 ° C, The thermal expansion coefficient is close to that of silicon, and can be used in semiconductor refrigerators, electronic heaters, high-power power semiconductor modules, power control circuits, power hybrid circuits, intelligent power components, high-frequency switching power supplies, solid-state relays, automotive electronics, aerospace and military Electronic components, solar panel components, telecommunications private switches, receiving systems, lasers and many other industrial electronics fields. Based on the characteristics of the above-mentioned copper-clad ceramic substrate, there are many ways to realize the bonding of the second metal layer 43 and the substrate 10 by using the copper-clad ceramic substrate technology. The effective alloying method widely used in industry is thick film method and molybdenum manganese method. The thick film method is composed of fine particles of precious metals by crimping together, and then adhered to the ceramic by molten glass, so the conductivity of the thick film is worse than that of metal copper. Although the molybdenum-manganese method makes the metal layer have relatively high electrical conductivity, the thickness of the metal layer is very thin, less than 25 μm, which limits the surge resistance of the power device 1 . Therefore, a new method of metal-ceramic bonding is adopted to improve the electrical conductivity of the second metal layer 43 and the ability to withstand large currents, reduce the contact thermal resistance between the second metal layer 43 and the substrate 10, and The manufacturing process is simple, thus reducing the manufacturing cost of the package of the power device 1 .

In addition, please refer to FIG. 8 , after the connection between the second metal layer 43 and the substrate 10 is completed, the substrate 10 is connected to the heat sink 70 through the second adhesive layer 60, and film is pasted and diced, and finally The package welding of the chip 20 is completed.

It can be understood that the second adhesive layer 60 is located between the substrate 10 and the heat sink 70, and the chip 20 is welded after completion. There are two welding methods for the chip 20: one is manual The method is to tin-plate the pad with an electric soldering iron first, then clamp one end of the chip with tweezers, fix the other end of the chip 20 on the corresponding pad of the device with a soldering iron, and remove the tweezers after the solder is slightly cooled. Solder the other end of the chip 20 with a soldering iron. The second is machine welding. The method is to make a printed stencil, print the solder paste on the circuit board, and then place the soldered chips 20 by hand or by machine placement, and finally The chips 20 are soldered through a high-temperature soldering furnace. In this embodiment, machine welding is preferably used, so as to improve the efficiency and accuracy of the chip 20 welding.

In the present invention, a plurality of grooves 41 arranged at intervals are formed on the substrate 30 , and metal with good thermal conductivity is filled in the grooves 41 to form the first metal layer 42 , formed on the substrate 10 The second metal layer 43 connected to the first metal layer 42 and the substrate 44 connected to the second metal layer 43, the first metal layer 42 is used to conduct the heat in the chip 1 to the The second metal layer 43, the second metal layer 43 conducts heat to the substrate 44, thereby improving the thermal diffusion efficiency and driving performance of the chip 20, achieving better packaging effect, without additionally increasing the chip 20 area, reducing the manufacturing cost of the chip 20 package.

The above is only a preferred embodiment of the present invention, but the scope of protection of the present invention is not limited thereto, any person familiar with the technical field within the technical scope disclosed in the present invention, according to the technical solution of the present invention Any equivalent replacement or change of the inventive concepts thereof shall fall within the protection scope of the present invention.

Claims (10)

1. A power device, characterized in that: it includes a substrate and a chip arranged on the substrate, the chip includes a substrate and a heat conduction component formed on the substrate, and the heat conduction component includes a plurality of intervals formed A groove on the lower surface of the substrate, a first metal layer formed in the groove, a second metal layer formed on the substrate and connected to the substrate, the depth of the groove is smaller than the thickness of the substrate, both the first metal layer and the second metal layer form ohmic contacts with the substrate. 2. The power device according to claim 1, characterized in that: the power device further comprises a first adhesive layer, a second adhesive layer and a heat sink, and the second metal layer passes through the first adhesive layer is connected to the substrate, and the substrate is connected to the heat sink through the second adhesive layer. 3. The power device according to claim 1, wherein the chip further comprises an epitaxial layer formed on the substrate with the same conductivity type as the substrate and an active layer formed on the epitaxial layer. region, the trench is opened from the lower surface of the substrate to the upper surface of the substrate, and the distance between the bottom of the trench and the lower surface of the epitaxial layer is greater than the thickness of the epitaxial layer. 4. A packaging method for a power device according to claim 1, characterized in that: S1: providing a chip, the chip including a substrate; S2: forming a plurality of grooves arranged at intervals from the lower surface of the substrate to the upper surface of the substrate, the depth of the grooves being smaller than the thickness of the substrate; S3: introducing a mixed gas into the trench for thermal annealing to form a first metal layer, and the first metal layer is in ohmic contact with the substrate; S4: metallizing the backside of the chip to form a second metal layer in ohmic contact with the substrate; S5: Connecting the chip to the substrate to complete packaging of the chip. 5 . The method for packaging power devices according to claim 4 , characterized in that: after the step S1 , the backside of the chip is thinned first, and then the step S2 is performed. 6 . 6 . The manufacturing method of the package structure according to claim 4 , wherein in the step S3 , first filling the trench with the first metal, and then injecting the mixed gas. 7 . 7. The method for packaging power devices according to claim 6, wherein the mixed gas is nitrogen and hydrogen, and the flow rate of the hydrogen gas is less than twice the flow rate of the nitrogen gas. 8. The method for packaging power devices according to claim 4, characterized in that: in the step S4, a second metal is added to the lower surface of the substrate and metallized to form the second metal layer. 9 . The method for packaging power devices according to claim 4 , wherein after the step S4 is completed, a thin film layer is formed on the surface of the second metal layer, and then the chips are diced and cut. 10. The packaging method of power devices according to claim 4, characterized in that: in the step S5, a first adhesive layer, a second adhesive layer and a heat sink are connected to the back of the chip, and the first The two metal layers are connected to the substrate through the first adhesive layer, the substrate is connected to the heat sink through the second adhesive layer, and then the chip is soldered.