CN109003894A - A kind of process improving double-pattern etching core model top fillet - Google Patents
A kind of process improving double-pattern etching core model top fillet Download PDFInfo
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- CN109003894A CN109003894A CN201810800712.XA CN201810800712A CN109003894A CN 109003894 A CN109003894 A CN 109003894A CN 201810800712 A CN201810800712 A CN 201810800712A CN 109003894 A CN109003894 A CN 109003894A
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- core model
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- etching
- side wall
- model layer
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- 238000000034 method Methods 0.000 title claims abstract description 87
- 230000008569 process Effects 0.000 title claims abstract description 58
- 238000005530 etching Methods 0.000 title claims abstract description 50
- 238000001039 wet etching Methods 0.000 claims abstract description 14
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 10
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 claims description 7
- 230000008021 deposition Effects 0.000 claims description 7
- 238000005516 engineering process Methods 0.000 claims description 7
- 239000007788 liquid Substances 0.000 claims description 7
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 6
- 239000002253 acid Substances 0.000 claims description 6
- 239000004065 semiconductor Substances 0.000 claims description 6
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 6
- 230000000694 effects Effects 0.000 claims description 5
- 239000000377 silicon dioxide Substances 0.000 claims description 5
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 claims description 4
- 239000000126 substance Substances 0.000 claims description 4
- 239000000758 substrate Substances 0.000 claims description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 3
- 239000013043 chemical agent Substances 0.000 claims description 3
- 229910000040 hydrogen fluoride Inorganic materials 0.000 claims description 3
- 229910052710 silicon Inorganic materials 0.000 claims description 3
- 239000010703 silicon Substances 0.000 claims description 3
- 230000003628 erosive effect Effects 0.000 claims description 2
- 238000000101 transmission high energy electron diffraction Methods 0.000 abstract description 10
- 230000006872 improvement Effects 0.000 abstract description 7
- 238000007670 refining Methods 0.000 abstract description 5
- 239000012528 membrane Substances 0.000 abstract description 3
- 238000004519 manufacturing process Methods 0.000 description 4
- 239000013078 crystal Substances 0.000 description 2
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 2
- DDFHBQSCUXNBSA-UHFFFAOYSA-N 5-(5-carboxythiophen-2-yl)thiophene-2-carboxylic acid Chemical compound S1C(C(=O)O)=CC=C1C1=CC=C(C(O)=O)S1 DDFHBQSCUXNBSA-UHFFFAOYSA-N 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 230000009977 dual effect Effects 0.000 description 1
- 238000003384 imaging method Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 125000006850 spacer group Chemical group 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
- H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
- H01L21/0337—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
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- Engineering & Computer Science (AREA)
- Chemical & Material Sciences (AREA)
- Inorganic Chemistry (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Weting (AREA)
Abstract
The invention proposes a kind of processes of SADP technique core mould top round looks in improvement 38nm and following process node.The biggish core model film quality of two layers of etching selection ratio is grown by selection, in first time core model process for refining, the film quality on top is not etched or lost after a little while, using the isotropism feature of wet etching, core model lower membrane is made to form the big small pattern in bottom in top.After removing core model top film layer, in second of core model process for refining, the isotropism feature of wet etching is utilized again, ultimately forms side wall perpendicular to the core model pattern on surface, be conducive to the operation of subsequent side wall and etching technics, greatly improve subsequent double-pattern etching technics window.
Description
Technical field
The present invention relates to semiconductor integrated circuit manufacturing fields, and in particular to a kind of improvement double-pattern etches core model top
Hold the process of fillet.
Background technique
As the process node of semiconductors manufacture is constantly urged downwardly into, critical size constantly reduces, and has had exceeded at present
The physics limit of the photoetching process of mainstream.In the manufacture of 38nm and following process node, general to will use autoregistration dual
Imaging process (Self-aligned Double Patterning, SADP).In SADP technique, for convenience of subsequent etching work
Skill, it is desirable that the side pattern of the side wall (spacer) as hard mask plate is as far as possible perpendicular to crystal column surface.This requires sides
The top core model (core) pattern of wall avoids the occurrence of " fillet " pattern (rounding) as far as possible perpendicular to crystal column surface.
Shown in the current following Fig. 1 a~Fig. 1 d of mainstream SADP technique way: using silica as core model 10, by wet
Method technique refines core model 10 to the critical size needed, then uses silicon nitride (SiN) as side wall 20.It is gone using wet processing
Except the silica of core model 10, hardmask plate of the silicon nitride as subsequent etching processes of side wall 20 is left.Due to wet processing
Have the characteristics that isotropic etching, it is general that 10 top of core model can all be caused fillet phenomenon occur, influence subsequent side wall 20
Pattern, finally influence subsequent critical size etching technics.Current technique can only accomplish to reduce 10 nose-circle of core model to the greatest extent
The effect at angle, it is difficult to avoid completely.
Summary of the invention
The invention proposes double-patterns in a kind of improvement 38nm and following process node to manufacture (SADP) technique core mould
The process of top round looks.
In order to achieve the above object, the technique side that the present invention proposes a kind of improvement double-pattern etching core model top fillet
Method, including the following steps:
Core model layer is formed on a semiconductor substrate comprising the first core model layer and the second core model layer；
Carry out first time core model layer micronization processes；
Remove the second core model layer；
Carry out second of core model layer micronization processes so that at the top of the first core model layer pattern under isotropic etching effect,
Keep vertical profile；
Carry out subsequent side wall technique and core model removal technique.
Further, the first core model layer and the second core model layer have acid etch liquid in core model layer micronization processes
Different etching selection ratios.
Further, in the first time core model layer micronization processes, the second core model layer etch amount is less than described first
Core model layer.
Further, in the first time core model layer micronization processes, the second core model layer is without etching, just for institute
The first core model layer is stated to perform etching.
Further, in the side wall technique, after side wall growth and etching technics, the dielectric layer of deposit is and the side
Wall technique has the film layer of different wet process etching selection ratios.
Further, the side wall medium layer is formed using ethyl orthosilicate or high temperature oxide deposition.
Further, the side wall technique further includes the steps that the sacrificial layer of chemical mechanical grinding deposit, the sacrificial layer
With the core model layer and the side wall medium layer there are different grinding rates to select ratio.
Further, the sacrificial layer includes silicon nitride, in high density plasma deposition silica and silicon oxynitride
It is one or more of.
Further, the second core model layer of the removal and side wall medium layer use wet-etching technology.
Further, the wet-etching technology is compared using side wall medium layer, core model layer and side wall film layer etching selection
High chemical agent, including dilute hydrogen fluoride acid or buffered oxide etch liquid.
The invention proposes SADP technique core mould top round looks in a kind of improvement 38nm and following process node
Process.The biggish core model film quality of two layers of etching selection ratio, in first time core model process for refining, top are grown by selection
Film quality do not etch or lose after a little while, using the isotropism feature of wet etching, core model lower membrane is made to form the big bottom in top
Small pattern.After removing core model top film layer, in second of core model process for refining, each to same of wet etching is utilized again
Property feature, ultimately forms side wall perpendicular to the core model pattern on surface, is conducive to the operation of subsequent side wall and etching technics, greatly
Improve subsequent double-pattern etching technics window.
Detailed description of the invention
Fig. 1 a~Fig. 1 d show SADP process flow chart in the prior art.
Fig. 2 show the process process for improving double-pattern etching core model top fillet of present pre-ferred embodiments
Figure.
Fig. 3 a~Fig. 3 d show the SADP process flow chart of present pre-ferred embodiments.
Specific embodiment
A specific embodiment of the invention is provided below in conjunction with attached drawing, but the present invention is not limited to the following embodiments and the accompanying drawings.Root
According to following explanation and claims, advantages and features of the invention will be become apparent from.It should be noted that attached drawing be all made of it is very simple
The form of change and use non-accurate ratio, be only used for conveniently, lucidly aid in illustrating the embodiment of the present invention purpose.
Referring to FIG. 2, Fig. 2 show the work for improving double-pattern etching core model top fillet of present pre-ferred embodiments
Process flow chart.The present invention proposes a kind of process of improvement double-pattern etching core model top fillet, including following step
It is rapid:
Step S100: core model layer is formed on a semiconductor substrate comprising the first core model layer and the second core model layer；
Step S200: first time core model layer micronization processes are carried out；
Step S300: removal the second core model layer；
Step S400: carrying out second of core model layer micronization processes, so that pattern is carved in isotropism at the top of the second core model layer
Under erosion effect, vertical profile is kept；
Step S500: subsequent side wall technique and core model removal technique are carried out.
The SADP process flow chart of present pre-ferred embodiments is shown referring again to Fig. 3 a~Fig. 3 d, Fig. 3 a~Fig. 3 d.
Present pre-ferred embodiments once form the first core model layer 200 and the second core model layer 300 on a semiconductor substrate 100, and described
One core model layer 200 and the second core model layer 300 have relatively big difference in core model layer micronization processes (sliming), to acid etch liquid
Etching selection ratio, please refer to shown in Fig. 3 a.
In the first time core model layer micronization processes, 300 etch amount of the second core model layer is less than the first core model layer
200.Further, in the first time core model layer micronization processes, the second core model layer 300 without etching, i.e., just for
The first core model layer 200 performs etching.It please refers to shown in Fig. 3 b.
Then the second core model layer 300 is removed by wet-etching technology, please referred to shown in Fig. 3 c.Then second is carried out
Secondary core model layer micronization processes, so that 200 top pattern of the first core model layer keeps vertical profile under isotropic etching effect,
It please refers to shown in Fig. 3 d.Subsequent side wall technique and core model removal technique are finally carried out, the hard exposure mask pattern of preferable side wall is formed,
To be conducive to subsequent etching technics.In order to reach the process conditions of requirement, the first core model layer 200, the second core model layer 300, side
The deposition thickness of wall is both needed to adjust according to actual needs.
Preferred embodiment according to the present invention, in the side wall technique, after side wall growth and etching technics, the medium of deposit
To have the film layer of significantly different wet etching selection ratio with the side wall technique, the side wall medium layer includes but is not limited to layer
It is formed using ethyl orthosilicate (TEOS) or high-temperature oxide (HTO) deposition.
Further, the side wall technique further includes the steps that the sacrificial layer of chemical mechanical grinding deposit, the sacrificial layer
With the core model layer and the side wall medium layer there is significantly different grinding rate to select ratio.Chemical mechanical grinding deposits sacrificial
Domestic animal layer is used depending on process requirements, and the sacrificial layer includes but is not limited to silicon nitride, high density plasma deposition silica
One or more of (High Density Plasma, referred to as " HDP ") and silicon oxynitride (SION).
The second core model layer of the removal and side wall medium layer use wet-etching technology, and the wet-etching technology uses side
Wall dielectric layer, core model layer and the higher chemical agent of side wall film layer etching selection ratio, including but not limited to dilute hydrogen fluoride acid (Dilute
Hydrofluoric Acid, DHP) or buffered oxide etch liquid (Buffered Oxide Etch, BOE), buffer oxide
Etching liquid is mixed with water or ammonium fluoride with water by hydrofluoric acid (49%).
In conclusion the invention proposes SADP technique core mould nose-circles in a kind of improvement 38nm and following process node
The process of angular looks.The biggish core model film quality of two layers of etching selection ratio is grown by selection, refines work in first time core model
When skill, the film quality on top is not etched or is lost after a little while, using the isotropism feature of wet etching, core model lower membrane is made to form top
The small pattern in the big bottom in portion.After removing core model top film layer, in second of core model process for refining, wet etching is utilized again
Isotropism feature, ultimately form side wall perpendicular to the core model pattern on surface, be conducive to the work of subsequent side wall and etching technics
Industry greatly improves subsequent double-pattern etching technics window.
Although the present invention has been disclosed as a preferred embodiment, however, it is not to limit the invention.Skill belonging to the present invention
Has usually intellectual in art field, without departing from the spirit and scope of the present invention, when can be used for a variety of modifications and variations.Cause
This, the scope of protection of the present invention is defined by those of the claims.
Claims (10)
1. a kind of process for improving double-pattern etching core model top fillet, characterized in that it comprises the following steps:
Core model layer is formed on a semiconductor substrate comprising the first core model layer and the second core model layer；
Carry out first time core model layer micronization processes；
Remove the second core model layer；
Second of core model layer micronization processes is carried out, so that pattern is kept under isotropic etching effect at the top of the first core model layer
Vertical profile；
Carry out subsequent side wall technique and core model removal technique.
2. the process according to claim 1 for improving double-pattern etching core model top fillet, which is characterized in that institute
The first core model layer and the second core model layer are stated in core model layer micronization processes, there is different etching selection ratios to acid etch liquid.
3. the process according to claim 1 for improving double-pattern etching core model top fillet, which is characterized in that institute
It states in first time core model layer micronization processes, the second core model layer etch amount is less than the first core model layer.
4. the process according to claim 1 for improving double-pattern etching core model top fillet, which is characterized in that institute
It states in first time core model layer micronization processes, the second core model layer is carved without etching just for the first core model layer
Erosion.
5. the process according to claim 1 for improving double-pattern etching core model top fillet, which is characterized in that institute
It states in side wall technique, after side wall growth and etching technics, the dielectric layer of deposit is and the side wall technique has different wet processes
The film layer of etching selection ratio.
6. the process according to claim 5 for improving double-pattern etching core model top fillet, which is characterized in that institute
Side wall medium layer is stated to be formed using ethyl orthosilicate or high temperature oxide deposition.
7. the process according to claim 5 for improving double-pattern etching core model top fillet, which is characterized in that institute
State the sacrificial layer that side wall technique further includes the steps that chemical mechanical grinding deposit, the sacrificial layer and the core model layer and described
There are side wall medium layer different grinding rates to select ratio.
8. the process according to claim 7 for improving double-pattern etching core model top fillet, which is characterized in that institute
Stating sacrificial layer includes silicon nitride, one or more of high density plasma deposition silica and silicon oxynitride.
9. the process according to claim 5 for improving double-pattern etching core model top fillet, which is characterized in that institute
The second core model layer of removal and side wall medium layer are stated using wet-etching technology.
10. the process according to claim 8 for improving double-pattern etching core model top fillet, which is characterized in that
The wet-etching technology uses side wall medium layer, core model layer and the higher chemical agent of side wall film layer etching selection ratio, including
Dilute hydrogen fluoride acid or buffered oxide etch liquid.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810800712.XA CN109003894B (en) | 2018-07-20 | 2018-07-20 | Process method for improving top end fillet of dual-pattern etching mandrel |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201810800712.XA CN109003894B (en) | 2018-07-20 | 2018-07-20 | Process method for improving top end fillet of dual-pattern etching mandrel |
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| CN109003894A true CN109003894A (en) | 2018-12-14 |
| CN109003894B CN109003894B (en) | 2020-11-13 |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109950141A (en) * | 2019-04-18 | 2019-06-28 | 上海华力微电子有限公司 | A kind of forming method of semiconductor structure |
| CN113130751A (en) * | 2021-03-02 | 2021-07-16 | 长鑫存储技术有限公司 | Manufacturing method of semiconductor structure and semiconductor structure |
| US12198932B2 (en) | 2021-03-02 | 2025-01-14 | Changxin Memory Technologies, Inc. | Method of manufacturing semiconductor structure including spacer filler etch and stacked mandrel layers and semiconductor structure |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6541360B1 (en) * | 2001-04-30 | 2003-04-01 | Advanced Micro Devices, Inc. | Bi-layer trim etch process to form integrated circuit gate structures |
| KR20090067608A (en) * | 2007-12-21 | 2009-06-25 | 주식회사 하이닉스반도체 | Pattern formation method of semiconductor device |
| CN103515197A (en) * | 2012-06-26 | 2014-01-15 | 中芯国际集成电路制造(上海)有限公司 | Self-aligned multi-patterning mask layer and formation method thereof |
| CN103578930A (en) * | 2012-07-20 | 2014-02-12 | 中芯国际集成电路制造(上海)有限公司 | Forming method for multiple graphical mask layer and semiconductor structure |
| CN105977141A (en) * | 2016-05-10 | 2016-09-28 | 上海格易电子有限公司 | Auto-aligning double patterning method |
| CN107359111A (en) * | 2016-05-10 | 2017-11-17 | 上海格易电子有限公司 | A kind of method of self-alignment duplex pattern |
| CN107742608A (en) * | 2017-11-23 | 2018-02-27 | 长江存储科技有限责任公司 | Double Pattern Sidewall Mask Etching Process |
-
2018
- 2018-07-20 CN CN201810800712.XA patent/CN109003894B/en active Active
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6541360B1 (en) * | 2001-04-30 | 2003-04-01 | Advanced Micro Devices, Inc. | Bi-layer trim etch process to form integrated circuit gate structures |
| KR20090067608A (en) * | 2007-12-21 | 2009-06-25 | 주식회사 하이닉스반도체 | Pattern formation method of semiconductor device |
| CN103515197A (en) * | 2012-06-26 | 2014-01-15 | 中芯国际集成电路制造(上海)有限公司 | Self-aligned multi-patterning mask layer and formation method thereof |
| CN103578930A (en) * | 2012-07-20 | 2014-02-12 | 中芯国际集成电路制造(上海)有限公司 | Forming method for multiple graphical mask layer and semiconductor structure |
| CN105977141A (en) * | 2016-05-10 | 2016-09-28 | 上海格易电子有限公司 | Auto-aligning double patterning method |
| CN107359111A (en) * | 2016-05-10 | 2017-11-17 | 上海格易电子有限公司 | A kind of method of self-alignment duplex pattern |
| CN107742608A (en) * | 2017-11-23 | 2018-02-27 | 长江存储科技有限责任公司 | Double Pattern Sidewall Mask Etching Process |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109950141A (en) * | 2019-04-18 | 2019-06-28 | 上海华力微电子有限公司 | A kind of forming method of semiconductor structure |
| CN113130751A (en) * | 2021-03-02 | 2021-07-16 | 长鑫存储技术有限公司 | Manufacturing method of semiconductor structure and semiconductor structure |
| US12198932B2 (en) | 2021-03-02 | 2025-01-14 | Changxin Memory Technologies, Inc. | Method of manufacturing semiconductor structure including spacer filler etch and stacked mandrel layers and semiconductor structure |
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