CN108984350B - Interrupt processing function verification system and method - Google Patents
Interrupt processing function verification system and method Download PDFInfo
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- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/2205—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested
- G06F11/2231—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested to test interrupt circuits
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- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/26—Functional testing
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- G06F11/26—Functional testing
- G06F11/263—Generation of test inputs, e.g. test vectors, patterns or sequences ; with adaptation of the tested hardware for testability with external testers
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Abstract
The invention provides an interrupt processing function verification system and method. The verification system includes: a sequence generator for generating interrupt data, the interrupt data comprising a configuration value of an interrupt handler or an interrupt source; the driver is used for converting the interrupt data into an interrupt input signal and sending the interrupt input signal to the interrupt processor; an interrupt processor configured to configure the interrupt processor when the received interrupt input signal is a configuration value of the interrupt processor; when the received interrupt input signal is an interrupt source, performing interrupt processing on the interrupt source to generate an interrupt response and a reference response, and sending the interrupt response and the reference response to a score board; and the score board is used for verifying the interrupt processing function by comparing the interrupt response with the reference response. The embodiment of the invention verifies that the environment has higher efficiency, stronger completeness, automation and reusability.
Description
Technical Field
The present invention relates to the field of system-on-chip, and in particular, to an interrupt handling function verification system and method.
Background
The interrupt controller is an important module of an SOC (System on Chip), and the interrupt sources of hardware interrupts, software interrupts and external interrupts must pass through the interrupt controller to be processed by the corresponding processor core in the SOC.
Verification of an interrupt controller first requires the generation of interrupt triggers, but some interrupt triggers take a long time to occur, and are even more difficult to occur. Therefore, a large amount of simulation time and hardware resources are wasted, and large-scale interrupt input is difficult to generate to verify the interrupt controller, so that the interrupt controller is not sufficiently verified, and the probability of missing errors in the verification process is increased.
In the existing verification method for simulating interrupt input, software is used for configuring a control register in an interrupt controller and inputting an interrupt source, the randomness of the configuration and the interrupt source is not guaranteed, the verification efficiency is low, and meanwhile, the reusability of the whole verification system is poor.
Disclosure of Invention
In view of the foregoing, embodiments of the present invention have been developed to provide an interrupt handling function validation system and method that overcome, or at least partially solve, the foregoing problems.
According to an aspect of an embodiment of the present invention, there is provided an interrupt handling function authentication system including:
a sequence generator for generating interrupt data, the interrupt data comprising a configuration value of an interrupt handler or an interrupt source;
the driver is used for converting the interrupt data into an interrupt input signal and sending the interrupt input signal to the interrupt processor;
an interrupt processor configured to configure the interrupt processor when the received interrupt input signal is a configuration value of the interrupt processor; when the received interrupt input signal is an interrupt source, performing interrupt processing on the interrupt source to generate an interrupt response and a reference response, and sending the interrupt response and the reference response to a score board;
and the score board is used for verifying the interrupt processing function by comparing the interrupt response with the reference response.
Optionally, the interrupt handler includes:
an interrupt controller, configured to configure a control register of the interrupt controller when the received interrupt input signal is a configuration value of an interrupt processor; when the received interrupt input signal is an interrupt source, performing interrupt processing on the interrupt source to generate an interrupt response;
an interrupt response monitor for monitoring the interrupt response generated by the interrupt controller and transmitting the interrupt response to a scoreboard;
and the interrupt responder is used for configuring a reference model of the interrupt controller when the received interrupt input signal is a configuration value of the interrupt processor, generating a reference response by performing interrupt processing on the interrupt source when the received interrupt input signal is an interrupt source, and transmitting the generated reference response to the score board.
Optionally, the interrupt responder is further configured to generate first bus protocol data and send the generated first bus protocol data to the scoreboard, where the first bus protocol data includes channel information of a write address channel and a write data channel of the interrupt controller;
the interrupt controller is further configured to generate second bus protocol data, where the second bus protocol data includes channel information of the write address channel and the write data channel;
the bus protocol monitor is used for monitoring the second bus protocol data generated by the interrupt controller and sending the second bus protocol data to the score board;
the scoreboard is further configured to verify an interrupt response output bus by comparing the first bus protocol data with the second bus protocol data.
Optionally, the driver communicates with the interrupt controller using a dedicated communication interface, and the interrupt response monitor communicates with the interrupt controller using a dedicated communication interface.
Optionally, the method further comprises:
and the coverage rate statistics device is used for sampling and analyzing the interrupt input signal output by the driver and the interrupt response output by the interrupt processor, and counting the coverage rate verified by the interrupt processing function.
Optionally, the verification System is built based on a UVM verification platform using a System Verilog hardware description language.
According to another aspect of the embodiment of the present invention, there is provided an interrupt processing function verification method, including:
generating interrupt data, wherein the interrupt data comprises a configuration value or an interrupt source of an interrupt processor;
converting the interrupt data into an interrupt input signal;
when the interrupt input signal is a configuration value of an interrupt processor, configuring the interrupt processor; when the interrupt input signal is an interrupt source, performing interrupt processing on the interrupt source to generate an interrupt response and a reference response;
and verifying an interrupt handling function by comparing the interrupt response with the reference response.
Optionally, the method further comprises:
when the interrupt input signal is a configuration value of an interrupt processor, respectively configuring an interrupt controller in the interrupt processor and a reference model of the interrupt controller;
when the interrupt input signal is an interrupt source, the interrupt controller performs interrupt processing on the interrupt source to generate the interrupt response, and a reference model of the interrupt controller performs interrupt processing on the interrupt source to generate the reference response.
Optionally, the method further comprises:
generating first bus protocol data, wherein the first bus protocol data comprises channel information of a write address channel and a write data channel of the interrupt controller;
generating second bus protocol data, wherein the second bus protocol data comprises the write address channel information and the channel information of a write data channel;
and validating an interrupt response output bus by comparing the first bus protocol data with the second bus protocol data.
Optionally, the verification method further includes:
and carrying out sampling analysis on the interrupt input signal and the interrupt response, and counting the coverage rate of the interrupt processing function verification.
According to another aspect of the embodiments of the present invention, there is provided a readable storage medium, which when executed by a processor of an electronic device, enables the electronic device to perform the interrupt processing function verification method as described above.
According to the embodiment of the invention, the UVM verification platform is applied to the verification of the interrupt controller of the multi-core processor, so that a hierarchical verification structure is realized. The System Verilog hardware description language is used for constructing a sequence generator and an interrupt processor with four distribution modes, the sequence generator can input a large number of random stimuli to the interrupt processor to be verified in a short time, the interrupt processor simultaneously generates an interrupt response and a reference response, and the scoreboard completes verification of an interrupt processing function by comparing the interrupt response of the interrupt processor with the reference response. The embodiment of the invention verifies that the environment has higher efficiency, stronger completeness, automation and reusability.
Furthermore, the verification system can also be simultaneously applied to the interrupt controller of the bridge chip and the interrupt controller of the universal multi-core chip, so that the verification system has more universality and portability.
The foregoing description is only an overview of the present invention, and is intended to be implemented in accordance with the teachings of the present invention in order that the same may be more clearly understood and to make the same and other objects, features and advantages of the present invention more readily apparent.
Drawings
Various other advantages and benefits will become apparent to those of ordinary skill in the art upon reading the following detailed description of the preferred embodiments. The drawings are only for purposes of illustrating the preferred embodiments and are not to be construed as limiting the invention. Also, like reference numerals are used to designate like parts throughout the figures. In the drawings:
FIG. 1 is one of the schematic diagrams of an interrupt handling function verification system according to a first embodiment of the present invention;
FIG. 2 is a second schematic diagram of an interrupt handling function verification system according to the first embodiment of the invention;
FIG. 3 is a schematic diagram of an interrupt handling function verification system according to a second embodiment of the invention;
FIG. 4 is a flowchart illustrating steps of an interrupt handling function verification method according to a third embodiment of the present invention;
fig. 5 is a flowchart illustrating steps of an interrupt handling function verification method according to a fourth embodiment of the present invention.
Detailed Description
Exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be embodied in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.
Example 1
Detailed description an interrupt handling function verification system provided by an embodiment of the present invention is described.
Referring to FIG. 1, a schematic diagram of an interrupt handling function verification system in an embodiment of the invention is shown. The system comprises:
a sequence generator 101 for generating interrupt data, the interrupt data comprising a configuration value or an interrupt source of the interrupt handler;
a driver 102 for converting the interrupt data into an interrupt input signal and transmitting the interrupt input signal to an interrupt processor;
an interrupt handler 103 for configuring the interrupt handler when the received interrupt input signal is a configuration value of the interrupt handler; when the received interrupt input signal is an interrupt source, performing interrupt processing on the interrupt source to generate an interrupt response and a reference response, and sending the interrupt response and the reference response to a score board;
In this embodiment, the verification System is built based on a UVM (Universal Verification Methodology ) verification platform using System Verilog hardware description language. The verification system comprises a sequence generator (sequence) 101, a driver (driver) 102, an interrupt handler 103, and a scoreboard (scoreboard) 104
The sequence generator 101 generates interrupt data containing configuration values write_valid, write_addr, write_data or interrupt source ioint of the interrupt processor 103. The sequence generator 101 may generate a plurality of interrupt data according to the interrupt processing function to be verified, which is not limited in detail in the embodiment of the present invention, and may be set according to actual situations.
The driver 102 receives interrupt data and converts the interrupt data into an interrupt input signal that can be input to the interrupt processor 103. Firstly, judging whether interrupt data is effective in the configuration value of an interrupt processor or the interrupt source according to the interrupt data write_valid, for example, when the write_valid is 1, the interrupt data is effective in the configuration value of the interrupt processor; when write_valid is 0, the interrupt data is the interrupt source valid. When the configuration values of the interrupt processors are valid, the configuration values write_valid, write_addr, and write_data of the interrupt processors are respectively generated into confbus according to the time sequence, and are driven to the interrupt processor 103. When the interrupt source is active, the interrupt source ioint is driven to the interrupt processor 103. After the driver 102 sends the configuration values of the interrupt handler, a plurality of interrupt sources may be continuously sent, which is not limited in detail in the embodiment of the present invention, and may be set according to practical situations.
The interrupt handler 103 configures the interrupt handler 103 when the received interrupt input signal is a configuration value of the interrupt handler, thereby setting an interrupt mode of each interrupt source and a distribution mode of each interrupt source. When the received interrupt input signal is an interrupt source, interrupt processing is carried out on the interrupt source according to an interrupt mode and a distribution mode of the interrupt source to generate an interrupt response and a reference response.
In a preferred embodiment of the present invention, referring to the interrupt handling function verification system shown in fig. 2, the interrupt handler 103 includes:
an interrupt controller 1031, configured to configure a control register 10311 of the interrupt controller 1031 when the received interrupt input signal is a configuration value of an interrupt processor; when the received interrupt input signal is an interrupt source, performing interrupt processing on the interrupt source to generate an interrupt response;
an interrupt response monitor 1032 for monitoring the interrupt response generated by the interrupt controller 1031 and transmitting the interrupt response to the scoreboard 104;
and an interrupt responder 1033, configured to configure a reference model of the interrupt controller 1031 when the received interrupt input signal is a configuration value of an interrupt processor, perform interrupt processing on the interrupt source to generate a reference response when the received interrupt input signal is an interrupt source, and send the generated reference response to the scoreboard 104.
In this embodiment, the interrupt controller 1031 is provided with a control register 10311, and the interrupt responder 1033 includes a reference model of the interrupt controller 1031.
When the received interrupt input signal is a configuration value of the interrupt processor, the interrupt controller 1031 configures the int_mask and the int_pol of the control register 10311, thereby setting an interrupt mode of each interrupt source; the bounce and auto of the control register 10311 are configured so as to set the distribution mode of each interrupt source. When the received interrupt input signal is an interrupt source, interrupt processing is carried out on the interrupt source according to an interrupt mode and a distribution mode of the interrupt source to generate an interrupt response.
The interrupt response monitor 1032 continuously monitors the output of the interrupt controller 1031 through an infinite loop, gathers interrupt responses core0_int, core1_int, core2_int, core3_int (for a quad-core processor), and sends the interrupt response to the scoreboard 104 through a write () command using uvm _analysis_port.
The interrupt responder 1033 configures the reference model when the received interrupt input signal is a configuration value for the interrupt handler. The driver 102 sends the same interrupt source to the interrupt controller 1031 and the interrupt responder 1033 in the interrupt processor 103, and when the interrupt controller 1031 performs interrupt processing on the interrupt source, the interrupt responder 1033 generates a reference response by performing standard interrupt processing on the interrupt source using the configured reference model, and sends the generated reference response to the scoreboard 104 through a write () command using uvm _analysis_port.
In a preferred embodiment of the present invention, the driver 102 communicates with the interrupt controller 1031 using a dedicated communication interface 105, and the interrupt response monitor 1032 communicates with the interrupt controller 1031 using a dedicated communication interface 105.
In this embodiment, the driver 102 communicates with the interrupt controller 1031 using a dedicated communication interface 105, and the interrupt response monitor 1032 communicates with the interrupt controller 1031 using the same dedicated communication interface (interface) that is driver-like. The communication signal includes: at least one of a clock signal (clk), a reset signal (reset), an interrupt source (ioint), a configuration value (conbus) of the interrupt processor, and an interrupt response (core0_int, core1_int, core2_int, core3_int) output by the interrupt controller (for a quad-core processor).
In a preferred embodiment of the present invention, and with reference to the interrupt handling function validation system shown in FIG. 2, the validation system further includes a sequencer 106.
In this embodiment, the sequencer 106 acquires interrupt data from the sequencer 101 and sends the interrupt data to the driver 102. When interrupt data is transmitted, the interrupt data may be transmitted in the order in which they were generated.
In summary, in the embodiment of the present invention, the UVM verification platform is applied to the verification of the interrupt controller of the multi-core processor, so as to implement a hierarchical verification structure. The System Verilog hardware description language is used for constructing a sequence generator and an interrupt processor with four distribution modes, the sequence generator can input a large number of random stimuli to the interrupt processor to be verified in a short time, the interrupt processor generates an interrupt response and a reference response, and the scoreboard completes interrupt processing function verification by comparing the interrupt response of the interrupt processor with the reference response. The embodiment of the invention verifies that the environment has higher efficiency, stronger completeness, automation and reusability.
Example two
Referring to FIG. 3, a schematic diagram of an interrupt handling function verification system in an embodiment of the invention is shown. This embodiment is based on the first embodiment.
The interrupt responder 1033 is further configured to generate first bus protocol data and send the generated first bus protocol data to the scoreboard 104, where the first bus protocol data includes channel information of a write address channel and a write data channel of the interrupt controller;
the interrupt controller 1031 is further configured to generate second bus protocol data, where the second bus protocol data includes channel information of the write address channel and the write data channel;
a bus protocol monitor 1034, configured to monitor the second bus protocol data generated by the interrupt controller 1031, and send the second bus protocol data to the scoreboard 104;
the scoreboard 104 is further configured to verify an interrupt response output bus by comparing the first bus protocol data with the second bus protocol data.
In this embodiment, when the interrupt controller 1031 is applied to the bridge, an interrupt response is output through the AXI (Advancede Xtensible Interface)) bus. AXI is a bus protocol, which is the most important part of the AMBA (Advanced Microcontroller Bus Architecture) 3.0 protocol proposed by ARM corporation, and is an on-chip bus for high performance, high bandwidth, and low latency.
The interrupt responder 1033 generates first bus protocol data based on a standard interrupt response. The interrupt controller 1031 generates second bus protocol data from data output from the write address channel (AW channel) and the write data channel (W channel) of the interrupt controller 1031. Interrupt responder 1033 sends first bus protocol data to scoreboard 104, bus protocol monitor 1034 communicates with interrupt controller 1031 using bus protocol communication interface (AXI reference) 107, monitors second bus protocol data generated by interrupt controller 1031, and sends second bus protocol data to scoreboard 104.
In a preferred embodiment of the present invention, the verification system further comprises:
and a coverage rate statistics unit 108 for sampling and analyzing the interrupt input signal output from the driver 102 and the first interrupt response output from the interrupt controller 1031, and counting the coverage rate of the functional verification of the interrupt controller 1031.
In summary, in the embodiment of the present invention, the verification system has higher efficiency, stronger completeness and reusability for the interrupt processing function verification of the interrupt controller, and the verification system can also be applied to both the interrupt controller of the bridge chip and the interrupt controller of the general multi-core processor, so that the verification system has more versatility and portability.
Example III
Detailed description is given of an interrupt handling function verification method provided by an embodiment of the present invention.
Referring to fig. 4, a flowchart illustrating steps of an interrupt handling function verification method in an embodiment of the present invention is applied to the interrupt handling function verification system described in the first to second embodiments, and the method includes:
in step 201, interrupt data is generated, wherein the interrupt data includes a configuration value of an interrupt handler or an interrupt source.
In this embodiment, the sequence generator 101 in the verification system generates interrupt data, where the interrupt data includes configuration values of the interrupt handler, such as write_valid, write_addr, write_data, or interrupt source ioint. The sequence generator 101 may randomly generate a large number of input stimuli in a short time based on the set membership variable constraints.
Optionally, the verification system may further include a sequencer 106, where the sequencer 106 obtains interrupt data generated by the sequence generator 101 and sends the interrupt data to the driver 102. When interrupt data is transmitted, the interrupt data may be transmitted in the order in which they were generated.
In this embodiment, after the driver 102 receives the interrupt data forwarded by the sequencer 106, it first determines whether the interrupt data is valid for the configuration value of the interrupt handler or for the interrupt source. For example, the interrupt data is valid as the configuration value of the interrupt processor when the write_valid is 1, and is valid as the interrupt source when the write_valid is 0.
When the interrupt data is valid as the configuration value of the interrupt handler, after the interrupt data converts the interrupt input signal, the interrupt input signal is the configuration value of the interrupt handler, and the driver 102 converts the configuration values write_valid, write_addr, write_data into conbus, and sends the conbus to the interrupt controller 1031 and the interrupt responder 1033 in the interrupt controller 103. Preferably, the driver 102 communicates with the interrupt controller 1031 using a dedicated communication interface 105. The communication signal includes: at least one of a clock signal (clk), a reset signal (reset), an interrupt source (ioint), and a configuration value (conbus) of an interrupt processor.
When the interrupt data is an interrupt source valid, the interrupt data converts the interrupt input signal, and then the interrupt input signal is an interrupt source, and the driver 102 transmits the interrupt source to the interrupt controller 1031 and simultaneously transmits the interrupt source to the interrupt responder 1033.
In the present embodiment, when the interrupt input signal is the configuration values write_valid, write_addr, write_data of the interrupt processor 103, the interrupt processor 103 is configured. The interrupt handler 103 includes an interrupt controller 1031, an interrupt response monitor 1032, and an interrupt response controller 1033. The interrupt controller 1031 is provided with a control register 10311, and the interrupt responder 1033 includes a reference model of the interrupt controller 1031.
Preferably, when the interrupt input signal is a configuration value of the interrupt processor 103, an interrupt controller 1031 in the interrupt processor 103 and a reference model of the interrupt controller 1031 are configured, respectively. Specifically, when the interrupt input signal received by the interrupt controller 1031 is a configuration value of the interrupt processor, the control register 10311 is configured to set the interrupt mode of each interrupt source and the distribution mode of each interrupt source. When the interrupt input signal received by the interrupt responder 1033 is a configuration value of the interrupt processor, a reference model of the interrupt controller 1031 is configured.
Preferably, when the interrupt input signal is an interrupt source, the interrupt controller 1031 performs interrupt processing on the interrupt source to generate the interrupt response, and the reference model of the interrupt controller 1031 performs interrupt processing on the interrupt source to generate the reference response. Specifically, when the interrupt input signal received by the interrupt controller 1031 is an interrupt source, interrupt processing is performed on the interrupt source, and an interrupt response is generated. Interrupt response monitor 1032 monitors interrupt responses generated by the interrupt controllers and sends interrupt responses to scoreboard 104. When the received interrupt input signal is an interrupt source, the interrupt responder 1033 performs standard interrupt processing on the interrupt source by using a reference model, generates a reference response, and transmits the reference response to the scoreboard 104.
In this embodiment, the scoreboard 104 compares the interrupt response with the reference response, and determines whether the interrupt processing of the interrupt controller 1031 is correct according to the comparison result, thereby verifying the interrupt processing function of the interrupt controller 1031. Specifically, the interrupt response matches the reference response, indicating that the interrupt handling by the interrupt controller 1031 is correct; an interrupt response that does not match the reference response indicates that the interrupt handling by interrupt controller 1031 is incorrect.
In summary, in the embodiment of the present invention, the UVM verification platform is applied to the verification of the interrupt controller of the multi-core processor, so as to implement a hierarchical verification structure. The System Verilog hardware description language is used for constructing a sequence generator and an interrupt processor with four distribution modes, the sequence generator can input a large number of random stimuli to the interrupt processor to be verified in a short time, the interrupt processor simultaneously generates an interrupt response and a reference response, and the scoreboard completes verification of an interrupt processing function by comparing the interrupt response of the interrupt processor with the reference response. The embodiment of the invention verifies that the environment has higher efficiency, stronger completeness, automation and reusability.
Example IV
Detailed description is given of an interrupt handling function verification method provided by an embodiment of the present invention.
Referring to fig. 5, a flowchart illustrating steps of an interrupt handling function verification method in an embodiment of the present invention is applied to the interrupt handling function verification system in the second embodiment, where the method includes:
in step 301, first bus protocol data is generated, where the first bus protocol data includes channel information of a write address channel and a write data channel of the interrupt controller.
In this embodiment, when the interrupt controller 1031 is applied to the bridge, an interrupt response is output through the AXI (Advancede Xtensible Interface)) bus. The authentication system in this embodiment further includes a bus protocol communication interface (AXI reference) 107 and a bus protocol monitor (AXI monitor) 1034; the bus protocol monitor 1034 connects a write address channel (AW channel) and a write data channel (W channel) of the interrupt controller 1031 through the bus protocol communication interface 107.
Interrupt responder 1033 generates first bus protocol data based on the standard interrupt response and sends the first bus protocol data to scoreboard 104.
In step 302, second bus protocol data is generated, where the second bus protocol data includes the write address channel information and channel information of a write data channel.
In this embodiment, the interrupt controller 1031 generates the second bus protocol data from the data output from the write address channel and the write data channel.
The bus protocol monitor 1034 monitors the second bus protocol data generated by the interrupt controller 1031 and transmits the second bus protocol data to the scoreboard 104.
In this embodiment, the scoreboard 104 receives the first bus protocol data and the second bus protocol data, compares the first bus protocol data with the second bus protocol data, and determines whether the interrupt response output bus is normal according to the comparison result, thereby verifying the interrupt response output bus. Specifically, the first bus protocol data and the second bus protocol data are matched, which indicates that the interrupt response output bus is normal; the first bus protocol data and the second bus protocol data do not match, indicating an interrupt response output bus exception.
In a preferred embodiment of the invention, a sampling analysis is performed on the interrupt input signal and the interrupt response, counting coverage of the interrupt handling function verification.
In this embodiment, for different interrupt sources, different interrupt handling manners, and different distribution modes, various interrupt handling functions of the interrupt controller 1031 may be verified. Specifically, the coverage rate of the function verification is calculated by defining the function coverage points in the function coverage group cov _group using assertion of assent and employing statistical coverage points.
In summary, in the embodiment of the present invention, the verification system has higher efficiency, stronger completeness and reusability for verifying the interrupt processing function of the interrupt controller. And the verification system can also simultaneously consider the interrupt controller applied to the bridge and the interrupt controller of the general multi-core processor, so that the verification system has more universality and portability.
It should be noted that, for simplicity of description, the foregoing method embodiments are all described as a series of acts, but it should be understood by those skilled in the art that the present invention is not limited by the order of acts described, as some steps may be performed in other orders or concurrently in accordance with the present invention. Further, those skilled in the art will appreciate that the embodiments described in the specification are presently preferred embodiments, and that the acts are not necessarily required for the present invention.
Example five
A readable storage medium provided by an embodiment of the present invention will be described in detail. The program in the storage medium, when executed by a processor of an electronic device, enables the electronic device to perform the interrupt processing function verification method as described in one or more of the third to fourth embodiments.
In this embodiment, a non-transitory computer readable storage medium, when executed by a processor of a terminal, causes the terminal to perform a method of launching an application, the method comprising:
generating interrupt data, wherein the interrupt data comprises a configuration value or an interrupt source of an interrupt processor;
converting the interrupt data into an interrupt input signal;
when the interrupt input signal is a configuration value of an interrupt processor, configuring the interrupt processor; when the interrupt input signal is an interrupt source, performing interrupt processing on the interrupt source to generate an interrupt response and a reference response;
and verifying an interrupt handling function by comparing the interrupt response with the reference response.
Optionally, the method further comprises:
when the interrupt input signal is a configuration value of an interrupt processor, respectively configuring an interrupt controller in the interrupt processor and a reference model of the interrupt controller;
when the interrupt input signal is an interrupt source, the interrupt controller performs interrupt processing on the interrupt source to generate the interrupt response, and a reference model of the interrupt controller performs interrupt processing on the interrupt source to generate the reference response.
Optionally, the method further comprises:
generating first bus protocol data, wherein the first bus protocol data comprises channel information of a write address channel and a write data channel of the interrupt controller;
generating second bus protocol data, wherein the second bus protocol data comprises the write address channel information and the channel information of a write data channel;
and validating an interrupt response output bus by comparing the first bus protocol data with the second bus protocol data.
Optionally, the verification method further includes:
and carrying out sampling analysis on the interrupt input signal and the interrupt response, and counting the coverage rate of the interrupt processing function verification.
In summary, in the embodiment of the present invention, the UVM verification platform is applied to the verification of the interrupt controller of the multi-core processor, so as to implement a hierarchical verification structure. The System Verilog hardware description language is used for constructing a sequence generator and an interrupt processor with four distribution modes, the sequence generator can input a large number of random stimuli to the interrupt processor to be verified in a short time, the interrupt processor simultaneously generates an interrupt response and a reference response, and the scoreboard completes verification of an interrupt processing function by comparing the interrupt response of the interrupt processor with the reference response. The embodiment of the invention verifies that the environment has higher efficiency, stronger completeness, automation and reusability.
In this specification, each embodiment is described in a progressive manner, and each embodiment is mainly described by differences from other embodiments, and identical and similar parts between the embodiments are all enough to be referred to each other.
As will be readily appreciated by those skilled in the art: any combination of the above embodiments is possible, and thus is an embodiment of the present invention, but the present specification is not limited by the text.
The interrupt handling function verification scheme provided herein is not inherently related to any particular computer, virtual system, or other apparatus. Various general-purpose systems may also be used with the teachings herein. The required structure for a system constructed with aspects of the present invention will be apparent from the description above. In addition, the present invention is not directed to any particular programming language. It will be appreciated that the teachings of the present invention described herein may be implemented in a variety of programming languages, and the above description of specific languages is provided for disclosure of enablement and best mode of the present invention.
In the description provided herein, numerous specific details are set forth. However, it is understood that embodiments of the invention may be practiced without these specific details. In some instances, well-known methods, structures and techniques have not been shown in detail in order not to obscure an understanding of this description.
Similarly, it should be appreciated that in the foregoing description of exemplary embodiments of the invention, various features of the invention are sometimes grouped together in a single embodiment, figure, or description thereof for the purpose of streamlining the disclosure and aiding in the understanding of one or more of the various inventive aspects. However, the disclosed method should not be construed as reflecting the intention that: i.e., the claimed invention requires more features than are expressly recited in each claim. Rather, as the following claims reflect, inventive aspects lie in less than all features of a single foregoing disclosed embodiment. Thus, the claims following the detailed description are hereby expressly incorporated into this detailed description, with each claim standing on its own as a separate embodiment of this invention.
Those skilled in the art will appreciate that the modules in the apparatus of the embodiments may be adaptively changed and disposed in one or more apparatuses different from the embodiments. The modules or units or components of the embodiments may be combined into one module or unit or component and, furthermore, they may be divided into a plurality of sub-modules or sub-units or sub-components. Any combination of all features disclosed in this specification (including any accompanying claims, abstract and drawings), and all of the processes or units of any method or apparatus so disclosed, may be used in combination, except insofar as at least some of such features and/or processes or units are mutually exclusive. Each feature disclosed in this specification (including any accompanying claims, abstract and drawings), may be replaced by alternative features serving the same, equivalent or similar purpose, unless expressly stated otherwise.
Furthermore, those skilled in the art will appreciate that while some embodiments described herein include some features but not others included in other embodiments, combinations of features of different embodiments are meant to be within the scope of the invention and form different embodiments. For example, in the claims, any of the claimed embodiments may be used in any combination.
Various component embodiments of the invention may be implemented in hardware, or in software modules running on one or more processors, or in a combination thereof. Those skilled in the art will appreciate that some or all of the functions of some or all of the components in an interrupt handling function verification scheme according to embodiments of the invention may be implemented in practice using a microprocessor or Digital Signal Processor (DSP). The present invention can also be implemented as an apparatus or device program (e.g., a computer program and a computer program product) for performing a portion or all of the methods described herein. Such a program embodying the present invention may be stored on a computer readable medium, or may have the form of one or more signals. Such signals may be downloaded from an internet website, provided on a carrier signal, or provided in any other form.
It should be noted that the above-mentioned embodiments illustrate rather than limit the invention, and that those skilled in the art will be able to design alternative embodiments without departing from the scope of the appended claims. In the claims, any reference signs placed between parentheses shall not be construed as limiting the claim. The word "comprising" does not exclude the presence of elements or steps not listed in a claim. The word "a" or "an" preceding an element does not exclude the presence of a plurality of such elements. The invention may be implemented by means of hardware comprising several distinct elements, and by means of a suitably programmed computer. In the unit claims enumerating several means, several of these means may be embodied by one and the same item of hardware. The use of the words first, second, third, etc. do not denote any order. These words may be interpreted as names.
Claims (8)
1. An interrupt handling function verification system, comprising:
a sequence generator for generating interrupt data, the interrupt data comprising a configuration value of an interrupt handler or an interrupt source;
the driver is used for converting the interrupt data into an interrupt input signal and sending the interrupt input signal to the interrupt processor;
an interrupt controller, configured to configure a control register of the interrupt controller when the received interrupt input signal is a configuration value of an interrupt processor, set an interrupt mode of each interrupt source, and configure the control register of the interrupt controller to set a distribution mode of each interrupt source; when the received interrupt input signal is the interrupt source, performing interrupt processing on the interrupt source according to an interrupt mode and a distribution mode of the interrupt source to generate an interrupt response, wherein the interrupt response is generated by setting four distribution modes for a four-core processor to perform interrupt processing and is at least one of core0_int, core1_int, core2_int and core3_int;
an interrupt response monitor for monitoring the interrupt response generated by the interrupt controller and transmitting the interrupt response to a scoreboard;
an interrupt responder, configured to configure a reference model of the interrupt controller when the received interrupt input signal is a configuration value of an interrupt processor; when the received interrupt input signal is an interrupt source, performing interrupt processing on the interrupt source to generate a reference response, and sending the generated reference response to a score board;
the scoring board is used for verifying an interrupt processing function by comparing the interrupt response with the reference response;
the verification System is built on the basis of a UVM verification platform by using a System Verilog hardware description language.
2. The authentication system of claim 1, wherein the authentication system comprises,
the interrupt responder is further configured to generate first bus protocol data and send the generated first bus protocol data to the scoreboard, where the first bus protocol data includes channel information of a write address channel and a write data channel of the interrupt controller;
the interrupt controller is further configured to generate second bus protocol data, where the second bus protocol data includes channel information of the write address channel and the write data channel;
the bus protocol monitor is used for monitoring the second bus protocol data generated by the interrupt controller and sending the second bus protocol data to the score board;
the scoreboard is further configured to verify an interrupt response output bus by comparing the first bus protocol data with the second bus protocol data.
3. The authentication system of claim 1 wherein the driver communicates with the interrupt controller using a dedicated communication interface and the interrupt response monitor communicates with the interrupt controller using a dedicated communication interface.
4. The authentication system of claim 1, further comprising:
and the coverage rate statistics device is used for sampling and analyzing the interrupt input signal output by the driver and the interrupt response output by the interrupt processor, and counting the coverage rate verified by the interrupt processing function.
5. An interrupt handling function verification method, the method comprising:
generating interrupt data, wherein the interrupt data comprises a configuration value or an interrupt source of an interrupt processor;
converting the interrupt data into an interrupt input signal;
when the received interrupt input signal is a configuration value of an interrupt processor, configuring a control register of an interrupt controller, setting an interrupt mode of each interrupt source, configuring the control register of the interrupt controller, and setting a distribution mode of each interrupt source; when the received interrupt input signal is the interrupt source, performing interrupt processing on the interrupt source according to an interrupt mode and a distribution mode of the interrupt source to generate an interrupt response, wherein the interrupt response is generated by setting four distribution modes for a four-core processor to perform interrupt processing and is at least one of core0_int, core1_int, core2_int and core3_int;
monitoring the interrupt response generated by the interrupt controller and sending the interrupt response to a score board;
when the received interrupt input signal is a configuration value of an interrupt processor, configuring a reference model of the interrupt controller; when the received interrupt input signal is an interrupt source, performing interrupt processing on the interrupt source to generate a reference response, and sending the generated reference response to a score board;
verifying an interrupt handling function by comparing the interrupt response to the reference response;
the method is applied to an interrupt processing function verification System, and the verification System is built on the basis of a UVM verification platform by using a System Verilog hardware description language.
6. The authentication method of claim 5, further comprising:
generating first bus protocol data, wherein the first bus protocol data comprises channel information of a write address channel and a write data channel of the interrupt controller;
generating second bus protocol data, wherein the second bus protocol data comprises the write address channel information and the channel information of a write data channel;
and validating an interrupt response output bus by comparing the first bus protocol data with the second bus protocol data.
7. The authentication method of claim 5, further comprising:
and carrying out sampling analysis on the interrupt input signal and the interrupt response, and counting the coverage rate of the interrupt processing function verification.
8. A readable storage medium, characterized in that a program in the storage medium, when executed by a processor of an electronic device, enables the electronic device to perform the interrupt handling function verification method according to one or more of the method claims 5-7.
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| CN113032305B (en) * | 2021-03-12 | 2023-07-04 | 飞腾信息技术有限公司 | Interface interrupt measurement method and device |
| CN114328065A (en) * | 2021-12-29 | 2022-04-12 | 北京爱芯科技有限公司 | Interrupt verification method and device and electronic equipment |
| CN117472673B (en) * | 2023-12-27 | 2024-03-26 | 睿思芯科(成都)科技有限公司 | Automatic test method, system and related equipment for interrupt controller |
| CN119356955B (en) * | 2024-08-28 | 2025-10-28 | 山东云海国创云计算装备产业创新中心有限公司 | Fully random testing method, device, equipment, medium and product for SGPIO master module |
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