CN108736860A - Container equivalent-circuit model is recalled in a kind of lotus control - Google Patents
Container equivalent-circuit model is recalled in a kind of lotus control Download PDFInfo
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Abstract
本发明公开了一种荷控忆容器等效电路模型。该电路模型利用运算放大器和乘法器等器件构建了满足忆容器特性的电路模型，可应用于忆容器基础电路特性的研究，以及忆容器非线性电路的研究。根据忆容器的数学定义式设计了忆容器二端口模拟电路模型，运算放大器U1用于实现了积分器功能、反相器功能、加法器功能，U2、U3、U4是实现信号相乘的功能。当输入正弦电流激励信号时，可以用示波器观察其特性，输出的电压信号与电荷信号的电压值之间满足紧致滞回曲线特性，且随信号频率的增加，其滞回旁瓣面积减小。该电路结构清晰，易于分析测量，可进行忆容器在基础电路中特性的研究，以及在非线性电路中的应用。
The invention discloses an equivalent circuit model of a charge-controlled memory capacitor. The circuit model uses operational amplifiers, multipliers and other devices to construct a circuit model that satisfies the characteristics of memcapacitors, which can be applied to the research of basic circuit characteristics of memcapacitors and the study of memcapacitor nonlinear circuits. According to the mathematical definition of the memory container A memcapacitor two-port analog circuit model is designed. Operational amplifier U1 is used to realize the functions of integrator, inverter and adder. U2, U3 and U4 are used to realize signal multiplication. When the sinusoidal current excitation signal is input, its characteristics can be observed with an oscilloscope. The output voltage signal and the voltage value of the charge signal meet the characteristics of a tight hysteresis curve, and as the signal frequency increases, the hysteresis sidelobe area decreases. . The circuit has a clear structure, is easy to analyze and measure, and can carry out the research on the characteristics of the memcapacitor in the basic circuit and the application in the nonlinear circuit.
Description
技术领域technical field
本发明属于电路设计技术领域，涉及一种荷控忆容器等效电路模型，特别涉及一种二端口网络的忆容器模拟电路模型，满足输出的电压信号与电荷信号之间的紧致滞回曲线特性。The invention belongs to the technical field of circuit design, and relates to a load-controlled memcapacitor equivalent circuit model, in particular to a two-port network memcapacitor analog circuit model, which satisfies the compact hysteresis curve between the output voltage signal and the charge signal characteristic.
背景技术Background technique
忆容器(或称记忆电容器)是继忆阻器之后的一类具有特殊记忆特性的非线性电路元器件。与忆阻器类似，此类记忆器件不需要外加电源就有记忆信息的功能。忆容器具有独特的记忆和动态存储能力等特性，可应用于微电子、神经网络以及非易失性存储等领域。忆容器是表征电荷与电压之间关系的记忆器件，其当前状态依赖于其系统的过去状态，且其状态在断电之后可以进行保持，其基本特性就是电压信号与电荷信号的关系相图为紧致滞回曲线。相对忆阻器而言，忆容器的研究还比较少，还未出现真实的忆容器器件，目前，仍然处于对其建模的研究，其数学模型和电路模型还不够完善。因此，提出新的忆容器数学模型和等效电路，并用其电路模型代替实际的忆容器件用于电路的实验研究与应用电路的设计中。Memcapacitors (or memcapacitors) are a class of non-linear circuit components with special memory characteristics after memristors. Similar to memristors, this type of memory device has the function of storing information without external power supply. Memcapacitors have unique characteristics such as memory and dynamic storage capabilities, and can be applied in the fields of microelectronics, neural networks, and non-volatile storage. A memcapacitor is a memory device that represents the relationship between charge and voltage. Its current state depends on the past state of its system, and its state can be maintained after power-off. Its basic characteristic is that the phase diagram of the relationship between the voltage signal and the charge signal is Tight hysteresis curve. Compared with memristors, the research on memcapacitors is still relatively small, and no real memcapacitor devices have appeared yet. At present, the research on its modeling is still in progress, and its mathematical model and circuit model are not perfect enough. Therefore, a new memcapacitor mathematical model and equivalent circuit are proposed, and its circuit model is used to replace the actual memcapacitor device for the experimental research of the circuit and the design of the application circuit.
目前，虽已报导了少量忆容器的数学模型，但大多数模型都只停留在理论分析与仿真验证，而很少由硬件电路构成的等效电路，有的模型较复杂，导致实际应用中难以实现；有的误差较大，难以精确模拟实际忆容器的特性。因此，设计一种更符合其特性的数学模型和对应的等效电路模型，对于增加忆容器模型的类型和未来实现实际的忆容器具有重要意义。At present, although a small number of mathematical models of memcapacitors have been reported, most of the models only stay in theoretical analysis and simulation verification, and there are few equivalent circuits composed of hardware circuits. Realization; some errors are large, and it is difficult to accurately simulate the characteristics of the actual memory container. Therefore, designing a mathematical model and corresponding equivalent circuit model that is more suitable for its characteristics is of great significance for increasing the types of memcapacitor models and realizing actual memcapacitors in the future.
发明内容Contents of the invention
针对现有技术存在的上述不足，本发明提出了一种新的忆容器数学模型和等效电路模型，用以模拟忆容器的电压-电荷特性，替代实际忆容器进行电路设计和应用。Aiming at the above-mentioned deficiencies in the prior art, the present invention proposes a new memcapacitor mathematical model and equivalent circuit model to simulate the voltage-charge characteristics of the memcapacitor and replace the actual memcapacitor for circuit design and application.
本发明解决技术问题所采取的技术方案如下：依据一种新的荷控忆容器数学模型u(t)＝(α+βδ(t)+γδ(t)2)q(t)，其中u(t)和q(t)为忆容器的电压与电荷。设计的忆容器等效电路模型，它包括积分运算、反相比例运算、乘法运算、加法运算电路。其中集成运算放大器U1用于实现积分运算、反相比例运算和加法运算，集成芯片U2、U3、U4用于实现乘法运算，最终通过加法器得到想要的忆容器电压量。The technical scheme adopted by the present invention to solve the technical problem is as follows: according to a new mathematical model u(t)=(α+βδ(t)+γδ(t) 2 )q(t), where u( t) and q(t) are the voltage and charge of the memcapacitor. The designed memcapacitor equivalent circuit model includes integral operation, inverse proportional operation, multiplication operation and addition operation circuit. Among them, the integrated operational amplifier U1 is used to realize the integral operation, the inverse proportional operation and the addition operation, and the integrated chips U2, U3, and U4 are used to realize the multiplication operation, and finally the desired memcapacitor voltage is obtained through the adder.
所述的集成运算放大器U1采用LF347BF；乘法器U2、U3、U4采用AD633JN。The integrated operational amplifier U1 adopts LF347BF; the multipliers U2, U3 and U4 adopt AD633JN.
所述的集成运算放大器U1的第1引脚与第一电容C1的一端、第二电阻R2的一端、第三电阻R3的一端、第五电阻R5的一端连接，第2引脚与第一电阻R1的一端、第一电容C1的另一端、第二电阻R2的另一端连接，第3、6引脚接地，第4引脚接电源VCC，第5引脚与第六电阻R6的一端、第五电阻R5的另一端连接，第7引脚与第九电阻R9的一端、乘法器U3和U4的第3引脚连接，第8引脚与第十电阻R10的一端连接、并作为最终的电压输出端口，第9引脚与第十电阻R10的另一端、第九电阻R9的另一端、第七电阻R7的另一端、第八电阻R8的一端连接，第10、12引脚接地，第11引脚接电源VEE，第13引脚与第三电阻R3的另一端、第二电容C2的一端、第四电阻R4的一端连接，第14引脚与乘法器U2的第1引脚连接。The first pin of the integrated operational amplifier U1 is connected to one end of the first capacitor C1, one end of the second resistor R2, one end of the third resistor R3, and one end of the fifth resistor R5, and the second pin is connected to the first end of the first resistor One end of R1, the other end of the first capacitor C1, and the other end of the second resistor R2 are connected, the 3rd and 6th pins are grounded, the 4th pin is connected to the power supply VCC, the 5th pin is connected to one end of the sixth resistor R6, the The other end of the fifth resistor R5 is connected, the seventh pin is connected to one end of the ninth resistor R9, the third pin of the multipliers U3 and U4, the eighth pin is connected to one end of the tenth resistor R10, and used as the final voltage Output port, the 9th pin is connected to the other end of the tenth resistor R10, the other end of the ninth resistor R9, the other end of the seventh resistor R7, and one end of the eighth resistor R8, the 10th and 12th pins are grounded, the 11th The pin is connected to the power supply VEE, the 13th pin is connected to the other end of the third resistor R3, one end of the second capacitor C2, and one end of the fourth resistor R4, and the 14th pin is connected to the first pin of the multiplier U2.
所述的乘法器U2的第1引脚与电容C2的另一端、第四电阻R4的另一端连接，第2、4、6引脚接地，第3引脚与电容C2的另一端、第四电阻R4的另一端、乘法器U3的第1引脚连接，第5引脚接电源VEE，第7引脚与乘法器U4第1引脚连接，第8引脚接电源VCC。The first pin of the multiplier U2 is connected to the other end of the capacitor C2 and the other end of the fourth resistor R4, the second, fourth, and sixth pins are grounded, the third pin is connected to the other end of the capacitor C2, the fourth The other end of the resistor R4 is connected to the first pin of the multiplier U3, the fifth pin is connected to the power supply VEE, the seventh pin is connected to the first pin of the multiplier U4, and the eighth pin is connected to the power supply VCC.
所述乘法器U3的第3引脚与第九电阻R9的一端、乘法器U4的第3引脚连接，第2、4、6引脚接地，第5引脚接电源VEE，第7引脚与第八电阻R8的另一端连接，第8引脚接电源VCC。The third pin of the multiplier U3 is connected to one end of the ninth resistor R9 and the third pin of the multiplier U4, the second, fourth, and sixth pins are grounded, the fifth pin is connected to the power supply VEE, and the seventh pin It is connected to the other end of the eighth resistor R8, and the eighth pin is connected to the power supply VCC.
所述乘法器U4的第2、4、6引脚接地，第3引脚与第九电阻R9的一端连接，第5引脚接电源VEE，第7引脚与第七电阻R7的另一端连接，第8引脚接电源VCC。The 2nd, 4th, and 6th pins of the multiplier U4 are grounded, the 3rd pin is connected to one end of the ninth resistor R9, the 5th pin is connected to the power supply VEE, and the 7th pin is connected to the other end of the seventh resistor R7 , the 8th pin is connected to the power supply VCC.
本发明构造了一个二端口荷控忆容器电路模型。该电路模型利用运算放大器和乘法器等器件构建了满足忆容器特性的电路模型，可应用于忆容器基础电路特性的研究，以及忆容器非线性电路的研究。根据忆容器的数学定义式u(t)＝(α+βδ+γδ2)q(t)设计了忆容器二端口模拟电路模型，运算放大器U1用于实现了积分器功能、反相器功能、加法器功能，U2、U3、U4是实现信号相乘的功能。当输入正弦电流激励信号时，可以用示波器观察其特性，输出的电压信号与电荷信号的电压值之间满足紧致滞回曲线特性，且随信号频率的增加，其滞回旁瓣面积减小。该电路结构清晰，易于分析测量，可进行忆容器在基础电路中特性的研究，以及在非线性电路中的应用。The invention constructs a two-port charge-controlled memcapacitor circuit model. The circuit model uses operational amplifiers, multipliers and other devices to construct a circuit model that satisfies the characteristics of memcapacitors, which can be applied to the research of basic circuit characteristics of memcapacitors and the study of memcapacitor nonlinear circuits. According to the mathematical definition of memcapacitor u(t)=(α+βδ+γδ 2 )q(t), a two-port analog circuit model of memcapacitor is designed. Operational amplifier U1 is used to realize the function of integrator, inverter, Adder function, U2, U3, U4 are the functions to realize signal multiplication. When the sinusoidal current excitation signal is input, its characteristics can be observed with an oscilloscope. The output voltage signal and the voltage value of the charge signal meet the characteristics of a tight hysteresis curve, and as the signal frequency increases, the hysteresis sidelobe area decreases. . The circuit has a clear structure, is easy to analyze and measure, and can carry out the research on the characteristics of the memcapacitor in the basic circuit and the application in the nonlinear circuit.
附图说明Description of drawings
图1是本发明的结构图。Fig. 1 is a structural diagram of the present invention.
图2是本发明的原理图。Figure 2 is a schematic diagram of the present invention.
具体实施方式Detailed ways
下面结合附图1和优选实例对本发明作更进一步的详细说明。Below in conjunction with accompanying drawing 1 and preferred example the present invention is described in further detail.
本发明设计的荷控忆容器数学模型为The load-controlled memory container mathematical model designed by the present invention is
u(t)＝(α+βδ(t)+γδ(t)2)q(t)u(t)=(α+βδ(t)+γδ(t) 2 )q(t)
u(t)和q(t)为忆容器的电压与电荷，其中α、β、γ为常量，是可变量，本模型试验选择为α＝0.2，β＝0.04，γ＝0.07能够获得良好紧磁滞回曲线特性。u(t) and q(t) are the voltage and charge of the memcapacitor, Among them, α, β, and γ are constants and variable variables. In this model test, α = 0.2, β = 0.04, and γ = 0.07 are selected to obtain good tight hysteresis curve characteristics.
如图2所示，集成运算放大器U1内集成了4个运算放大器，其中第1、2、3引脚对应的运算放大器与第一电阻R1、第二电阻R2以及第一电容C1构成积分电路，用来获得忆容器的电荷量，输入的电流i(t)通过第一电阻R1输入到集成运算放大器U1的第2引脚，U1引脚的电荷量为q1(t)：As shown in Figure 2, four operational amplifiers are integrated in the integrated operational amplifier U1, where the operational amplifiers corresponding to pins 1, 2, and 3 form an integrating circuit with the first resistor R1, the second resistor R2, and the first capacitor C1. To obtain the amount of charge of the memcapacitor, the input current i(t) is input to the second pin of the integrated operational amplifier U1 through the first resistor R1, and the charge amount of the U1 pin is q 1 (t):
集成运算放大器U1的第5、6、7引脚对应的运算放大器，与外围第五电阻R5、第六电阻R6构成反相运算放大器，用于实现输入电荷q(t)的反相增益，从而得到正向的电荷量，U1引脚7的电荷为q2(t)：The operational amplifiers corresponding to pins 5, 6, and 7 of the integrated operational amplifier U1 form an inverting operational amplifier with the peripheral fifth resistor R5 and sixth resistor R6 to realize the inverting gain of the input charge q(t), thereby To get the amount of positive charge, the charge on pin 7 of U1 is q 2 (t):
集成运算放大器U1的第12、13、14引脚与外围第三电阻R3、第四电阻R4、第二电容C2构成积分运算电路，用于实现对U1输出的电荷再次积分，从而可以得到中间变量δ(t)：The 12th, 13th, and 14th pins of the integrated operational amplifier U1, the peripheral third resistor R3, the fourth resistor R4, and the second capacitor C2 form an integral operation circuit, which is used to integrate the charge output by U1 again, so that an intermediate variable can be obtained δ(t):
乘法器U2的第1、3引脚与集成运算放大器的第14引脚相连，第2、4、6引脚接地，第八引脚接VCC，第五引脚接VEE。这第七引脚为输出端，其输出的信号为：δ2(t)；同理乘法器U3和U4分别输出的是q(t)δ(t)和q(t)δ2(t)。The 1st and 3rd pins of the multiplier U2 are connected to the 14th pin of the integrated operational amplifier, the 2nd, 4th, and 6th pins are grounded, the eighth pin is connected to VCC, and the fifth pin is connected to VEE. The seventh pin is the output terminal, and the output signal is: δ 2 (t); similarly, the multipliers U3 and U4 respectively output q(t)δ(t) and q(t)δ 2 (t) .
最终由集成运算放大器U1的第8、9、10引脚与第十电阻R10、第七电阻R7、第八电阻R8、第九电阻R9构成加法运算电路，用于实现对信号的叠加。从而可得输出电压u(t)：Finally, the 8th, 9th, and 10th pins of the integrated operational amplifier U1 and the 10th resistor R10, the 7th resistor R7, the 8th resistor R8, and the 9th resistor R9 form an addition operation circuit for superimposing signals. Thus the output voltage u(t) can be obtained:
集成电路U1选用LF347BF集成运算放大器，所述集成运算放大器U1的第1引脚通过电阻R2连接到U1的第2引脚，通过电阻R3连接到U1的第13引脚，通过电阻R5连接到U1的第5引脚，通过电阻R5和电阻R6连接到U1的第7引脚。第2引脚通过电阻R1与输入电流源相连接，通过电阻R2和电阻R3连接到U1的第14引脚。第3引脚接地。第4引脚接电源VCC。第5引脚通过电阻R6与U1的第9引脚以及U3的第3引脚相连接。第6引脚接地。第7引脚与U3的第3引脚相连接，并通过电阻R9与U1的第9引脚相连接。第8引脚为最终输出电压端。第9引脚通过电阻R10与第8引脚相连接。第10引脚接地。第11引脚接电源VEE。第12引脚接地。第13引脚通过电阻R4分别与U2的第1引脚、第3引脚，U3的第一引脚相连接。第14引脚与U2的第1引脚相连接。The integrated circuit U1 selects the LF347BF integrated operational amplifier, the first pin of the integrated operational amplifier U1 is connected to the second pin of U1 through the resistor R2, connected to the 13th pin of U1 through the resistor R3, and connected to the U1 through the resistor R5 The 5th pin of U1 is connected to the 7th pin of U1 through resistor R5 and resistor R6. The second pin is connected to the input current source through the resistor R1, and connected to the 14th pin of U1 through the resistor R2 and the resistor R3. Pin 3 is grounded. The 4th pin is connected to the power supply VCC. The fifth pin is connected to the ninth pin of U1 and the third pin of U3 through the resistor R6. Pin 6 is grounded. The 7th pin is connected with the 3rd pin of U3, and is connected with the 9th pin of U1 through the resistor R9. The 8th pin is the final output voltage terminal. The ninth pin is connected with the eighth pin through the resistor R10. Pin 10 is grounded. The 11th pin is connected to the power supply VEE. Pin 12 is grounded. The thirteenth pin is respectively connected to the first pin, the third pin of U2, and the first pin of U3 through the resistor R4. The 14th pin is connected with the 1st pin of U2.
集成电路U2选用AD633JN乘法器，所述乘法器U2的第2引脚、第4引脚、第6引脚接地。第5引脚接电源VEE。第8引脚接电源VCC。第7引脚与U4的第1引脚相连接。The integrated circuit U2 is an AD633JN multiplier, and the second pin, the fourth pin, and the sixth pin of the multiplier U2 are grounded. The fifth pin is connected to the power supply VEE. The 8th pin is connected to the power supply VCC. Pin 7 is connected to pin 1 of U4.
集成电路U3选用AD633JN乘法器，所述乘法器U3的第2引脚、第4引脚、第6引脚接地。第5引脚接电源VEE。第8引脚接电源VCC。第3引脚与U4的第3引脚相连接。第7引脚通过电阻R8与U1的第9引脚相连接。The integrated circuit U3 is an AD633JN multiplier, and the second pin, the fourth pin, and the sixth pin of the multiplier U3 are grounded. The fifth pin is connected to the power supply VEE. The 8th pin is connected to the power supply VCC. The 3rd pin is connected with the 3rd pin of U4. The seventh pin is connected to the ninth pin of U1 through the resistor R8.
集成电路U4选用AD633JN乘法器，所述乘法器U4的第2引脚、第4引脚、第6引脚接地。第5引脚接电源VEE。第8引脚接电源VCC。第3引脚与U1的第7引脚相连接。第7引脚通过电阻R7与U1的第9引脚相连接。The integrated circuit U4 is an AD633JN multiplier, and the second pin, the fourth pin, and the sixth pin of the multiplier U4 are grounded. The fifth pin is connected to the power supply VEE. The 8th pin is connected to the power supply VCC. The 3rd pin is connected with the 7th pin of U1. The seventh pin is connected to the ninth pin of U1 through the resistor R7.
当然，上述说明并非对发明的限制，本发明也不仅限于上述举例，本技术领域的普通技术人员在本发明的实质范围内所做出的变化、改型、添加或替换，也属于本发明的保护范围。Of course, the above description is not a limitation to the invention, and the present invention is not limited to the above examples, and the changes, modifications, additions or replacements made by those skilled in the art within the scope of the present invention also belong to the scope of the present invention. protected range.
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