CN108550624A - A kind of high heat dispersion double grid gallium oxide field-effect thin film transistor (TFT) and preparation method thereof - Google Patents

Abstract

The invention relates to a double-gate gallium oxide field-effect thin film transistor with high heat dissipation performance and a preparation method thereof, comprising a substrate, a bottom gate electrode, a bottom gate dielectric layer, a gallium oxide channel layer, a top gate dielectric layer, a top gate electrode, a source electrode, drain electrode. Among them, the gallium oxide channel layer is transferred to the substrate by tape stripping technology, the thickness is very thin, the thermal resistance is small, the heat dissipation effect is good, and the transistor has a double-gate structure, and the gate electrode is enhanced by the double-gate structure. Control ability, improve the pinch-off characteristics of the device, the thermal resistance of the transistor is greatly reduced, and the heat dissipation performance is high. Improve device pinch-off characteristics.

Description

A high heat dissipation performance double-gate gallium oxide field-effect thin film transistor and its preparation method

technical field

The invention relates to a double-gate gallium oxide field-effect thin film transistor with high heat dissipation performance and a preparation method thereof, belonging to the technical field of semiconductor power devices.

Background technique

Gallium oxide is a new type of semiconductor material with direct band gap and wide bandgap. It has the advantages of large band gap and high breakdown electric field. Field effect transistors based on gallium oxide materials have the advantages of high withstand voltage, low loss, and radiation resistance. The field of high-voltage and high-power devices, especially in the fields of power conversion, electric vehicles, and photovoltaic systems, has broad application prospects. However, the thermal conductivity of the gallium oxide material is very low, and the field effect transistor device prepared on the gallium oxide substrate has a large thermal resistance, resulting in a high junction temperature of the device, which seriously affects the performance of the transistor device. In addition, conventional gallium oxide transistors are depletion-type and require a large negative voltage to turn off.

Chinese patent document CN107742647A provides a gallium oxide field effect transistor. The gallium oxide field effect transistor includes: a substrate, a gallium oxide channel layer, a source, a drain, and a gate, the upper surface of the substrate is the gallium oxide channel layer, and the two sides of the gallium oxide channel layer They are the source and the drain respectively, the middle part of the gallium oxide channel layer is the gate, and the gate completely surrounds the gallium oxide channel layer. In the present invention, when the current density is increased by increasing the thickness of the gallium oxide channel layer, the gate is designed to completely surround the gallium oxide channel layer, so that the gate control will not be deteriorated, and good gate control can be obtained; The method increases the current density by increasing the thickness of the gallium oxide channel layer, the greater the thickness of the gallium oxide channel layer, the greater the thermal resistance and the greater the heat dissipation performance.

Contents of the invention

Aiming at the deficiencies of the prior art, the present invention provides a double-gate Gallium Oxide Field-Effect Thin Film Transistor with high heat dissipation performance and a preparation method thereof. The transistor of the present invention has a double-gate structure, and the control of the gate electrode to carriers is enhanced through the double-gate structure. ability, improve the pinch-off characteristics of the device, the thermal resistance of the transistor is greatly reduced, and the heat dissipation performance is high.

The present invention is achieved through the following technical solutions:

A double-gate gallium oxide field-effect thin film transistor with high heat dissipation performance, including a substrate, a gate electrode, a source electrode and a drain electrode, is characterized in that a bottom gate dielectric layer and a gallium oxide channel layer are sequentially arranged on the substrate from bottom to top A source electrode and a drain electrode are arranged on the gallium oxide channel layer, and the upper surface of the gallium oxide channel layer between the source electrode and the drain electrode is covered with a top gate dielectric layer.

Preferably according to the present invention, the gate electrode includes a bottom gate electrode and a top gate electrode, the bottom gate electrode is located at the bottom of the substrate or between the substrate and the bottom gate dielectric; the top gate electrode is located on the top gate dielectric layer.

Preferably according to the present invention, the substrate is one of silicon carbide, diamond, silicon or copper.

Preferably according to the present invention, the bottom gate electrode is a Ti/Au/Ti three-layer alloy, the thickness of Ti is 10-500 nm, and the thickness of Au is 50-1000 nm.

Preferably according to the present invention, the thickness of the bottom gate dielectric layer is 10-100 nm, and the bottom gate dielectric layer is silicon oxide, aluminum oxide or hafnium oxide.

Preferably, according to the present invention, the gallium oxide channel layer uses a gallium oxide film as the channel layer, the gallium oxide film has a thickness of 50-500 nm, is N-type doped gallium oxide, and has a doping concentration of 5×10 ¹⁶ cm ^{- 3} -5×10 ¹⁸ cm ^-3

Preferably according to the present invention, the thickness of the top gate dielectric layer is 10-100 nm, and the top gate dielectric layer is silicon oxide, aluminum oxide or hafnium oxide.

Preferably according to the present invention, the top gate electrode is a Pd/Au alloy, the thickness of Pd is 10-500nm, and the thickness of Au is 50-1000nm.

Preferably according to the present invention, the source electrode is a Ti/Au alloy, the thickness of Ti is 10-500nm, and the thickness of Au is 50-1000nm.

Preferably according to the present invention, the drain electrode is a Ti/Au alloy, the thickness of Ti is 10-500 nm, and the thickness of Au is 50-1000 nm.

According to the present invention, a method for preparing a double-gate Gallium Oxide Field Effect Thin Film Transistor comprises the following steps:

(1) Substrate cleaning step;

(2) Bottom gate electrode layer is evaporated on the bottom or top of the substrate;

(3) The surface of the sample obtained in step (2) is deposited with a bottom gate dielectric layer by atomic layer deposition;

(4) Tear off the gallium oxide film from the gallium oxide crystal and transfer it to the sample in step (3);

(5) remove transfer, then clean;

(6) Atom deposition of the top gate dielectric layer on the cleaned sample;

(7) Etching and removing the top gate dielectric layer at both ends to form a source region and a drain region,

(8) Covering the upper surface of the source region and the drain region with a Ti/Au alloy to form a source electrode and a drain electrode respectively;

(9) the sample annealing that step (8) obtains;

(10) After annealing, cover the upper surface of the top gate dielectric layer with Pd/Au alloy to form a top gate electrode.

Preferably according to the present invention, in step (1), the substrate cleaning step is: cleaning the substrate with acetone, ethanol, and deionized water for 4-8 minutes in sequence, and then drying it with nitrogen.

Preferably according to the present invention, in step (4), tearing off the gallium oxide film from the gallium oxide crystal is as follows: stick the adhesive tape on the gallium oxide crystal, and then tear it off quickly, the surface film of the gallium oxide crystal is stuck on the adhesive tape, The thickness of the gallium oxide film on the adhesive tape is 50-500nm.

Preferably according to the present invention, in step (5), removing the transferred substance is to place the sample in 4-methylisobutyl ketone, heat to 75-85°C, soak for 20 minutes, and remove the adhesive tape.

Preferably according to the present invention, the cleaning in step (5) is to wash the sample with acetone, ethanol, and deionized water for 4-8 minutes in sequence, and then blow dry with nitrogen.

Preferably according to the present invention, step (7) removes part of the top gate dielectric layer by photoetching and inductively coupled plasma etching.

Preferably according to the present invention, the annealing temperature in step (9) is 400-500° C., and the annealing time is 60 seconds.

The evaporation of the bottom gate electrode layer is carried out in an evaporation apparatus, and the atomic layer deposition method, photoetching and inductively coupled plasma etching are all carried out according to the prior art.

Beneficial effects of the present invention

Aiming at the problems of low thermal conductivity of gallium oxide materials, poor heat dissipation performance, and high pinch-off voltage of field effect transistors based on gallium oxide materials, the present invention proposes a gallium oxide-based thin film field effect transistor with a double-gate structure and a preparation method thereof. Bottom-gate electrodes and bottom-gate dielectrics were prepared on a substrate with high thermal conductivity, and the gallium oxide film was peeled off from the single crystal with adhesive tape, transferred to the substrate, and then top-gate dielectrics, source-drain electrodes, and gate electrodes were prepared to obtain a Gallium oxide thin-film field-effect transistors with double-gate and bottom-gate structures. First of all, the thickness of the gallium oxide peeled off with adhesive tape is very thin, only about 100nm, and the thermal resistance is significantly lower than that of traditional gallium oxide-based field effect transistor devices; in addition, the gallium oxide film is transferred to a substrate with high thermal conductivity, which can effectively improve the performance of the device. Heat dissipation performance; in addition, the double gate structure of the top gate and the bottom gate can be used to enhance the control ability of the gate electrode to the carriers and improve the pinch-off characteristics of the device.

Description of drawings

FIG. 1 is a schematic structural diagram of a double-gate gallium oxide field-effect thin film transistor according to Embodiment 1 of the present invention;

2 is a schematic structural diagram of a double-gate gallium oxide field-effect thin film transistor according to Embodiment 2 of the present invention;

Fig. 3 is the transistor transfer characteristic graph of embodiment 1 of the present invention and comparative example 1;

Fig. 4 is the transistor transfer characteristic graph of embodiment 1 of the present invention and comparative example 2;

In the figure, 1 is the substrate; 2 is the bottom gate electrode; 3 is the bottom gate dielectric layer; 4 is the gallium oxide channel layer; 5 is the drain electrode, 6 is the top gate dielectric layer; 7 is the top gate electrode; 8 is the source electrode.

Detailed ways

The present invention will be further described below in conjunction with the accompanying drawings and embodiments, but is not limited thereto.

Example 1

A double-gate gallium oxide field effect transistor with high heat dissipation performance. The structure is shown in FIG. A source electrode 8 and a drain electrode 5 are arranged on the channel layer 4, and the upper surface of the gallium oxide channel layer between the source electrode 8 and the drain electrode 5 is covered with a top gate dielectric layer 6, and a top gate electrode is arranged on the top gate dielectric layer 7.

The substrate is a silicon carbide substrate, and the bottom gate electrode is a three-layer alloy of Ti/Au/Ti, with thicknesses of 10/1000/10nm respectively.

The thickness of the bottom gate dielectric layer is 10 nm, and the bottom gate dielectric layer is aluminum oxide.

The gallium oxide channel layer uses gallium oxide film as the channel layer, the thickness of the gallium oxide film is 50nm, it is N-type doped gallium oxide, and the doping concentration is 5×10 ¹⁶ cm ^-3 -5×10 ¹⁸ cm ^-3

The thickness of the top gate dielectric layer is 10nm, the top gate dielectric layer is hafnium oxide, the top gate electrode is Pd/Au alloy, the thickness of Pd is 10nm, and the thickness of Au is 1000nm.

The source electrode is Ti/Au alloy, the thickness of Ti is 10nm, and the thickness of Au is 1000nm. The drain electrode is Ti/Au alloy, the thickness of Ti is 10nm, and the thickness of Au is 1000nm.

The preparation steps are as follows:

(1) Clean the silicon carbide substrate as follows: wash with acetone for 5 minutes, then wash with ethanol for 5 minutes, then wash with deionized water for 5 minutes, and finally blow dry with nitrogen.

(2) Bottom gate electrodes are evaporated on the upper surface of the cleaned substrate, the material is Ti/Au/Ti, and the thicknesses are 10/1000/10nm respectively;

(3), aluminum oxide is deposited as the bottom gate dielectric layer by atomic layer deposition on the upper surface of the sample after step (2), with a thickness of 10nm;

(4), stick the adhesive tape on the gallium oxide crystal, and then tear it off quickly, the surface film of the gallium oxide crystal will stick to the tape, with a thickness of 50nm;

(5), the adhesive tape described in step (4) is put on the sample of step (3);

(6), put the sample of step (5) in 4-methylisobutyl ketone, heat to 80°C, soak for 20 minutes, and remove the adhesive tape;

(7), the sample described in step (6) is cleaned, and the steps are as follows: put into acetone to wash for 5 minutes, then put into ethanol to wash for 5 minutes, then wash with deionized water for 5 minutes, and finally blow dry with nitrogen.

(8), put the sample described in step (7) into the atomic layer deposition equipment, and grow 10nm hafnium oxide as the top gate dielectric layer;

(9), removing part of hafnium oxide from the sample described in step (8) by photolithography and inductively coupled plasma etching, for the preparation of the source electrode and the drain electrode;

(10), the sample described in step (9) is prepared by photolithography, electron beam evaporation and stripping, and the source electrode and the drain electrode are made of Ti/Au with a thickness of 10/1000nm;

(11), the sample described in step (10) is put into the vacuum annealing furnace, temperature is 400 degrees, annealed for 60 seconds;

(12) The sample described in step (11) was prepared by photolithography, electron beam evaporation and lift-off techniques, and the top gate electrode was prepared from Pd/Au with a thickness of 10/1000nm.

Example 2

A double-gate gallium oxide field effect transistor with high heat dissipation performance. The structure is shown in FIG. The channel layer 4 is provided with a source electrode 8 and a drain electrode 5 on the gallium oxide channel layer 4, and the upper surface of the gallium oxide channel layer between the source electrode 8 and the drain electrode 5 is covered with a top gate dielectric layer 6, and the top gate dielectric layer A top gate electrode 7 is provided on the layer.

The substrate is a silicon carbide substrate, and the bottom gate electrode is a Ti/Au/Ti three-layer alloy with thicknesses of 500/50/500nm respectively.

The thickness of the bottom gate dielectric layer is 100nm, and the bottom gate dielectric layer is hafnium oxide.

The gallium oxide channel layer uses gallium oxide film as the channel layer, the thickness of the gallium oxide film is 500nm, it is N-type doped gallium oxide, and the doping concentration is 5×10 ¹⁶ cm ^-3 -5×10 ¹⁸ cm ^-3

The thickness of the top gate dielectric layer is 100nm, the top gate dielectric layer is aluminum oxide, the top gate electrode is Pd/Au alloy, the thickness of Pd is 50nm, and the thickness of Au is 500nm.

The source electrode is Ti/Au alloy, the thickness of Ti is 50nm, and the thickness of Au is 500nm. The drain electrode is Ti/Au alloy, the thickness of Ti is 50nm, and the thickness of Au is 500nm.

The preparation steps are as follows:

(1) Clean the silicon carbide substrate as follows: wash with acetone for 5 minutes, then wash with ethanol for 5 minutes, then wash with deionized water for 5 minutes, and finally blow dry with nitrogen.

(2) Bottom gate electrodes are evaporated on the upper surface of the cleaned substrate, the material is Ti/Au/Ti, and the thicknesses are 500/50/500nm respectively;

(3) Hafnium oxide is deposited as a bottom gate dielectric layer by atomic layer deposition on the upper surface of the sample processed in step (2), with a thickness of 100nm;

(4), stick the adhesive tape on the gallium oxide crystal, and then quickly tear it off, the surface film of the gallium oxide crystal will stick to the tape, with a thickness of 500nm;

(5), the adhesive tape described in step (4) is put on the sample of step (3);

(6), put the sample of step (5) in 4-methylisobutyl ketone, heat to 80°C, soak for 20 minutes, and remove the adhesive tape;

(7), the sample described in step (6) is cleaned, and the steps are as follows: put into acetone to wash for 5 minutes, then put into ethanol to wash for 5 minutes, then wash with deionized water for 5 minutes, and finally blow dry with nitrogen.

(8), the sample described in step (7) is put into atomic layer deposition equipment, the aluminum oxide of growth 100nm, as top gate dielectric layer;

(9), removing part of the aluminum oxide from the sample described in step (8) by photolithography and inductively coupled plasma etching, for the preparation of the source electrode and the drain electrode;

(10), the sample described in step (9) is prepared by photolithography, electron beam evaporation and stripping, and the source electrode and the drain electrode are made of Ti/Au, with a thickness of 50/500nm;

(11), the sample described in step (10) is put into the vacuum annealing furnace, temperature is 400 degrees, annealed for 60 seconds;

(12) The sample described in step (11) is prepared by photolithography, electron beam evaporation and lift-off techniques, and the top gate electrode is prepared from Pd/Au with a thickness of 50/500nm.

Comparative example 1

A gallium oxide field thin film effect transistor, the structure is as shown in embodiment 1, the difference is:

The transistor does not have a bottom gate dielectric layer.

Comparative example experiment 1

Test the transfer characteristic of embodiment 1 and comparative example 1, the transfer characteristic curve that records is as shown in Figure 3; Can find out that the threshold voltage of embodiment 1 and comparative example 1 are respectively-4V and-3V from the figure; Voltage (such as -3V), the source and drain currents of Example 1 and Comparative Example 1 are 1.6×10 ^-11 A and 1.6×10 ^-9 A respectively; by comparing Figure 3, it can be clearly seen that the present invention has a double gate structure The transistor can significantly improve the control ability of the gate electrode to the carrier, and improve the pinch-off characteristics of the device.

Comparative example 2

A gallium oxide field thin film effect transistor, the structure is as shown in embodiment 1, the difference is:

The transistor is not provided with a top gate dielectric layer and a top gate electrode.

Comparative example experiment 2

Test the transfer characteristic of embodiment 1 and comparative example 2, the transfer characteristic curve that records is as shown in Figure 4; Can find out that the threshold voltage of embodiment 1 and comparative example 2 are respectively-4V and-3.5V from the figure; Same The gate voltage (such as -3V), the source and drain currents of Example 1 and Comparative Example 1 are 1.6×10 ^-11 A and 2.7×10 ^-10 A respectively; by comparing Figure 4, it can be clearly seen that the present invention has a double gate structure The transistor can significantly improve the control ability of the gate electrode to the carrier, and improve the pinch-off characteristics of the device.

Claims (10)

1. a kind of high heat dispersion double grid gallium oxide field-effect thin film transistor (TFT), including substrate, gate electrode, source electrode and electric leakage Pole, which is characterized in that bottom gate dielectric layer, gallium oxide channel layer are disposed on substrate from bottom to up, on gallium oxide channel layer It is provided with source electrode and drain electrode, the gallium oxide channel layer upper surface between source electrode and drain electrode is covered with top gate medium layer.

2. high heat dispersion double grid gallium oxide field-effect thin film transistor (TFT) according to claim 1, which is characterized in that described Gate electrode include bottom gate thin film and top-gated electrode, bottom gate thin film is between substrate bottom or substrate and bottom gate medium；Top-gated Electrode is located on top gate medium layer.

3. high heat dispersion double grid gallium oxide field-effect thin film transistor (TFT) according to claim 1, which is characterized in that described Substrate is one kind in silicon carbide, diamond, silicon or copper；The bottom gate thin film is Ti/Au/Ti three-layer alloys, Ti thickness 10- 500nm, Au thickness 50-1000nm.

4. high heat dispersion double grid gallium oxide field-effect thin film transistor (TFT) according to claim 1, which is characterized in that described The thickness of bottom gate dielectric layer is 10-100nm, and bottom gate dielectric layer is silica, aluminium oxide or hafnium oxide.

5. high heat dispersion double grid gallium oxide field-effect thin film transistor (TFT) according to claim 1, which is characterized in that described Gallium oxide channel layer using gallium oxide film as channel layer, the thickness of gallium oxide film is 50-500nm, is aoxidized for n-type doping Gallium, doping concentration 5 × 10¹⁶cm^-3-5×10¹⁸cm^-3。

6. high heat dispersion double grid gallium oxide field-effect thin film transistor (TFT) according to claim 1, which is characterized in that top-gated Thickness of dielectric layers is 10-100nm, and top gate medium layer is silica, aluminium oxide or hafnium oxide；The top-gated electrode is Pd/Au Alloy, Pd thickness 10-500nm, Au thickness 50-1000nm；The source electrode is Ti/Au alloys, and Ti thickness 10-500nm, Au are thick Spend 50-1000nm；The electric leakage extremely Ti/Au alloys, Ti thickness 10-500nm, Au thickness 50-1000nm.

7. a kind of preparation method of double grid gallium oxide field-effect thin film transistor (TFT), including steps are as follows：

(1) substrate cleaning step；

(2) bottom gate thin film layer is deposited in substrate bottom or top；

(3) sample surfaces that step (2) obtains deposit bottom gate dielectric layer using atomic layer deposition method；

(4) it tears and gallium oxide film and is transferred on step (3) sample on gallium oxide crystal；

(5) transfer is removed, is then cleaned；

(6) sample atoms after cleaning deposit top gate medium layer；

(7) the top gate medium layer at etching removal both ends forms source region and drain region,

(8) Ti/Au alloys are covered in source region and drain region upper surface, is respectively formed source electrode and drain electrode；

(9) the sample annealing that step (8) obtains；

(10) Pd/Au alloys are covered in top gate medium layer upper surface after annealing, form top-gated electrode.

8. the preparation method of double grid gallium oxide field-effect thin film transistor (TFT) according to claim 7, which is characterized in that step (1) in, substrate cleaning step is：Substrate is cleaned 4-8 minutes with acetone, ethyl alcohol, deionized water successively, then nitrogen drying； In step (4), gallium oxide film of tearing on gallium oxide crystal is that adhesive tape is attached on gallium oxide crystal, is then quickly torn Under, the surface layer film of gallium oxide crystal is sticked on adhesive tape, and gallium oxide film thickness is 50-500nm on adhesive tape.

9. the preparation method of double grid gallium oxide field-effect thin film transistor (TFT) according to claim 7, which is characterized in that step (5) in, removal transfer is that sample is placed in 4- hexones, is heated to 75-85 DEG C, is impregnated 20 minutes, removal Adhesive tape；Cleaning in step (5) is, sample is cleaned 4-8 minutes with acetone, ethyl alcohol, deionized water successively, then nitrogen Drying.

10. the preparation method of double grid gallium oxide field-effect thin film transistor (TFT) according to claim 7, which is characterized in that step Suddenly (7) remove part top gate medium layer by photoengraving and inductively coupled plasma etching；Annealing temperature is 400- in step (9) 500 DEG C, annealing time is 60 seconds.