CN108549181A - A kind of array substrate, display device and test method - Google Patents

Abstract

A kind of array substrate, display device and test method, the array substrate include：First signal wire and second signal line, first signal wire and the second signal line are disconnected from each other, and first signal wire and the second signal line are coupled to the different location of same grid line.Array substrate provided in this embodiment provides independent two independent signal wires for same grid line, realizes the detection to grid line virtual connection.

Description

Array substrate, display device and testing method

technical field

The invention relates to electronic technology, in particular to an array substrate, a display device and a testing method.

Background technique

LCD (Liquid Crystal Display) is a flat and ultra-thin display device, which consists of a certain number of color or black and white pixels. At present, liquid crystal display is mainly based on thin film transistor (Thin Film Transistor, TFT) liquid crystal display, and its production process can be roughly divided into three parts: thin film transistor array (TFT Array) preparation and color filter plate preparation, liquid crystal display unit assembly (LC Cell) Assembly) preparation, liquid crystal display module (LiquidCrystal Module, LCM) preparation. During the manufacturing process of the liquid crystal panel, multiple inspection procedures need to be carried out. One of the most important inspection procedures is to test the cut liquid crystal cells (Cell Test) to confirm whether the liquid crystal cells are defective. Cell Test, referred to as ET, is carried out before the liquid crystal panel is attached with the driver chip and the flexible circuit board for input display signal. The test process is to first input a test signal to the liquid crystal panel to make its pixels display colors, and then use a defect detection device to observe whether each pixel is good or not. This process is called a light-on test (Light-on Test).

With the development of the display field, the requirements for product characteristics and durability are getting higher and higher, and functional defects such as X-line (bright line) and Open (broken line) should not occur. At present, it is difficult for LCD products to effectively intercept such defects during the ET lighting process, resulting in a waste of back-end module materials. What's more, bad products flow into the client and cause serious losses.

Contents of the invention

At least one embodiment of the present invention provides an array substrate panel, a display device, and a testing method, so as to detect defects.

In order to achieve the purpose of the present invention, at least one embodiment of the present invention provides an array substrate, including: a first signal line and a second signal line, the first signal line and the second signal line are disconnected from each other, and the The first signal line and the second signal line are coupled to different positions of the same gate line.

At least one embodiment of the present invention provides a display device, including the array substrate described in any embodiment.

At least one embodiment of the present invention provides a method for testing the above-mentioned array substrate, including:

A first voltage signal is provided to the first signal line, and a second voltage signal opposite in polarity to the first voltage signal is provided to the second signal line.

Compared with the related art, the array substrate provided by an embodiment of the present invention includes a first signal line and a second signal line, the first signal line and the second signal line are disconnected from each other, and the first signal line and the second signal line are coupled to different positions of the same gate line. The array substrate provided in this embodiment provides two independent signal lines for the same gate line, so as to realize the detection of the virtual connection of the gate lines.

Additional features and advantages of the invention will be set forth in the description which follows, and in part will be apparent from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention may be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.

Description of drawings

The accompanying drawings are used to provide a further understanding of the technical solution of the present invention, and constitute a part of the description, and are used together with the embodiments of the application to explain the technical solution of the present invention, and do not constitute a limitation to the technical solution of the present invention.

Fig. 1 is a schematic diagram of Gate (grid) normal and virtual connection;

FIG. 2 is a schematic diagram of ET pad (test pad) routing in the related art;

FIG. 3 is a structural diagram of a GOA circuit in the related art;

FIG. 4 is a schematic diagram of an array substrate provided by an embodiment of the present invention;

FIG. 5 is a schematic diagram of an array substrate provided by another embodiment of the present invention;

Fig. 6a is a schematic diagram of an array substrate provided by another embodiment of the present invention;

Fig. 6b is a schematic diagram of an array substrate provided by another embodiment of the present invention;

Fig. 7a is a schematic diagram of an array substrate provided by another embodiment of the present invention;

Fig. 7b is a schematic diagram of an array substrate provided by another embodiment of the present invention;

Fig. 7c is a schematic diagram of an array substrate provided by another embodiment of the present invention;

FIG. 8 is a schematic diagram of a GOA circuit provided by an embodiment of the present invention;

FIG. 9 is a schematic diagram of a GOA circuit provided by an embodiment of the present invention;

FIG. 10 is a flowchart of a testing method provided by an embodiment of the present invention.

Detailed ways

In order to make the purpose, technical solution and advantages of the present invention more clear, the embodiments of the present invention will be described in detail below in conjunction with the accompanying drawings. It should be noted that, in the case of no conflict, the embodiments in the present application and the features in the embodiments can be combined arbitrarily with each other.

The steps shown in the flowcharts of the figures may be performed in a computer system, such as a set of computer-executable instructions. Also, although a logical order is shown in the flowcharts, in some cases the steps shown or described may be performed in an order different from that shown or described herein.

Unless otherwise defined, the technical terms or scientific terms used in the present disclosure shall have the usual meanings understood by those skilled in the art to which the present invention belongs. "First", "second" and similar words used in the present disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. "Comprising" or "comprising" and similar words mean that the elements or items appearing before the word include the elements or items listed after the word and their equivalents, without excluding other elements or items. Words such as "connected" or "connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "Down", "Left", "Right" and so on are only used to indicate the relative positional relationship. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

Figure 1 is a schematic diagram of Gate (gate) normal and virtual connection. As shown in Figure 1, the normal product is shown in Figure 1 (a). During the manufacturing process of abnormal products, the connection abnormalities circled in (b) of Figure 1 appear, seemingly connected or disconnected, and in a false connection state. Such products often cannot be effectively intercepted during the manufacturing process, and have a bad impact on the client.

For the above problems, you can input signals with opposite polarities on the same grid line, so that the position of the line virtual connection will generate heat and burn out, and then perform a lighting test. Since the virtual connection position has been disconnected, the corresponding pixel unit cannot be lit. On, so as to detect the virtual connection of the line and detect the fault.

FIG. 2 is a schematic diagram of wiring of a panel (panel) ET pad (test pad) in the related art. In the related art, the gate driver circuit is fabricated on the array substrate by using GOA (Gate Driver On Array, gate driver on array) technology. AA in FIG. 2 is a display area, and GOA circuits (not shown) are arranged on both sides of the display area AA. The GOA circuit provides a gate drive signal for the TFT. GOA drivers include two types, bilateral GOA drivers and unilateral GOA drivers. Among them, double-sided driving refers to corresponding to a row of gate lines, and there is a GOA unit on the left and right sides to drive it. Unilateral driving means that only one GOA unit drives a row of gate lines. line, and the GOA unit on the other side drives the even row gate lines. As shown in FIG. 2 , VGH voltage and VGL voltage are applied to the GOA unit through VGH wiring and VGL wiring, wherein VGH (high level) and VGL (low level) are the turn-on voltage and turn-off voltage of the TFT respectively. In related technologies, in order to achieve lighting and GOA driving effects, VGH and VGL give signals when ET is lighting. FIG. 3 is a structural diagram of a GOA circuit in the related art. In the circuit shown in Figure 3, the overall GOA output signal (such as OUTPUT_N) can be turned into a VGL signal by pulling the Reset signal high, but because the VGH or VGL signals input on the left and right sides are consistent, it is impossible to realize ET lighting. The left GOA unit and the right GOA unit output opposite gate driving signals to the same gate line, therefore, it is impossible to detect poor virtual connection of the gate line in the related art.

Embodiment one

As shown in FIG. 4 , this embodiment provides an array substrate 40, including: a first signal line 401 and a second signal line 402, the first signal line 401 and the second signal line 402 are disconnected from each other, and The first signal line 401 and the second signal line 402 are coupled to different positions of the same gate line 403 .

For example, the different positions where the first signal line 401 and the second signal line 402 are coupled to the same gate line 403 include: the first signal line 401 and the second signal line 402 are coupled to the same gate line 403 at both ends.

It should be noted that only one gate line is shown in the figure, and there are multiple gate lines on the array substrate 40 , and the rest of the gate lines are similar and will not be described here again.

In this embodiment, two signal lines disconnected from each other are coupled to the same gate line, and different signals with opposite polarities can be input to the same gate line through these two signal lines. If there is a virtual connection in the gate line, Then the position of the virtual connection will generate heat and burn out, exposing the defect, and then perform a lighting test. Since the position of the virtual connection has been disconnected, the corresponding pixel unit cannot be lit, so as to detect the virtual connection of the line and detect the defect.

In one embodiment, the first signal line 401 is connected to a test pad 404 , and the second signal line 402 is connected to a test pad 405 . The test pad is used for inputting signals to the first signal line 401 and the second signal line 402 conveniently. The test pad 404 and the test pad 405 can be directly arranged at the end of the signal line to which they are connected, or can be connected to the signal line through a lead wire, so as to facilitate the layout of the test pad. The test pad 404 and the test pad 405 are, for example, round pads or square pads, of course, they may also be in other shapes, which are not limited in this application.

Embodiment two

As shown in FIG. 5, in this embodiment, on the basis of FIG. 4, a first GOA circuit 406 is included between the first signal line 401 and the gate line 403, and the first signal line 401 passes through the first GOA circuit 406. Coupled to the gate line 403, the first signal line 401 is coupled to the drive signal input end (such as VGH, VGL input end) of the first GOA circuit 406, the drive signal output end of the first GOA circuit 406 Coupled to one end of the gate line 403, a second GOA circuit 407 is included between the second signal line 402 and the gate line 403, and the second signal line 402 is coupled to the gate line 403 through the second GOA circuit 407 , the second signal line 402 is coupled to the driving signal input terminal (such as VGH, VGL input terminal) of the second GOA circuit 407, and the driving signal output terminal of the second GOA circuit 407 is coupled to the gate the other end of line 403. This scheme can be applied to the case of bilateral GOA driving.

In an embodiment, the first signal line 401 may use an existing gate drive signal line, such as the first high-level drive signal line (such as a signal line for inputting a VGH signal) and at least one of a first low-level drive signal line (such as a signal line for inputting a VGL signal), the first high-level drive signal line and the first low-level drive signal line are coupled to the The drive signal input end of the first GOA circuit, the second signal line 402 is at least one of a second high-level drive signal line and a second low-level drive signal line, and the second high-level drive signal line and the second low-level driving signal line are coupled to the driving signal input terminal of the second GOA circuit.

Embodiment three

As shown in FIG. 6a, in this embodiment, on the basis of FIG. 4, a first GOA circuit 406 is included between the first signal line 401 and the gate line 403, and the first signal line 401 is coupled to the The driving signal input end of the first GOA circuit 406 (such as VGH, VGL input end), the driving signal output end of the first GOA circuit 406 is coupled to one end of the gate line 403, the second signal line 402 It is coupled to the other end of the gate line through a switch circuit 408 . This scheme can be applied to the case of unilateral GOA driving. When the switch circuit 408 is turned on, the gate line is connected to the second signal line 402 , and when the switch circuit 408 is turned off, the gate line is disconnected from the second signal line 402 . As shown in FIG. 6b, the switch circuit 408 is, for example, a transistor, and the gate line 403 and the second signal line 403 are respectively connected to two ends of the transistor. It should be noted that this is only an example, and other switching circuits can be used as required.

In an embodiment, the first signal line 401 includes at least one of a first high-level drive signal line and a first low-level drive signal line, and the first high-level drive signal line is used to input a high-level signal line. A flat signal is sent to the first GOA circuit, and the first low-level driving signal line is used to input a low-level signal to the first GOA circuit. The first high-level driving signal line and the first low-level driving signal line are coupled to a driving signal input end of the first GOA circuit. The second signal line 402 is, for example, at least one of a second high-level drive signal line and a second low-level drive signal line, and the second high-level drive signal line and the second low-level drive signal line The line is coupled to the driving signal input terminal of the second GOA circuit.

Embodiment Four

In this solution, the VGL and VGH ET pads are changed to two-sided input mode, and the disconnection design is carried out on the opposite side of the IC. In this way, the VGH and VGL of the GOA on both sides can be controlled independently.

As shown in Figure 7a, in this embodiment, by adding an electrical signal input function on the other side of the Gate line outside the normal structure of the Panel lighting line, the existing VGH line and VGL line are disconnected (as shown in the circle in Figure 7a shown), VGHpad and VGL pad are added on the right side to provide different signals for the left and right GOA. After adding this structure, when the product is ET, the normal lighting signal is input on one side, and the opposite polarity signal is input on the other side. By inputting the opposite polarity signal on the Gate line, heat occurs at the virtual connection position of the line and burns out, thereby Realize the detection of virtual connection of the line and detect the fault. That is, in this embodiment, the first signal line is the VGH line 701a and the VGL line 702a on the left side, the second signal line is the VGH line 703a and the VGL line 704a on the right side, and the VGH line 701a and the VGH line 703a are disconnected from each other , VGL line 702a and VGL line 704a are disconnected from each other.

In another embodiment, as shown in Figure 7b, only the existing VGH line can be disconnected, the left and right sides of the existing VGL line can be kept connected, and a VGH pad (not a VGL pad) can be added on the right side to realize Different signals are provided for left and right GOA. That is, in this embodiment, the first signal line is the left VGH line 701b, the second signal line is the right VGH line 703b, and the VGH line 701b and the VGH line 703b are disconnected from each other. A VGH signal can be applied to the VGH pad connected to the VGH line 701b, and a VGL signal can be applied to the VGH pad connected to the VGH line 703b, so that the positions where the gate lines are virtual-connected will generate heat and burn out.

In another embodiment, as shown in Figure 7c, only the existing VGL line can be disconnected, the left and right sides of the existing VGH line can be kept connected, and a VGL pad (without adding a VGH pad) can be added on the right side to realize Different signals are provided for left and right GOA. That is, in this embodiment, the first signal line is the left VGL line 702c, the second signal line is the right VGL line 704c, and the VGL line 702c and the VGL line 704c are disconnected from each other. The VGH signal can be applied to the VGL pad connected to the VGL line 702c, and the VGL signal can be applied to the VGL pad connected to the VGL line 704c, so that the positions where the grid lines are virtual-connected will generate heat and burn out.

The scheme shown in Figure 7a is used for illustration. As shown in Figure 8, for one side of the GOA, when the Reset signal is high, a VGL signal (low level signal) is applied to the VGLpad, and the GOA circuit outputs the VGL signal to the Gate line through OUTPUT_N. As shown in Figure 9, for the GOA on the other side, for example: when the Reset signal is provided, the VGH signal (high level signal) is provided to the GOA through the VGL pad, and the GOA on the other side outputs the VGH signal to the Gate line through OUTPUT_N. At this time, The signal polarity at both ends of the Gate line is opposite (one is VGL, the other is VGH). When the left and right sides of the Gate line provide different signals, the virtual connection position is similar to the high resistance position, which is equivalent to a resistance. According to Joule's law: Joule's heat Q=I ² RT, the greater the resistance R, the greater the heat Q, thus, the virtual connection part of the Gate line will be open, and the line failure can be effectively detected when the ET is lit, so as to prevent the functional failure of the customer point And lead to problems such as point line, compensation and so on. However, there is no problem with the normal line, and the gate line will not have the abnormal problem of burning due to heat. This type of design is suitable for bilateral GOA driven products to improve Gate open defects. It should be noted that the VGL input terminal of the GOA circuit in FIG. 8 and FIG. 9 may also be the VGH input terminal, that is, both of them share the input terminal. It should be noted that the GOA circuits shown in FIG. 8 and FIG. 9 are only schematic diagrams, which are not limited in this application. Other GOA circuits can also be applied in this application.

It should be noted that the present application is not limited to the array substrate using the GOA technology, and other array substrates are also applicable.

Embodiment five

For single-side drive GOA products, one of the left VGH signal line and VGL signal line can be used as the first signal line, and one of the right VGH signal line and VGL signal line can be used as the second signal line, one end of the gate line The drive signal output end of the GOA circuit is connected, and the other end of the gate line is coupled to the second signal line through the switch circuit. For example, when the left GOA provides drive signals for the odd-numbered gate lines, and the right GOA provides drive signals for the even-numbered gate lines, the second signal line is connected to the right end of the odd-numbered gate lines and the left end of the even-numbered gate lines through the switch circuit. At this time, the VGL signal can be provided on one side of the gate line, and the VGH signal can be provided on the other side. For example, one side provides the VGL signal through the GOA circuit, and the other side directly provides the VGH signal through the second signal line (at this time, the switching circuit The control signal EN Touch is pulled high, and the VGH signal is provided through the VGH pad or VGL pad), according to Joule’s law: Joule’s heat Q=I ² RT, the larger the resistance R, the larger the heat Q, and the left and right sides of the virtual connection part of the Gate line provide positive and negative There is an open circuit in the signal, and the interception is poor.

Embodiment six

This embodiment provides a display device, which includes the array substrate provided by any one of the above embodiments. An example of the display device is a liquid crystal display device.

The display device may be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame and a navigator.

Embodiment seven

As shown in FIG. 10 , this embodiment provides a method for testing the array substrate described in any of the above embodiments, including:

Step 1001, providing a first voltage signal to the first signal line, and providing a second voltage signal opposite in polarity to the first voltage signal to the second signal line.

In this embodiment, by applying voltage signals with opposite polarities on the same gate line, the virtual contact position is burned and disconnected, thereby exposing the defect.

Wherein, the first voltage signal and the second voltage signal may be a VGH signal and a VGL signal respectively. It should be noted that this is only an example, and the first voltage signal and the second voltage signal may also be other voltage signals with opposite polarities. , the specific value can be obtained through experiments.

In one embodiment, after providing a first voltage signal to the first signal line, and providing a second voltage signal opposite to the polarity of the first voltage signal to the second signal line, step 1002 is further included: performing Lighting test. After the virtual contact position is disconnected through step 1001, a lighting test signal is applied to perform a lighting test. The specific lighting test method will not be repeated here.

Take the solution shown in Figure 7a as an example to illustrate the test method. Apply the VGH signal to the VGH line 701a, then the left GOA outputs the VGH signal to the grid line, and applies the VGL signal to the VGL line 704a, then the right GOA outputs the VGL signal to the grid line. At this time, the two sides of the grid line are respectively applied VGH signal and VGL signal, if there is a virtual connection on the gate line, the position of the virtual connection will generate heat and burn out to disconnect. Then, a lighting test is performed by applying a VGH signal to the VGH line 701a, applying a VGH signal to the VGH line 703a, and then applying a VGL signal to the VGL line 702a, and applying a VGL signal to the VGL line 704a.

Taking the scheme shown in FIG. 7b as an example, when a VGH signal is applied to the VGH line 701b, the left GOA outputs a VGH signal to the gate line, and when a VGL signal is applied to the VGH line 703b, the right GOA outputs a VGL signal to the gate line. At this time, the VGH signal and the VGL signal are respectively applied to both sides of the gate line. If there is a virtual connection in the gate line, the position of the virtual connection will generate heat at this time and burn out to disconnect. Then, a lighting test is performed in which a VGH signal is applied to the VGH line 701b, a VGH signal is applied to the VGH line 703b, and thereafter, a VGL signal is applied to the VGL line 702b.

Taking the solution shown in FIG. 7c as an example, when a VGH signal is applied to the VGL line 702c, the left GOA outputs a VGH signal to the gate line, and when a VGL signal is applied to the VGL line 704c, the right GOA outputs a VGL signal to the gate line. At this time, the VGH signal and the VGL signal are respectively applied to both sides of the gate line. If there is a virtual connection in the gate line, the position of the virtual connection will generate heat at this time and burn out to disconnect. Then, a lighting test is performed in which a VGH signal is applied to the VGH line 701c, and then a VGL signal is applied to the VGL line 702c, and a VGL signal is applied to the VGL line 704c.

The following points need to be explained:

(1) Embodiments of the present invention The drawings only relate to the structures related to the embodiments of the present invention, other structures can refer to the general design.

(2) For the sake of clarity, in the drawings used to describe the embodiments of the present invention, the thickness of layers or regions is enlarged or reduced, that is, these drawings are not drawn according to actual scale. It will be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" or "under" another element, it can be "directly on" or "under" the other element, Or intervening elements may be present.

(3) In the case of no conflict, the embodiments of the present invention and the features in the embodiments can be combined with each other to obtain new embodiments.

Although the embodiments disclosed in the present invention are as above, the described content is only an embodiment adopted for understanding the present invention, and is not intended to limit the present invention. Anyone skilled in the field of the present invention can make any modifications and changes in the form and details of the implementation without departing from the spirit and scope disclosed by the present invention, but the patent protection scope of the present invention must still be The scope defined by the appended claims shall prevail.

Claims (10)

1. An array substrate, comprising: a first signal line and a second signal line, the first signal line and the second signal line are disconnected from each other, and the first signal line and the second signal line Coupled to different positions of the same gate line. 2. The array substrate according to claim 1, wherein the different positions where the first signal line and the second signal line are coupled to the same gate line include: the first signal line and the second signal line The two signal lines are coupled to two ends of the same gate line. 3. The array substrate according to claim 1, wherein a first array substrate gate drive circuit is included between the first signal line and the gate line, and the first signal line is coupled to the The driving signal input terminal of the first array substrate gate driving circuit, the driving signal output terminal of the first array substrate gate driving circuit is coupled to one end of the gate line, the second signal line and the gate line A second array substrate gate drive circuit is included between them, the second signal line is coupled to the drive signal input end of the second array substrate gate drive circuit, and the drive signal of the second array substrate gate drive circuit The output end is coupled to the other end of the gate line. 4. The array substrate according to claim 3, wherein the first signal line comprises at least one of a first high-level drive signal line and a first low-level drive signal line, and the first high-level drive signal line The flat driving signal line and the first low-level driving signal line are coupled to the driving signal input end of the first array substrate gate driving circuit, and the first high-level driving signal line is used to input a high level signal to the gate drive circuit of the first array substrate, the first low-level drive signal line is used to input a low-level signal to the gate drive circuit of the first array substrate, and the second signal line includes the first At least one of two high-level drive signal lines and a second low-level drive signal line, the second high-level drive signal line and the second low-level drive signal line are coupled to the second array substrate The drive signal input terminal of the gate drive circuit, the second high-level drive signal line is used to input a high-level signal to the gate drive circuit of the first array substrate, and the second low-level drive signal line is used for and inputting a low level signal to the gate driving circuit of the second array substrate. 5. The array substrate according to claim 1, wherein a first array substrate gate drive circuit is included between the first signal line and the gate line, and the first signal line is coupled to the The driving signal input terminal of the gate driving circuit of the first array substrate, the driving signal output terminal of the first array substrate gate driving circuit is coupled to one end of the gate line, and the second signal line is coupled through a switch circuit Connect to the other end of the grid line. 6. The array substrate according to claim 5, wherein the first signal line comprises at least one of a first high-level drive signal line and a first low-level drive signal line, and the first high-level drive signal line The flat drive signal line and the first low-level drive signal line are coupled to the drive signal input end of the array substrate gate drive circuit, and the first high-level drive signal line is used to input a high-level signal to In the first array substrate gate drive circuit, the first low-level drive signal line is used to input a low-level signal to the first array substrate gate drive circuit. 7. The array substrate according to any one of claims 1 to 6, wherein the first signal line is connected to a test pad, and the second signal line is connected to a test pad. 8. A display device, comprising the array substrate according to any one of claims 1 to 7. 9. A method for testing the array substrate according to any one of claims 1 to 7, comprising: A first voltage signal is provided to the first signal line, and a second voltage signal opposite in polarity to the first voltage signal is provided to the second signal line. 10. The testing method according to claim 9, wherein a first voltage signal is provided to the first signal line, and a second voltage signal opposite in polarity to the first voltage signal is provided to the second signal line. After the voltage signal, it also includes: performing a lighting test.