CN108537999A - A kind of eight road Competition Answers - Google Patents

Abstract

The invention discloses a kind of eight road Competition Answers, circuit and timing circuit are raced to be the first to answer a question in the control circuit connection：Race to be the first to answer a question circuit：It is used simultaneously for eight players, is elected to picking hand button press, the player got at first can numbered and be latched, and shown on the screen；Timing circuit：After host starts " beginning " key, timer carries out subtracting timing, and contestant races to be the first to answer a question within the set time, races to be the first to answer a question effectively；If timing has arrived, nobody races to be the first to answer a question, then it is invalid to race to be the first to answer a question.Compared with traditional question-and-answer game apparatus, production cost is greatly reduced with 74LS148 and other common 74LS series digits integrated circuits using the functional characteristics of 74LS148 No. eight latch in the present invention.

Description

An eight-way competition answering machine

technical field

The invention relates to the technical field of electronic design, in particular to an eight-way race answering machine.

Background technique

The traditional answering machine design uses many discrete components in the answering machine, resulting in high cost per channel, and the development of modern electronic technology requires electronic circuits to develop in the direction of digitalization and integration, so a digital integrated full integrated circuit is designed The advanced multi-channel answering machine is a requirement for the development of modern electronic technology.

In order to solve the above problems, according to the functional characteristics of 74LS148 eight-way latch, an eight-way responder circuit is designed by using 74LS148 and several other commonly used 74LS series digital integrated circuits.

Contents of the invention

Based on the technical problems in the background technology, the present invention proposes an eight-way responder, which adopts the functional characteristics of the 74LS148 eight-way latch, uses 74LS148 and other commonly used 74LS series digital integrated circuits, and greatly reduces the production cost.

An eight-way competition answering machine, the control circuit is connected to the answering circuit and the timing circuit:

Answering circuit: It can be used by eight players at the same time. When the player presses the button, the number of the first player will be latched and displayed on the screen;

Timing circuit: When the host activates the "Start" button, the timer will count down, and the contestants will rush to answer within the set time, and the quick answer is valid; if the time is up and there is no one to answer, the quick answer is invalid.

Preferably, the answering circuit includes a priority encoder, a latch, and a decoding circuit, and the timing circuit includes a timing circuit and a decoding circuit, and the terminals of the answering circuit and the timing circuit are connected to a display circuit, so Said control circuit is also connected with the host control switch and the alarm circuit.

Preferably, the model of the priority encoder is 74LS148, which is used for judging the encoding of the answering contestants.

Preferably, the model of the latch is 74LS279, which is used to lock the player number.

Preferably, the model of the integrated decoder used in the decoding circuit is 74LS48, which is used to compile the player number.

Preferably, the timing circuit uses two decimal up-down counters 74LS192 to form a decimal down counter, and the clock pulse of the counter is provided by the second pulse circuit.

Design ideas of the present invention: (1) the answering device is simultaneously used for 8 players or 8 representative teams to compete, represented by 8 buttons S0-S7 respectively; (2) a system clearing and answering control switch S is set, and the switch is controlled by the host (3) The answering device has the functions of locking and displaying, that is, the contestant presses the button, and the corresponding number is locked and displayed on the LED digital tube. Until the system is cleared by someone; (4) The answering machine has a timed answering function. When the host activates the "Start" button, the timer will count down; Keep it until the host clears the system; (6) If the time is up and no one rushes to answer, this rush to answer is invalid.

The design principle of the present invention is as shown in Figure 1: after the power is turned on, the host will turn the switch to the "clear" state, the answering machine will be in the prohibited state, the number display will go out, and the timer will display the set time; the host will switch the switch Set the "Start" state, announce the "Start" answerer work, and the timer counts down. When the contestants rush to answer within the selected time, the answering machine completes: priority judgment, number latch, number display, and speaker prompts. After one round of answering, the timer stops, the second answering is prohibited, and the timer displays the remaining time. If you rush to answer again, the moderator must operate the "clear" and "start" state switches again.

The basic working process of the answering machine is: first the circuit is powered on, and before the host presses the "Start" button, when the switch is in the "reset" state, the answering is invalid; then press the answering button, the timing circuit starts timing, when the countdown ends If there is no contestant to answer the circuit alarm; before the end of the countdown, if someone rushes to answer, the display will display the contestant number and stop timing. The moderator resets the circuit and prepares for the next answer. as shown in picture 2.

The answering circuit design of the answering machine needs to meet three functions: (1) judge the priority of the players to answer; (2) latch the number of the priority answerer; (3) compile the latch signal and display the player's number. The answering machine needs a priority encoder, a latch and a decoding display circuit to complete its function. Priority encoder 74LS148 and RS latch 74LS279 can meet the design requirements, as shown in Figure 3.

The working principle of the answering circuit: W1-8 represents eight contestants answering the button switch, which is controlled by the host SW9 single-pole double-throw. SW9 has two states: (1) When the host control switch is in the zero state, the R of the trigger RS is low, and the output is low. 74LS48BI is high, and the display is off; 74LS148 is high through the input ST, and the working condition is 74LS148. This time the latch circuit does not work. If player No. 3 presses the answer switch (that is, closes SW4). At this time, the priority encoder 74LS148 inputs I3 with low efficiency, outputs a2a1a0100, a2a1a0 are respectively connected to 4S, 3S and 2S, according to the truth table of the RS latch, the output 2q3q4q are 110, 74 and 0011 input DCBA74LS48. 74LS48 The code and display shows "3". At the same time, when the 74LS148 input has a low normally, the GS activity is low, and the decoder is in the working state, so 1S 0. At this time, 1q outputs a high level, resulting in a high level of EI, 74LS148 is prohibited from working, and the input signals of other players' answer buttons will not be accepted. This ensures the accuracy of the answering circuit and priority of the transponder. For the final answer, the switch of the main unit is set to reset, the digital tube is displayed in gray, and everything returns to the initial state before entering the next round of answering rounds.

The answering device required by the design has a timing function, and the program host sets a quick answering time (30s) according to the difficulty of answering questions. In the design and use of the decimal synchronous up/down counter 74LS192, 74LS192 is a component with setting and reset functions. According to the design requirements, two pieces of 74LS192 are needed to form the decimal down counter. It can be seen from the functional truth table that only the borrow output terminal BO of the ones digit 74LS192 and the CPd of the tens digit 74LS192 can realize decimal counting down. It is noteworthy that, in order to make it count down, the CPu port must be connected to a high level, as shown in Figure 4.

Working principle of the timing circuit: firstly, the main engine answers (30 seconds, 555 assumptions) the pulse generating circuit according to the degree of difficulty of the change level of the input d3d2d1d074LS192. The pulse generating circuit provides a pulse timing circuit. In response to the start-off switch of the host, the PL activity of the 74LS192 set number terminal is low, the state is set, and the digital tube displays the time. The counter counts to 00, one by one zero 74LS192 borrow output end is low level, the counter stops working and alarms. When someone answers the time, the counter stops counting and the display shows the time.

Compared with the prior art, the present invention has the beneficial effects of:

An eight-way answering machine proposed by the present invention has the following advantages compared with ordinary answering machines: (1) It has a reset device and a quick answering control, and can be manipulated by the host to prevent someone from advancing before the host says "start". Quick answering violates the rules; (2) It has a timing function, and if no one answers within the specified time, all contestants or teams will abstain from this question; (3) If there is still no one to answer within the specified time, the time is exhausted and rush answering is prohibited. Compared with the traditional answering machine, the present invention adopts the functional characteristics of the 74LS148 eight-way latch, and uses the 74LS148 and other commonly used 74LS series digital integrated circuits to greatly reduce the production cost.

Description of drawings

The accompanying drawings are used to provide a further understanding of the present invention, and constitute a part of the description, and are used together with the embodiments of the present invention to explain the present invention, and do not constitute a limitation to the present invention. In the attached picture:

Fig. 1 is the general block diagram of digital answering machine of the present invention;

Fig. 2 is the basic workflow of the responder designed by the present invention;

Fig. 3 is the quick-answer circuit of this quick-answer device;

Fig. 4 is the timing circuit of this answering machine;

Figure 5 is the overall circuit of the responder.

Detailed ways

The present invention will be further explained below in conjunction with specific embodiments.

Referring to Fig. 3, the present invention is made up of priority coder, latch, decoding circuit in the rush answering circuit part. The answering circuit needs to meet three functions: first, to judge the priority of the players to answer; second, to latch the number of the priority answerer; third, to compile the latch signal and display the player's number. The answering machine needs a priority encoder, a latch and a decoding display circuit to complete its function. Priority encoder 74LS148 and RS latch 74LS279 can meet the design requirements. According to the 74LS148 truth table, the encoder has 8 signal inputs and 3 binary outputs. EI is the enable input terminal and active low, when EI is low usually, the encoder is in the working state; EO output enable terminal, only when EI=0, and all inputs 1, output 0; characterize GS encoder if and EI GS is active when at least one active level is input for low level. Therefore, the circuit can be controlled accordingly according to the characteristics of the EI, EO, and GS function extension terminals. The function of the encoder in the answering circuit is to judge the number of the responding person.

74LS279 is composed of 4 RS latches, and all of them are RS latches composed of NAND gates. Among them, 1S and 3S have two input ends, and S1 and S2 are both phase-and relationships. In this design, connect S2 to high level, and only use S1 to control the output. Its pin diagram is shown in Figure 4. The following table is the functional truth table of the SR latch. It is worth noting that S and R cannot be high at the same time, otherwise the output is uncertain.

74LS48 is a seven-segment display decoder. The integrated decoder has multiple auxiliary control terminals to enhance the functionality of the device. BI/RBO is the light-off input, when BI=0, all fonts are off. It can be seen from the truth table that the output of the decoder 74LS48 is active high, which is used to drive the common cathode digital tube. In order to form a four-input digital display circuit, the seven-segment display decoder can be connected with the seven-segment display digital tube.

Referring to Fig. 4, the answering machine designed by the present invention has a timing function and the program host according to the difficulty of answering questions quickly, and a quick answering time (30s) is set. The 74LS192 design is used in the design of the decade synchronous up/down counter, and the 74LS192 is a component with set and reset functions. According to the design requirements, two pieces of 74LS192 are needed to form a 100 base down counter. It can be seen from the functional truth table that only the borrow output terminal BO of the ones digit 74LS192 and the CPd of the tens digit 74LS192 can realize decimal counting down. It is worth noting that, to make it realize counting down, the CPU port must be connected to a high level.

The clock pulse of the counter is provided by the second pulse circuit, and the second pulse circuit is composed of a multivibrator composed of 555. The multivibrator can generate a rectangular wave output by itself when the power is turned on without an external input signal. Since the period is one second, the frequency is 1 Hertz. The charging and discharging times of the capacitor in the figure are:

t1=RB×C×ln2≈0.7RB×C

t2=(RA+RB)×C×ln2≈0.7(RA+RB)C

Therefore, the frequency of the 3-terminal output of the 555 is: f=1/(t1+t2)≈1.43/[(2RA+RB)C]

The values of resistance and capacitance used in the present invention are respectively: RA=15KΩ, R2=68KΩ, C1=10uf, which satisfy the above formula, that is, the second pulse is obtained.

Referring to Fig. 5, connect the rush-answer circuit circuit and the timing circuit, which is the overall circuit of the present invention. The host clears the entire circuit system, puts the switch in the "clear" position, and outputs low level, which is divided into two ways: one way is connected to the 1R2R3R4R terminal of the latch, so that the output terminal 1Q2Q3Q4Q is low level, 1Q The output low level is fed back to the EI terminal of 74LS148 through the AND gate, and the encoder does not work, so the display of the answering part is off and there is no display, and the reset is realized. Next, the host sets the answering time according to the difficulty of the question. This setting can be carried out by adjusting the high and low levels of the four input terminals D, C, B, and A of two 74LS192 inputs (for example, to set the time to 30 Seconds, the D, C, B, and A of the 74192 of the tens digit are set to 0, 0, 1, and 1 respectively, and the D, C, B, and A of the 74LS192 of each bit are all set to 0).

When the host reads the topic and says "Start" and puts the switch in the "Start" position, the output is high level, and this high level has two directions: one is output to the LD terminal of 74LS192, so that it is at high level And start counting down; there is one output to the R terminal of the latch.

When there is a contestant rushing to answer, such as answering No. 3, the 74LS148 three-terminal input is active low, and when the GS activity is low and the encoder is working normally, it is characterized. The encoded output of a2a1a0 is 100, and the corresponding 4s3s2s is 100, which is 74ls279, the output of 4q3q2q is 011, and the decoded displayed number is 3. At the same time, a high level of feedback: the output of the encoder can be input, making it stop working. At this time, if other players press the button or output, this ensures the priority of the response and the accuracy of the answering circuit.

On the other hand, the output level of 74LS148GS changes from high to low, and the second pulse generator generates the second pulse phase and the output is 0, and the pulse reaches the lower end of the 74LS192 counter. When the counter stops working, the original display is kept unchanged, that is, the time function of the count is used to calculate the pause of the record. If there is no player at the push of a button, the 74LS279 outputs all high levels and the 74LS148 also outputs high levels, and the 74LS48 outputs low levels until the end of the first quarter, and the 74LS48 turns off the input RI/RBO so that the signal 7474LS48 is not displayed; if the timer The counter counts down to 00, if no player presses a button to start, ten pieces of 74LS192 will stop counting by outputting a high level at the output end.

The above is only a preferred embodiment of the present invention, but the scope of protection of the present invention is not limited thereto, any person familiar with the technical field within the technical scope disclosed in the present invention, according to the technical solution of the present invention Any equivalent replacement or change of the inventive concepts thereof shall fall within the protection scope of the present invention.

Claims (6)

1. An eight-way competition answering machine, comprising a control circuit, is characterized in that, the control circuit is connected with a quick answering circuit and a timing circuit: Answering circuit: It can be used by eight players at the same time. When the player presses the button, the number of the first player will be latched and displayed on the screen; Timing circuit: When the host activates the "Start" button, the timer will count down, and the contestants will rush to answer within the set time, and the quick answer is valid; if the time is up and there is no one to answer, the quick answer is invalid. 2. A kind of eight-way race answering machine according to claim 1, wherein said answering circuit comprises a priority encoder, a latch and a decoding circuit, and said timing circuit comprises a timing circuit and a decoding circuit, so As mentioned above, the terminals of the answering circuit and the timing circuit are connected to the display circuit, and the control circuit is also connected to the moderator control switch and the alarm circuit. 3. A kind of eight-way competition answering machine according to claim 2, characterized in that, the model of the priority encoder is 74LS148, which is used to judge the encoding of the answering players. 4. An eight-way competition answering machine according to claim 2, characterized in that the model of the latch is 74LS279, which is used to lock the player number. 5. A kind of eight-way race answering machine according to claim 2, characterized in that, the model of the integrated decoder used in the decoding circuit is 74LS48, which is used to compile the player number. 6. A kind of eight-way competition answering machine according to claim 2, characterized in that, the timing circuit adopts two decimal system reversible counters 74LS192 to form a 100 system down counter, and the clock pulse of the counter is provided by the second pulse circuit.