CN108365007A - Insulated gate bipolar transistor - Google Patents

Abstract

The present invention proposes an insulated gate bipolar transistor, which comprises: a drift region; a P well region arranged on one side of the drift region; an N ⁺ emitter arranged on a side of the P well region away from the drift region side; two trenches, each trench is opened in the N ⁺ emitter, P well region and drift region, and runs through the N ⁺ emitter and P well region; the trench oxide layer is arranged in the two trenches and Covering the surface of each trench; two polysilicon gates, each polysilicon gate is filled on the side of the trench oxide layer away from the drift region, and each polysilicon gate includes N-type sub-gates and P-type sub-gate. The gate of the IGBT proposed by the present invention is set as a PN junction, so that the parasitic capacitance Cgc between the gate and the collector can be reduced, thereby shortening the turn-on time and further reducing the turn-on loss.

Description

Insulated Gate Bipolar Transistor

technical field

The invention relates to the technical field of semiconductors, and in particular, the invention relates to an insulated gate bipolar transistor.

Background technique

At present, the Insulated Gate Bipolar Transistor (Insulated Gate Bipolar Transistor, referred to as IGBT) is a composite fully-controlled voltage-driven power semiconductor device composed of a bipolar transistor (BJT) and an insulated gate field effect transistor (MOSFET). The advantages of the high input impedance of the power transistor and the low conduction voltage drop of the power transistor (that is, the giant transistor, referred to as GTR), because the IGBT has the advantages of small driving power and low saturation voltage, the IGBT is a new type of power electronic device. Widely used in various fields.

At this stage, FIG. 1 is a cross-sectional structure diagram of an existing insulated gate bipolar transistor. When the IGBT is turned on, electrons are injected from the emitter 300 to the drift region 100, and holes are injected from the collector 600 to the drift region 100. Electrons and holes The conductance modulation effect occurs in the drift region 100, so that the turn-on voltage drop of the IGBT is low; and when the IGBT is turned off, the holes in the drift region 100 are mainly eliminated by recombining with the electrons in the drift region, thereby realizing the turn-off of the IGBT. broken.

Contents of the invention

The present invention aims to solve one of the technical problems in the related art at least to a certain extent.

The present invention has been accomplished based on the following findings of the inventors:

During the research process, the inventors found that the performance of IGBT can be divided into dynamic characteristics and static characteristics. The dynamic characteristics are mainly reflected in the switching time of the IGBT, that is, the shorter the switching time, the smaller the switching power consumption of the IGBT and the better the dynamic characteristics of the IGBT; while the static characteristics are mainly reflected in the conduction voltage drop of the IGBT, that is, the conduction voltage The lower the drop, the lower the on-state power consumption of the IGBT and the better the static characteristics of the IGBT. Among them, the switching time of the IGBT is closely related to the parasitic capacitance Cge (the parasitic capacitance between the gate and the emitter) and Cgc (the parasitic capacitance between the gate and the collector). The smaller the parasitic capacitance, the shorter the turn-on time of the IGBT . The parasitic capacitance of the IGBT can be reduced by increasing the thickness of the trench oxide layer, but as the thickness of the trench oxide layer increases, the threshold voltage of the IGBT will increase, which in turn will result in an increase in the conduction voltage drop and deterioration of the static characteristics.

The inventors of the present invention have found through in-depth research that the gate of the IGBT can be set as a PN junction, so that the parasitic capacitance Cgc between the gate and the collector can be reduced, thereby shortening the turn-on time of the IGBT, thereby reducing the IGBT Turn-on loss. Moreover, the drift region can also be designed as a common drift region and a low-mobility drift region. In this way, when the IGBT is turned on, the common drift region provides a channel with a lower resistance for the drift of electrons and holes without affecting the IGBT. Turn-on voltage drop; when the IGBT is turned off, the low-mobility drift region can accelerate the recombination speed of electrons and holes, thereby shortening the turn-off time of the IGBT, thereby reducing the turn-off power consumption of the IGBT.

In view of this, an object of the present invention is to provide an insulated gate bipolar transistor that reduces parasitic capacitance, shortens switching time, or does not affect the conduction voltage.

In a first aspect of the invention, the invention proposes an insulated gate bipolar transistor.

According to an embodiment of the present invention, the insulated gate bipolar transistor includes: a drift region; a P well region, the P well region is arranged on one side of the drift region; an N ⁺ emitter, the N ⁺ emitter Set on the side of the P well region away from the drift region; two trenches, each of which is opened in the N ⁺ emitter, the P well region and the drift region, and runs through The N ⁺ emitter and the P well region; a trench oxide layer, the trench oxide layer is arranged in the two trenches and covers the surface of each trench; two polysilicon gates Each of the polysilicon gates is filled on the side of the trench oxide layer away from the drift region, and each of the polysilicon gates includes an N-type sub-gate and a P-type sub-gate stacked in sequence .

The inventor found through research that the gate of the insulated gate bipolar transistor of the embodiment of the present invention is a PN junction composed of an N-type sub-gate and a P-type sub-gate, so that the gap between the gate and the collector can be reduced. The parasitic capacitance Cgc, so as to shorten the turn-on time of the IGBT without increasing the turn-on voltage drop, thereby reducing the turn-on loss of the IGBT.

In addition, the insulated gate bipolar transistor according to the above embodiments of the present invention may also have the following additional technical features:

According to an embodiment of the present invention, the IGBT further includes: an insulating layer, the insulating layer is disposed on the surface of the polysilicon gate away from the drift region, and the insulating layer is in the drift region The orthographic projection on the polysilicon gate covers the orthographic projection of the polysilicon gate on the drift region; the P ⁺ collector layer, the P ⁺ collector layer is arranged on the side of the drift region away from the P well region.

According to an embodiment of the present invention, the material forming the drift region, the P well region, the N ⁺ emitter and the P ⁺ collector layer includes at least one selected from Si and SiC.

According to an embodiment of the present invention, the distance from the surface of the N-type sub-gate close to the P-type sub-gate to the bottom wall of the trench is smaller than the distance from the surface of the P-well region close to the drift region to the The distance from the bottom wall of the trench.

According to an embodiment of the present invention, the doping concentration of the N-type sub-gate is greater than 1*10 ¹⁸ /cm ³ , and the doping concentration of the P-type sub-gate is less than 5*10 ¹⁷ /cm ³ .

According to an embodiment of the present invention, the drift region includes: two first drift regions, the first drift region is in contact with the trench; a second drift region is disposed between the two Between the first drift region and forming the second drift region, the material of the first drift region is obtained by low-mobility treatment.

According to an embodiment of the present invention, the low mobility treatment method includes electron radiation and ion bombardment.

According to an embodiment of the present invention, the width of the trench is 1.5 microns, the width of the first drift region is 5 microns, and the width of the second drift region is 2 microns.

According to an embodiment of the present invention, the drift region includes a plurality of second drift regions and a plurality of third drift regions, and the plurality of second drift regions and the plurality of third drift regions are separated between the two The first drift regions are distributed alternately, and the material of the third drift region is the same as that of the first drift region.

According to an embodiment of the present invention, the trench has a width of 1.5 microns, the first drift region has a width of 5 microns, and the second drift region and the third drift region have a width of 0.3 microns.

Additional aspects and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention.

Description of drawings

The above and/or additional aspects and advantages of the present invention will become apparent and comprehensible from the description of the embodiments in conjunction with the following drawings, wherein:

FIG. 1 is a schematic cross-sectional structure diagram of an IGBT in the prior art;

Fig. 2 is a schematic cross-sectional structure diagram of an insulated gate bipolar transistor according to an embodiment of the present invention;

3 is a schematic cross-sectional structure diagram of an insulated gate bipolar transistor according to another embodiment of the present invention;

FIG. 4 is a schematic cross-sectional structure diagram of an IGBT according to another embodiment of the present invention.

reference sign

100 Drift Zone

110 First Drift Zone

120 Second Drift Zone

130 The third drift zone

200 P well area

300 N ⁺ emitter

410 groove

420 trench oxide

431 N-type sub-gate

432 P-type sub-gate

440 insulation

500 P ⁺ Collector

Detailed ways

The following describes the embodiments of the present invention in detail, and those skilled in the art will understand that the following embodiments are intended to explain the present invention, and should not be regarded as limiting the present invention. Unless otherwise specified, in the following examples that do not explicitly describe specific techniques or conditions, those skilled in the art can carry out according to commonly used techniques or conditions in this field or according to product instructions.

In one aspect of the invention, the invention provides an insulated gate bipolar transistor.

According to an embodiment of the present invention, referring to FIG. 2, the insulated gate bipolar transistor includes: a drift region 100, a P well region 200, an N ⁺ emitter 300, two trenches 410, a trench oxide layer 420 and two polysilicon gate; wherein, the P well region 200 is arranged on one side of the drift region 100; the N ⁺ emitter 300 is arranged on the side of the P well region 200 away from the drift region 100; each trench 410 is opened on the N ⁺ emitter 300, In the P well region 200 and the drift region 100, and through the N ⁺ emitter 300 and the P well region 200; the trench oxide layer 420 is arranged in the two trenches 410, and covers the surface of each trench 410; each polysilicon The gate is filled on the side of the trench oxide layer 420 away from the drift region 100 , and each polysilicon gate includes an N-type sub-gate 431 and a P-type sub-gate 432 stacked in sequence.

The inventors of the present invention have found through research that the gate of the IGBT can be set as a PN junction, so that when the gate voltage is applied, the gate PN junction is reversely biased, so that the gap between the N-type polysilicon gate and the P-type polysilicon gate It is equivalent to forming a capacitor C1, and a capacitor C2 is formed between the P-type polysilicon gate and the collector. Therefore, the parasitic capacitance Cgc' between the gate and the collector of the IGBT is equal to the series capacitance of the capacitance C1 and C2, that is, Cgc'=C1*C2/(C1+C2). It can be seen that after the gate of the IGBT is set as a PN junction, its parasitic capacitance Cgc' is smaller than C2 (that is, the parasitic capacitance Cgc in the prior art). Therefore, setting the polysilicon gate of the IGBT as a PN junction can effectively reduce the parasitic capacitance Cgc between the gate and the collector of the IGBT, thereby shortening the turn-on time of the IGBT without affecting the conduction voltage, thereby reducing Turn-on loss of small IGBT.

According to an embodiment of the present invention, referring to FIG. 3 , the insulated gate bipolar transistor may further include an insulating layer 440 and a P ⁺ collector layer 500; wherein, the insulating layer 440 is disposed on the surface of the polysilicon gate away from the drift region 100, and is insulated The orthographic projection of the layer 440 on the drift region 100 covers the orthographic projection of the polysilicon gate on the drift region 100 ; and the P ⁺ collector layer 500 is disposed on the side of the drift region 100 away from the P well region 200 . In this way, an IGBT with a more complete structure and function can be obtained, and the insulating layer 440 can fully protect the polysilicon gate during the manufacturing process or during use, so that the device stability of the heterojunction silicon carbide insulated gate transistor is better. .

According to the embodiment of the present invention, the specific material type for forming the insulated gate bipolar transistor is not particularly limited, and any IGBT substrate commonly used in the field can be used. Performance requirements are chosen accordingly. In some embodiments of the present invention, the material for forming the drift region 100, the P well region 200, the N ⁺ emitter 300 and the P ⁺ collector layer 500 can be Si, so that the long-term performance of the silicon-based IGBT Better stability, lower voltage and strong adaptability. In other embodiments of the present invention, the material for forming the drift region 100, the P well region 200, the N ⁺ emitter 300 and the P ⁺ collector layer 500 can be SiC, so that the silicon carbide insulated gate bipolar transistor Better withstand voltage performance, higher current and higher voltage.

According to an embodiment of the present invention, referring to FIG. 3 , the distance from the surface A of the N-type sub-gate 431 close to the P-type sub-gate 432 to the bottom wall B of the trench 410 is smaller than that from the surface C to the surface C of the P well region 200 close to the drift region 100. The distance of the bottom wall B of the trench 410 can ensure that the P-type sub-gate 432 is lower than the p-well region 200, so that the polysilicon gate composed of the N-type sub-gate 431 and the P-type sub-gate 432 can be more Fine control of conductance modulation effects.

According to the embodiment of the present invention, the specific doping concentration of the N-type sub-gate 431 and the P-type sub-gate 432 is not particularly limited, as long as the doping concentration of the concentration can make the polysilicon gate form a PN junction. Those skilled in the art can make corresponding adjustments according to the actual effect of shortening the turn-on time of the PN junction. In some embodiments of the present invention, the doping concentration of the N-type sub-gate can be greater than 1*10 ¹⁸ /cm ³ , and the doping concentration of the P-type sub-gate can be less than 5*10 ¹⁷ /cm ³ . Make the depletion region between the N-type sub-gate 431 and the P-type sub-gate 432 expand to the P-type sub-gate 432 more, and ensure that the depletion region is lower than the p-well region 200, thereby ensuring the turn-on of the IGBT reliability.

According to an embodiment of the present invention, referring to FIG. 3 , the drift region 100 (not shown in the figure) may include two first drift regions 110 and second drift regions 120, wherein the first drift region 110 is in contact with the trench 410, The second drift region 120 is disposed between the two first drift regions 110 , and the material forming the second drift region 120 is obtained by processing the material of the first drift region 110 through low mobility. It should be noted that “low mobility treatment” herein specifically refers to a treatment method that reduces the mobility of electrons and holes in the semiconductor material, and “contact” specifically refers to the contact between the first drift region 110 and the trench 410. No other structures and are directly connected.

The inventors of the present invention have found through in-depth research that the drift region 100 can also be divided into a first drift region 110 and a second drift region 120, so that when the IGBT is turned on, the first drift region 110 as a common drift region can be electron , The drift of the hole provides a channel with a small resistance without affecting the turn-on voltage drop of the IGBT; when the IGBT is turned off, it acts as the second drift region of the drift region with low mobility (that is, the life of holes and electrons is short) 120 can accelerate the recombination speed of electrons and holes, thereby shortening the turn-off time of the IGBT, thereby reducing the turn-off power consumption of the IGBT.

According to the embodiment of the present invention, the specific method of low mobility treatment is not particularly limited, and those skilled in the art can make a corresponding selection according to the specific substrate type of the IGBT. In some embodiments of the present invention, for Si-based or SiC materials, the low-mobility treatment method can be electron radiation or ion bombardment, so that the second drift can be quickly and efficiently reduced by using the above-mentioned low-mobility treatment method The mobility of electrons and holes in region 120.

According to the embodiment of the present invention, the specific width of each trench 410, the first drift region 110 and the second drift region 120 in the IGBT is not particularly limited, as long as the first drift region 110 can communicate with the trench It only needs to be in contact with the trench 410 and the second drift region 120 is not in contact with the trench 410 , and those skilled in the art can adjust accordingly according to the actual turn-off time of the IGBT. In some embodiments of the present invention, the width of the trench 410 may be 1.5 microns, the width of the first drift region 110 may be 5 microns, and the width of the second drift region 120 may be 2 microns. Thus, for a size of 10 microns The insulated gate bipolar transistor can obtain good dynamic performance and static performance at the same time.

According to an embodiment of the present invention, referring to FIG. 4 , the drift region 100 (not shown in the figure) may further include a plurality of second drift regions 120 and a plurality of third drift regions 130, wherein the plurality of second drift regions 120 and A plurality of third drift regions 130 are distributed alternately between the two first drift regions 100, and the material of the third drift regions 130 is the same as that of the first drift regions 110, so that the low mobility drifts distributed at intervals The region can also speed up the recombination speed of electrons and holes when turned off, and the third drift region 130 between the second drift region 120 can further ensure the overall stability of the conduction voltage drop when turned on. It should be noted that "multiple" herein specifically refers to two or more.

According to the embodiment of the present invention, the specific width ratio of the second drift region 120 and the third drift region 130 in the IGBT is not particularly limited, and those skilled in the art can make The off time is adjusted accordingly. In some embodiments of the present invention, for the case where the width of the trench is 1.5 microns and the width of the first drift region 110 is 5 microns, the widths of the second drift region 120 and the third drift region 130 can both be 0.3 microns, In this way, better dynamic performance and static performance can be obtained simultaneously for the IGBT with a size of 0 micron.

According to the embodiment of the present invention, the specific depth of each trench 410 is not particularly limited, specifically, for example, 6.5 microns, etc., and those skilled in the art can design accordingly according to the specific thickness of the P-well region 200, which will not be repeated here. repeat. According to the embodiment of the present invention, the specific spacing between the two trenches 410 is not particularly limited, for example, 5.5 microns, etc., and those skilled in the art can make corresponding adjustments according to the specific electrical performance requirements of the IGBT. design, and will not be repeated here.

According to the embodiment of the present invention, the specific thickness of the trench oxide layer 420 is not particularly limited, for example, 0.15 microns, and those skilled in the art can design accordingly according to the specific electrical performance requirements of the IGBT. I won't repeat them here. According to the embodiment of the present invention, the specific material of the trench oxide layer 420 is not particularly limited, such as silicon dioxide, etc., and those skilled in the art can perform corresponding oxidation according to the specific type of substrate, which will not be repeated here. repeat.

According to the embodiment of the present invention, the specific thickness of the P-well region 200 is not particularly limited, for example, 2.8 microns, etc. Those skilled in the art can design correspondingly according to the specific thickness of the P-well region, which will not be repeated here. According to the embodiment of the present invention, the specific thickness of the N ⁺ emitter 300 is not particularly limited, specifically, for example, 0.5 microns, etc., and those skilled in the art can design accordingly according to the specific thickness of the P well region, which will not be repeated here. repeat. According to the embodiment of the present invention, the specific thickness of the drift region 100 is not particularly limited, for example, 70 microns, etc., those skilled in the art can design accordingly according to the specific electrical performance requirements of the IGBT, I won't repeat them here. According to the embodiment of the present invention, the specific thickness of the P ⁺ collector layer 500 is not particularly limited, specifically, for example, 0.5 microns, etc., and those skilled in the art can make corresponding calculations according to the specific electrical performance requirements of the insulated gate bipolar transistor. design, and will not be repeated here.

According to the embodiment of the present invention, the specific doping concentration of the drift region 100, the P well region 200, the N ⁺ emitter 300 and the P ⁺ collector layer 500 are not particularly limited, for example, the doping concentration of the drift region 100 can be 1.5*10 ¹⁴ /cm ³ , the doping concentration of the P well region 200 can be 4*10 ¹⁶ /cm ³ , the doping concentration of the N ⁺ emitter 300 can be 5*10 ¹⁹ /cm ³ or the doping concentration of the P ⁺ set The doping concentration can be 1.5*10 ¹⁴ /cm ³ , the doping concentration of the electrode layer 500 can be 8*10 ¹⁷ /cm ³ , etc., and those skilled in the art can according to the actual electrical current of the IGBT The performance is adjusted accordingly, which will not be repeated here.

To sum up, according to the embodiments of the present invention, the present invention proposes an insulated gate bipolar transistor, the gate of which is a PN junction composed of an N-type sub-gate and a P-type sub-gate, thus reducing the The parasitic capacitance Cgc between the gate and the collector shortens the turn-on time of the IGBT without increasing the turn-on voltage drop, thereby reducing the turn-on loss of the IGBT.

In describing the present invention, it should be understood that the terms "center", "longitudinal", "transverse", "length", "width", "thickness", "upper", "lower", "front", " Back", "Left", "Right", "Vertical", "Horizontal", "Top", "Bottom", "Inner", "Outer", "Clockwise", "Counterclockwise", "Axial" , "radial", "circumferential" and other indicated orientations or positional relationships are based on the orientations or positional relationships shown in the drawings, which are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying the referred device or Elements must have certain orientations, be constructed and operate in certain orientations, and therefore should not be construed as limitations on the invention.

In addition, the terms "first", "second", and "third" are used for descriptive purposes only, and cannot be interpreted as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, features defined as "first", "second", and "third" may explicitly or implicitly include at least one of these features. In the description of the present invention, "plurality" means at least two, such as two, three, etc., unless otherwise specifically defined.

In the description of this specification, descriptions referring to the terms "one embodiment", "some embodiments", "example", "specific examples", or "some examples" mean that specific features described in connection with the embodiment or example , structure, material or characteristic is included in at least one embodiment or example of the present invention. In this specification, the schematic representations of the above terms are not necessarily directed to the same embodiment or example. Furthermore, the described specific features, structures, materials or characteristics may be combined in any suitable manner in any one or more embodiments or examples. In addition, those skilled in the art can combine and combine different embodiments or examples and features of different embodiments or examples described in this specification without conflicting with each other.

Although the embodiments of the present invention have been shown and described above, it can be understood that the above embodiments are exemplary and should not be construed as limiting the present invention, those skilled in the art can make the above-mentioned The embodiments are subject to changes, modifications, substitutions and variations.

Claims (10)

1. a kind of insulated gate bipolar transistor, which is characterized in that including：

Drift region；

The side in the drift region is arranged in p-well region, the p-well region；

N⁺Emitter, the N⁺Emitter is arranged in side of the p-well region far from the drift region；

Two grooves, each groove are opened in the N⁺In emitter, the p-well region and the drift region, and through described N⁺Emitter and the p-well region；

Trench oxide layer, the trench oxide layer are arranged in described two grooves, and cover the surface of each groove；

Two polysilicon gates, each polysilicon gate are filled in one of the trench oxide layer far from the drift region Side, also, each polysilicon gate includes the sub- grid of N-type being cascading and the sub- grid of p-type.

2. insulated gate bipolar transistor according to claim 1, which is characterized in that further comprise：

Insulating layer, the insulating layer is arranged on surface of the polysilicon gate far from the drift region, and the insulating layer exists Orthographic projection on the drift region covers orthographic projection of the polysilicon gate on the drift region；

P⁺Collector layer, the P⁺Collector layer is arranged in side of the drift region far from the p-well region.

3. insulated gate bipolar transistor according to claim 2, which is characterized in that form the drift region, the p-well Area, the N⁺Emitter and the P⁺The material of collector layer includes being selected from least one of Si and SiC.

4. insulated gate bipolar transistor according to claim 1, which is characterized in that the sub- grid of N-type is close to the P The distance of the surface of type grid to the bottom wall of the groove be less than the p-well region close to the drift region surface to the ditch The distance of the bottom wall of slot.

5. insulated gate bipolar transistor according to claim 1, which is characterized in that the doping of the sub- grid of N-type is dense Degree is more than 1*10¹⁸/cm³, the doping concentration of the sub- grid of p-type is less than 5*10¹⁷/cm³。

6. insulated gate bipolar transistor according to any one of claims 1 to 5, which is characterized in that the drift region Including：

Two the first drift regions, first drift region and the trench contact；

Second drift region, second drift region are arranged between described two first drift regions, and form second drift The material in area is to be handled by low mobility the material of first drift region to obtain.

7. insulated gate bipolar transistor according to claim 6, which is characterized in that the method for the low mobility processing Including electron radiation and ion bombardment.

8. insulated gate bipolar transistor according to claim 6, which is characterized in that the width of the groove is 1.5 micro- Rice, and the width of first drift region is 5 microns, the width of second drift region is 2 microns.

9. insulated gate bipolar transistor according to claim 6, which is characterized in that the drift region includes multiple described Second drift region and multiple third drift regions, the multiple second drift region and the multiple third drift region are described two the It distributes alternately between one drift region, and the material identical of the material of the third drift region and first drift region.

10. insulated gate bipolar transistor according to claim 9, which is characterized in that the width of the groove is 1.5 micro- The width of rice, first drift region is 5 microns, and the width of second drift region and the third drift region is all 0.3 Micron.