CN108336152A - Groove-shaped silicon carbide SBD device with floating junction and its manufacturing method - Google Patents
Groove-shaped silicon carbide SBD device with floating junction and its manufacturing method Download PDFInfo
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- 238000007667 floating Methods 0.000 title claims abstract description 33
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 13
- 229910052751 metal Inorganic materials 0.000 claims abstract description 41
- 239000002184 metal Substances 0.000 claims abstract description 41
- 238000005468 ion implantation Methods 0.000 claims abstract description 32
- 238000002955 isolation Methods 0.000 claims abstract description 26
- 239000000758 substrate Substances 0.000 claims abstract description 24
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 40
- 239000000463 material Substances 0.000 claims description 36
- 238000000034 method Methods 0.000 claims description 25
- 229910052681 coesite Inorganic materials 0.000 claims description 20
- 229910052906 cristobalite Inorganic materials 0.000 claims description 20
- 239000000377 silicon dioxide Substances 0.000 claims description 20
- 235000012239 silicon dioxide Nutrition 0.000 claims description 20
- 229910052682 stishovite Inorganic materials 0.000 claims description 20
- 229910052905 tridymite Inorganic materials 0.000 claims description 20
- 239000004020 conductor Substances 0.000 claims description 14
- 150000002500 ions Chemical class 0.000 claims description 6
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 6
- 229920005591 polysilicon Polymers 0.000 claims description 6
- 238000005530 etching Methods 0.000 claims description 5
- 229910052804 chromium Inorganic materials 0.000 claims description 4
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- 229910052782 aluminium Inorganic materials 0.000 claims description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 3
- 238000011049 filling Methods 0.000 claims description 3
- 239000000203 mixture Substances 0.000 claims description 3
- 238000000407 epitaxy Methods 0.000 claims 1
- 230000004888 barrier function Effects 0.000 abstract description 19
- 230000015556 catabolic process Effects 0.000 abstract description 7
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- 238000005229 chemical vapour deposition Methods 0.000 description 7
- 229920002120 photoresistant polymer Polymers 0.000 description 5
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- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 239000000969 carrier Substances 0.000 description 3
- 230000005684 electric field Effects 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 230000003647 oxidation Effects 0.000 description 3
- 238000007254 oxidation reaction Methods 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 238000000137 annealing Methods 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 2
- 230000017525 heat dissipation Effects 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 239000002210 silicon-based material Substances 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
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- 230000005855 radiation Effects 0.000 description 1
- 238000004151 rapid thermal annealing Methods 0.000 description 1
- 238000011084 recovery Methods 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
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Abstract
本发明涉及一种具有浮动结的沟槽型碳化硅SBD器件及其制造方法,属于半导体器件技术领域,包含碳化硅衬底(101)、第一外延层(201)、P型离子注入区(203)、第二外延层(301)、沟槽结构(302)、终端区绝缘介质隔离层(401),肖特基金属层(501)及金属电极(502);所述碳化硅衬底(101)、第一外延层(201)、第二外延层(301)和肖特基金属层(501)自下而上依次层叠设置,所述P型离子注入区(203)呈一定间隔嵌入在第一外延层(201)的上表面,所述P型离子注入区(203)与第一外延层(201)的上表面齐平且与所述第二外延层(301)的下表面接触。本发明具有在不影响器件导通电流的情况下,最大程度地提高现有肖特基势垒二极管结构的反向击穿电压的优点。
The invention relates to a trench-type silicon carbide SBD device with a floating junction and a manufacturing method thereof, belonging to the technical field of semiconductor devices, comprising a silicon carbide substrate (101), a first epitaxial layer (201), and a P-type ion implantation region ( 203), the second epitaxial layer (301), the trench structure (302), the terminal area insulating dielectric isolation layer (401), the Schottky metal layer (501) and the metal electrode (502); the silicon carbide substrate ( 101), the first epitaxial layer (201), the second epitaxial layer (301) and the Schottky metal layer (501) are stacked sequentially from bottom to top, and the P-type ion implantation region (203) is embedded in a certain interval On the upper surface of the first epitaxial layer (201), the P-type ion implantation region (203) is flush with the upper surface of the first epitaxial layer (201) and in contact with the lower surface of the second epitaxial layer (301). The invention has the advantage of maximally improving the reverse breakdown voltage of the existing Schottky barrier diode structure without affecting the conduction current of the device.
Description
技术领域technical field
本发明属于半导体器件技术领域,涉及一种具有浮动结的沟槽型碳化硅SBD器件及其制造方法。The invention belongs to the technical field of semiconductor devices, and relates to a trench type silicon carbide SBD device with a floating junction and a manufacturing method thereof.
背景技术Background technique
双极型器件由于具有少数载流子的电导率调制作用而使其具有较低的导通电阻,但是同样由于其结构内过剩载流子的存在,而导致这种器件具有较低的开关频率和较高的开关损耗,限制了双极型器件在高开关频率场合的应用。然而,单极型器件由于其结构内部没有少数载流子进行电导率的调制,其开关频率远远高于双极型器件,在高开关频率电路中有着广泛的应用。Bipolar devices have lower on-resistance due to conductivity modulation by minority carriers, but also have lower switching frequencies due to the presence of excess carriers in their structure And higher switching losses limit the application of bipolar devices in high switching frequency occasions. However, the switching frequency of unipolar devices is much higher than that of bipolar devices because there are no minority carriers in its structure to modulate the conductivity, and it is widely used in high switching frequency circuits.
对硅材料而言,由于其较低的禁带宽度和热导率,适用于较低压电路系统。碳化硅材料因其禁带宽度更大(约是Si的3倍),临界击穿电场更强(约是Si的10倍),热导率更高(约是Si的3倍)等优势在功率电子领域具有更大的应用优势。使用碳化硅材料制作的器件,其漏电流要比硅的小几个数量级,因此碳化硅器件可以在500℃以上的高温环境中工作,并具有良好的抗辐射能力。由于碳化硅材料比硅有更大的禁带宽度,使得碳化硅器件在同样的耐压前提下,器件的漂移区长度对硅更小,大幅降低了器件的导通电阻。碳化硅材料更大的热导率也使得器件的散热性更好,即使在高温环境下工作,也无需额外的散热装置,大大缩小了系统的体积和成本。因此,碳化硅材料是制造高温、大功率、高电压、低功耗电子器件的理想材料,在电力电子中有着广阔的应用情景。For silicon material, due to its lower band gap and thermal conductivity, it is suitable for lower voltage circuit system. Silicon carbide material has the advantages of larger bandgap (about 3 times that of Si), stronger critical breakdown electric field (about 10 times that of Si), and higher thermal conductivity (about 3 times that of Si). The field of power electronics has greater application advantages. The leakage current of devices made of silicon carbide materials is several orders of magnitude smaller than that of silicon, so silicon carbide devices can work in high temperature environments above 500°C and have good radiation resistance. Since the silicon carbide material has a larger band gap than silicon, the drift region length of the silicon carbide device is smaller than that of silicon under the same withstand voltage, which greatly reduces the on-resistance of the device. The greater thermal conductivity of silicon carbide material also makes the device have better heat dissipation. Even if it works in a high temperature environment, no additional heat dissipation device is needed, which greatly reduces the size and cost of the system. Therefore, silicon carbide materials are ideal materials for manufacturing high-temperature, high-power, high-voltage, and low-power electronic devices, and have broad application scenarios in power electronics.
碳化硅材料通常使用外延技术生长,由于材料的特殊性,目前碳化硅材料的生长技术还远不及硅材料成熟,且在生长得到的碳化硅材料都比较薄,厚的碳化硅材料由于技术的原因通常存在较多的缺陷,严重影响了器件的性能。在器件中引入浮动结结构可以在同一掺杂浓度及厚度的条件下将器件的耐压提高近一倍左右,是解决以上问题的关键,在近几年的功率器件领域得到了广泛的关注。Silicon carbide materials are usually grown using epitaxial technology. Due to the particularity of the material, the current growth technology of silicon carbide materials is far less mature than that of silicon materials, and the silicon carbide materials obtained during growth are relatively thin. Thick silicon carbide materials are due to technical reasons. There are usually more defects, which seriously affect the performance of the device. Introducing a floating junction structure into the device can nearly double the withstand voltage of the device under the same doping concentration and thickness, which is the key to solving the above problems, and has received extensive attention in the field of power devices in recent years.
浮动结碳化硅肖特基二极管兼具了传统肖特基二极管低压降、大电流特性的同时,比传统肖特基二极管具有更高的反向击穿电压。关注到,申请号为“201410166386.3”专利提出的“基于外延工艺的沟槽式浮动结碳化硅SBD器件及其制造方法”中,虽然该结构也采用了浮动结+沟槽结构的SBD器件,但是其设计缺陷是明显的。该发明在浮岛上方采用金属填充沟槽,虽然起到增大电极接触面积的作用,但是由于浮岛的存在,限制了电流的通路面积,因此这种设计并不能增加器件的导通电流。同时,使用金属填充沟槽时,沟槽内的金属与碳化硅材料仅形成肖特基接触,肖特基势垒与沟槽上表面的金属与碳化硅材料形成的肖特基势垒性质相同,这相当于减小了碳化硅材料的漂移层厚度,从而降低了器件的反向耐压。Floating junction silicon carbide Schottky diodes not only have the characteristics of low dropout and high current of traditional Schottky diodes, but also have higher reverse breakdown voltage than traditional Schottky diodes. It is noted that in the "trenched floating junction silicon carbide SBD device and its manufacturing method based on epitaxial process" proposed by the patent application number "201410166386.3", although the structure also uses a floating junction + trench structure SBD device, but Its design flaws are obvious. This invention uses metal to fill the trench above the floating island. Although it can increase the electrode contact area, the existence of the floating island limits the current path area, so this design cannot increase the on-current of the device. At the same time, when the trench is filled with metal, the metal in the trench and the silicon carbide material only form a Schottky contact, and the Schottky barrier is the same as that formed by the metal on the upper surface of the trench and the silicon carbide material. , which is equivalent to reducing the thickness of the drift layer of the silicon carbide material, thereby reducing the reverse withstand voltage of the device.
发明内容Contents of the invention
有鉴于此,本发明的目的在于提供一种具有浮动结的沟槽型碳化硅SBD器件及其制造方法,以解决在不影响器件导通电流的情况下,最大程度地提高现有肖特基势垒二极管结构的反向击穿电压。In view of this, the object of the present invention is to provide a trench type silicon carbide SBD device with a floating junction and a manufacturing method thereof, to solve the problem of maximizing the existing Schottky SBD without affecting the conduction current of the device. The reverse breakdown voltage of a barrier diode structure.
为达到上述目的,本发明提供如下技术方案:To achieve the above object, the present invention provides the following technical solutions:
具有浮动结的沟槽型碳化硅SBD器件,该器件包含碳化硅衬底101、第一外延层201、P型离子注入区203、第二外延层301、沟槽结构302、终端区绝缘介质隔离层401,肖特基金属层501及金属电极502;A trench-type silicon carbide SBD device with a floating junction, the device includes a silicon carbide substrate 101, a first epitaxial layer 201, a P-type ion implantation region 203, a second epitaxial layer 301, a trench structure 302, and a terminal area insulating dielectric isolation Layer 401, Schottky metal layer 501 and metal electrode 502;
所述碳化硅衬底101、第一外延层201、第二外延层301和肖特基金属层501自下而上依次层叠设置,所述P型离子注入区203呈一定间隔嵌入在第一外延层201的上表面,所述P型离子注入区203与第一外延层201的上表面齐平且与所述第二外延层301的下表面接触,;The silicon carbide substrate 101, the first epitaxial layer 201, the second epitaxial layer 301 and the Schottky metal layer 501 are stacked sequentially from bottom to top, and the P-type ion implantation region 203 is embedded in the first epitaxial layer at a certain interval. The upper surface of the layer 201, the P-type ion implantation region 203 is flush with the upper surface of the first epitaxial layer 201 and is in contact with the lower surface of the second epitaxial layer 301;
所述第二外延层301的两侧外表面与所述碳化硅衬底101和第一外延层201的两侧外表面齐平,所述沟槽结构302间隔一定距离嵌入在所述第二外延层301的上表面,且所述沟槽结构302在的位置与所述P型离子注入区203的位置一一对应;The outer surfaces on both sides of the second epitaxial layer 301 are flush with the outer surfaces on both sides of the silicon carbide substrate 101 and the first epitaxial layer 201, and the groove structure 302 is embedded in the second epitaxial layer at a certain distance. The upper surface of the layer 301, and the position of the trench structure 302 corresponds to the position of the P-type ion implantation region 203;
所述沟槽结构302内壁设置绝缘介质层304,所述绝缘介质层304内填充有导电材料305,所述沟槽结构302、绝缘介质层304和导电材料305的上表面均与所述第二外延层301的上表面齐平;The inner wall of the trench structure 302 is provided with an insulating dielectric layer 304, and the insulating dielectric layer 304 is filled with a conductive material 305. The upper surfaces of the trench structure 302, the insulating dielectric layer 304, and the conductive material 305 are all connected to the second The upper surface of the epitaxial layer 301 is flush;
所述终端区绝缘介质隔离层401设置在所述第二外延层301上表面的两侧,两侧的所述终端区绝缘介质隔离层401分别至少与一个所述沟槽结构302的上表面接触,所述金属电极502贴合在所述肖特基金属层501和终端区绝缘介质隔离层401的上表面,且所述金属电极502的两侧表面不超过所述终端区绝缘介质隔离层401的两侧表面。The terminal region insulating dielectric isolation layer 401 is disposed on both sides of the upper surface of the second epitaxial layer 301, and the terminal region insulating dielectric isolation layer 401 on both sides is in contact with at least one upper surface of the trench structure 302 respectively. , the metal electrode 502 is bonded to the upper surface of the Schottky metal layer 501 and the insulating dielectric isolation layer 401 in the terminal area, and the surfaces on both sides of the metal electrode 502 do not exceed the insulating dielectric isolation layer 401 in the terminal area surfaces on both sides.
进一步,所述碳化硅衬底101为N+型碳化硅导电衬底,其掺杂浓度为1×1019~1×1020cm-3。Further, the silicon carbide substrate 101 is an N + -type silicon carbide conductive substrate, and its doping concentration is 1×10 19 -1×10 20 cm −3 .
进一步,所述第一外延层201和第二外延层301均为N-型碳化硅外延层,所述第一外延层201的厚度为4~20μm,离子掺杂浓度为5×1014~1×1017cm-3,所述第二外延层301的厚度为5~20μm,掺杂浓度为5×1014~1×1017cm-3。Further, both the first epitaxial layer 201 and the second epitaxial layer 301 are N - type silicon carbide epitaxial layers, the thickness of the first epitaxial layer 201 is 4-20 μm, and the ion doping concentration is 5×10 14 ˜1 ×10 17 cm -3 , the thickness of the second epitaxial layer 301 is 5-20 μm, and the doping concentration is 5×10 14 -1×10 17 cm -3 .
进一步,所述P型离子注入区203的形状为圆形或方形,且注入离子为铝,注入浓度为1×1017~1×1019cm-3。Further, the shape of the P-type ion implantation region 203 is circular or square, and the implanted ions are aluminum, and the implantation concentration is 1×10 17 -1×10 19 cm −3 .
进一步,所述沟槽结构302的宽度为1~4μm,深度为1~5μm,所述绝缘介质层304采用SiO2制成,所述绝缘介质层304的厚度为50~500μm,除与所述终端区绝缘介质隔离层401接触的所述沟槽结构302外,其余所述沟槽结构302的宽度与所述P型离子注入区203的宽度相同,且所述沟槽结构302的俯视形状为矩形、五边形、五边以上的多边形及圆形中的一种或多种组合,所述沟槽结构的排列方式为等距排列、错位排列或者两种排列的混合。Further, the width of the trench structure 302 is 1-4 μm, and the depth is 1-5 μm. The insulating dielectric layer 304 is made of SiO2, and the thickness of the insulating dielectric layer 304 is 50-500 μm. Except for the trench structure 302 in contact with the insulating dielectric isolation layer 401, the width of the rest of the trench structure 302 is the same as the width of the P-type ion implantation region 203, and the top view shape of the trench structure 302 is rectangular , a pentagon, a polygon with more than five sides, and a circle, and the groove structure is arranged in an equidistant arrangement, a dislocation arrangement or a mixture of the two arrangements.
进一步,所述终端区绝缘介质隔离层401采用SiO2制成,所述终端区绝缘介质隔离层401覆盖的沟槽结构302至少一个,且所述终端区绝缘介质隔离层401所覆盖的沟槽结构302之间的间距以及宽度与覆盖区外的沟槽结构302之间的间距以及宽度不同。Further, the insulating dielectric isolation layer 401 in the terminal area is made of SiO2, at least one trench structure 302 covered by the insulating dielectric isolation layer 401 in the terminal area, and the trench structure covered by the insulating dielectric isolation layer 401 in the terminal area The spacing and width between the trench structures 302 outside the coverage area and the spacing and width between the trench structures 302 are different.
进一步,所述肖特基金属层501采用Ti、Pt、Ni、Cr、W、Mo或Co制成。Further, the Schottky metal layer 501 is made of Ti, Pt, Ni, Cr, W, Mo or Co.
具有浮动结的沟槽型碳化硅SBD器件的制造方法,该方法包含如下步骤:A method for manufacturing a trench-type silicon carbide SBD device with a floating junction, the method comprising the steps of:
S1:制备N+型碳化硅导电衬底;S1: Prepare N + type silicon carbide conductive substrate;
S2:在S1中的N+型碳化硅导电衬底的表面外延生长第一外延层,并于第一外延层表面设置若干个掩膜窗口,进行P型离子注入形成P型浮岛结构;S2: growing the first epitaxial layer epitaxially on the surface of the N + type silicon carbide conductive substrate in S1, and setting several mask windows on the surface of the first epitaxial layer, and performing P-type ion implantation to form a P-type floating island structure;
S3:除去步骤S2中的掩膜,并于第一外延层表面外延生长第二外延层;S3: removing the mask in step S2, and epitaxially growing a second epitaxial layer on the surface of the first epitaxial layer;
S4:在所述第二外延层表面设置若干个掩膜窗口并蚀刻形成若干个沟槽;S4: setting several mask windows on the surface of the second epitaxial layer and etching to form several grooves;
S5:除去步骤S4中的掩膜,在所述沟槽内设置介质层,并于所述沟槽内填充导电材料;S5: removing the mask in step S4, setting a dielectric layer in the trench, and filling the trench with a conductive material;
S6:除去步骤S5中第二外延层表面的介质层,露出碳化硅材料,在其表面生长绝缘介质层;S6: removing the dielectric layer on the surface of the second epitaxial layer in step S5, exposing the silicon carbide material, and growing an insulating dielectric layer on its surface;
S7:除去绝缘介质层中间区域材料直至露出第二外延层表面的碳化硅,并保留器件两端的绝缘介质层作为终端区,在所述第二外延层表面设置肖特基金属层,并设置正面电极层。S7: Remove the material in the middle region of the insulating dielectric layer until the silicon carbide on the surface of the second epitaxial layer is exposed, and retain the insulating dielectric layer at both ends of the device as a terminal area, set a Schottky metal layer on the surface of the second epitaxial layer, and set the front side electrode layer.
进一步,所述沟槽内介质层为SiO2,沟槽内填充导电材料为高掺杂的多晶硅。Further, the dielectric layer in the trench is SiO2, and the conductive material filled in the trench is highly doped polysilicon.
进一步,步骤S2中进行P型离子注入形成P型浮岛结构,其中注入能量范围为200keV~2MeV。Further, in step S2, P-type ion implantation is performed to form a P-type floating island structure, wherein the implantation energy ranges from 200keV to 2MeV.
本发明的有益效果在于:本发明通过在碳化硅材料内部引入P型离子掺杂浮动结结构,并结合沟槽结构,通过在沟槽内形成SiO2介质层将器件的方向电场分散于沟槽底部及浮动结位置,提高了器件的击穿电压,并通过在沟槽内填充多晶硅材料,使其与SiO2介质层另一侧的碳化硅材料形成平板电容器,增加了器件的软恢复特性。因此,本发明具有在不影响器件导通电流的情况下,最大程度地提高现有肖特基势垒二极管结构的反向击穿电压的优点。本发明结构和工艺步骤简单,效果显著,具有广阔的应用前景。The beneficial effect of the present invention is that: the present invention introduces a P-type ion-doped floating junction structure inside the silicon carbide material, and combines the trench structure, and disperses the directional electric field of the device at the bottom of the trench by forming a SiO2 dielectric layer in the trench And the position of the floating junction improves the breakdown voltage of the device, and by filling the trench with polysilicon material, it forms a plate capacitor with the silicon carbide material on the other side of the SiO2 dielectric layer, which increases the soft recovery characteristics of the device. Therefore, the present invention has the advantage of maximally improving the reverse breakdown voltage of the existing Schottky barrier diode structure without affecting the conduction current of the device. The invention has simple structure and process steps, remarkable effect and broad application prospect.
附图说明Description of drawings
为了使本发明的目的、技术方案和有益效果更加清楚,本发明提供如下附图进行说明:In order to make the purpose, technical scheme and beneficial effect of the present invention clearer, the present invention provides the following drawings for illustration:
图1为本发明SBD器件的结构示意图;Fig. 1 is the structural representation of SBD device of the present invention;
图2~图5为本发明提SBD器件结构中沟槽形状及排列方式示意图;Fig. 2~Fig. 5 is the schematic diagram of groove shape and arrangement mode in the structure of SBD device of the present invention;
图6~图14为本发明SBD器件的制作方法工艺步骤示意图;6 to 14 are schematic diagrams of the process steps of the manufacturing method of the SBD device of the present invention;
其中附图标记为:101碳化硅衬底,201第一外延层,202阻挡层,203P型离子注入区,301第二外延层,302沟槽结构,303掩膜层,304绝缘介质层,305导电材料,401终端区绝缘介质隔离层,501肖特基金属层,502金属电极。The reference numerals are: 101 silicon carbide substrate, 201 first epitaxial layer, 202 barrier layer, 203 P-type ion implantation region, 301 second epitaxial layer, 302 trench structure, 303 mask layer, 304 insulating dielectric layer, 305 Conductive material, 401 terminal area insulating dielectric isolation layer, 501 Schottky metal layer, 502 metal electrode.
具体实施方式Detailed ways
下面将结合附图,对本发明的优选实施例进行详细的描述。The preferred embodiments of the present invention will be described in detail below with reference to the accompanying drawings.
以下图1~图14为本实施例中提供的一种具有浮动结的沟槽型碳化硅SBD器件结构及简易制作方法。需要注意的是,以下图示仅以示意图方式说明本发明的基本构想,图中仅显示与本发明有关的组件而并非按照实际实施时的组件数目、形状及尺寸绘制。在实际实施时,各组件的形态、尺寸、数量及比例可根据需要随意改变,凡是熟悉此技术的人士,在没有脱离本发明所揭示的精神及技术思想下完成的一切等效修饰或改变,仍应由本发明的权利要求所涵盖。Figures 1 to 14 below show the structure and simple manufacturing method of a trench-type silicon carbide SBD device with a floating junction provided in this embodiment. It should be noted that the following figures are only schematic diagrams illustrating the basic idea of the present invention, and only components related to the present invention are shown in the figures, rather than drawn according to the number, shape and size of the components in actual implementation. In actual implementation, the shape, size, quantity and ratio of each component can be changed at will according to the needs. Those who are familiar with this technology can complete all equivalent modifications or changes without departing from the spirit and technical ideas disclosed in the present invention. should still be covered by the claims of the present invention.
如图1所示,本实施例提供的一种具有浮动结的沟槽型碳化硅SBD器件,碳化硅SBD器件包括:碳化硅衬底101,第一外延层201,形成于碳化硅衬底101的表面,阻挡层202,形成于第一外延层201的表面,P型离子注入区203,通过阻挡层202的阻挡,在第一外延层201中形成多个不连续的P型浮动结结构;第二外延层301,形成于第一外延层201的表面;掩膜层303,形成于第二外延层301表面;沟槽结构302,绝缘介质层304,形成于第二外延层301的表面及沟槽结构302表面;沟槽内填充导电材料305,形成于所述绝缘介质层304的外部;终端区绝缘介质隔离层401,形成于所述第二外延层301表面两侧终端区域。As shown in FIG. 1 , this embodiment provides a trench type silicon carbide SBD device with a floating junction. The silicon carbide SBD device includes: a silicon carbide substrate 101 , a first epitaxial layer 201 formed on the silicon carbide substrate 101 The surface of the barrier layer 202 is formed on the surface of the first epitaxial layer 201, and the P-type ion implantation region 203 forms a plurality of discontinuous P-type floating junction structures in the first epitaxial layer 201 through the barrier of the barrier layer 202; The second epitaxial layer 301 is formed on the surface of the first epitaxial layer 201; the mask layer 303 is formed on the surface of the second epitaxial layer 301; the trench structure 302 and the insulating dielectric layer 304 are formed on the surface of the second epitaxial layer 301 and The surface of the trench structure 302 ; the trench is filled with conductive material 305 and formed outside the insulating dielectric layer 304 ; the insulating dielectric isolation layer 401 in the termination area is formed in the termination regions on both sides of the surface of the second epitaxial layer 301 .
肖特基金属层501,形成于所述第二外延层301及填充后的沟槽结构302的表面;金属电极502,形成于所述终端区绝缘介质隔离层401及肖特基金属层501的表面。The Schottky metal layer 501 is formed on the surface of the second epitaxial layer 301 and the filled trench structure 302; the metal electrode 502 is formed on the terminal region insulating dielectric isolation layer 401 and the Schottky metal layer 501 surface.
在本发明实施例中,碳化硅衬底101为N+型碳化硅衬底,掺杂浓度为1×1019~1×1020cm-3,所述第一外延层201为碳化硅N-型,为N型轻掺杂;具体地,第一外延层201是在碳化硅衬底101面上通过外延生长形成,其掺杂浓度范围为5×1014~1×1017cm-3,外延生长厚度范围为4~20μm。In the embodiment of the present invention, the silicon carbide substrate 101 is an N + -type silicon carbide substrate with a doping concentration of 1×10 19 to 1×10 20 cm -3 , and the first epitaxial layer 201 is a silicon carbide N - type, which is N-type lightly doped; specifically, the first epitaxial layer 201 is formed by epitaxial growth on the surface of the silicon carbide substrate 101, and its doping concentration ranges from 5×10 14 to 1×10 17 cm -3 , The epitaxial growth thickness ranges from 4 to 20 μm.
阻挡层202为SiO2阻挡层,位于第一外延层201,通过热氧化或化学气相沉积(CVD)工艺形成。在本实施例中,阻挡层202厚度可根据P型离子注入能量进行相应调整,保证阻挡层202下无P型离子注入剂量。The barrier layer 202 is a SiO2 barrier layer located on the first epitaxial layer 201 and formed by thermal oxidation or chemical vapor deposition (CVD) process. In this embodiment, the thickness of the barrier layer 202 can be adjusted accordingly according to the P-type ion implantation energy to ensure that there is no P-type ion implantation dose under the barrier layer 202 .
进一步,P型离子注入区203的深度需根据实际操作中设计的电压要求进行调整,P型离子注入区203的深度范围为0.3~0.6μm,离子注入掺杂浓度为1×1017~1×1019cm-3,注入离子为铝。Furthermore, the depth of the P-type ion implantation region 203 needs to be adjusted according to the voltage requirements designed in actual operation. The depth of the P-type ion implantation region 203 ranges from 0.3 to 0.6 μm, and the doping concentration of the ion implantation is 1×10 17 to 1× 10 19 cm -3 , the implanted ions are aluminum.
第二外延层301为N-型碳化硅外延层,具体地,第二外延层301于第一外延层201表面外延生长形成,其掺杂浓度范围为5×1014~1×1017cm-3,外延生长厚度范围为4~20μm;第二外延层301上表面通过引入掩膜层303刻蚀形成具有沟槽形貌302,除去掩膜层303后,通过热氧化于第二外延层301表面及沟槽结构302表面形成绝缘介质层304,绝缘介质层304为SiO2,厚度为50~500nm;而后在沟槽内填充导电材料305,具体地,导电材料305为P型掺杂多晶硅材料。The second epitaxial layer 301 is an N - type silicon carbide epitaxial layer. Specifically, the second epitaxial layer 301 is formed by epitaxial growth on the surface of the first epitaxial layer 201, and its doping concentration ranges from 5×10 14 to 1×10 17 cm − 3. The epitaxial growth thickness ranges from 4 to 20 μm; the upper surface of the second epitaxial layer 301 is etched by introducing a mask layer 303 to form a groove shape 302, and after removing the mask layer 303, the second epitaxial layer 301 is thermally oxidized An insulating dielectric layer 304 is formed on the surface and the surface of the trench structure 302. The insulating dielectric layer 304 is SiO2 with a thickness of 50-500nm; then the trench is filled with a conductive material 305, specifically, the conductive material 305 is a P-type doped polysilicon material.
终端区绝缘介质隔离层401材料为SiO2,材料厚度为0.5~2μm;具体地,终端区绝缘介质层401位于终端区,具体宽度可根据设计要去确定。肖特基金属层501形成于第二外延层301表面,为与碳化硅材料形成肖特基势垒的金属材料,可以是Ti、Pt、Ni、Cr、W、Mo或Co,金属电极502,形成于所述终端区绝缘介质隔离层401及肖特基金属层501表面。The material of the insulating dielectric isolation layer 401 in the terminal area is SiO2, and the thickness of the material is 0.5-2 μm; specifically, the insulating dielectric layer 401 in the terminal area is located in the terminal area, and the specific width can be determined according to the design. The Schottky metal layer 501 is formed on the surface of the second epitaxial layer 301, and is a metal material that forms a Schottky barrier with the silicon carbide material, which can be Ti, Pt, Ni, Cr, W, Mo or Co, and the metal electrode 502, It is formed on the surface of the insulating dielectric isolation layer 401 and the Schottky metal layer 501 in the terminal area.
需要特别说明的是,以上沟槽结构302其形貌与第一外延层201中的P型离子注入区203结构在元胞区是一致的,它们的尺寸相同,排列方式可有多种。图2~5所示为沟槽结构302的形貌及排列方式示意图;作为示例,沟槽结构302俯视形状可以是矩形、五边形、五边以上的多边形及圆形中的一种或多种组合,所述沟槽结构排列方式可以是等距排列、错位排列及以上两种排列的混合。It should be noted that the shape of the above trench structure 302 is consistent with the structure of the P-type ion implantation region 203 in the first epitaxial layer 201 in the cell region, their dimensions are the same, and there are various arrangements. 2 to 5 are schematic diagrams showing the shape and arrangement of the trench structure 302; as an example, the top view shape of the trench structure 302 can be one or more of a rectangle, a pentagon, a polygon with more than five sides, and a circle. The arrangement of the groove structure can be equidistant arrangement, dislocation arrangement or a mixture of the above two arrangements.
如图6~图14所示,本例还提供一种具有浮动结的沟槽型碳化硅SBD器件制作方法,包括步骤:As shown in Figures 6 to 14, this example also provides a method for manufacturing a trench-type silicon carbide SBD device with a floating junction, including steps:
如图6所示,首先制备碳化硅衬底101,于所述碳化硅衬底101表面形成碳化硅第一外延层201。作为示例,第一外延层201的掺杂类型为N-型掺杂,掺杂浓度范围为5×1014~1×1017cm-3,外延层浓度的选取需要实际需求选定,外延层生长工艺为碳化硅外延生长工艺,外延温度范围为1550~1600℃,外延生长厚度为4~20μm。As shown in FIG. 6 , a silicon carbide substrate 101 is first prepared, and a first epitaxial layer 201 of silicon carbide is formed on the surface of the silicon carbide substrate 101 . As an example, the doping type of the first epitaxial layer 201 is N - type doping, and the doping concentration ranges from 5×10 14 to 1×10 17 cm -3 . The concentration of the epitaxial layer needs to be selected according to actual needs. The growth process is a silicon carbide epitaxial growth process, the epitaxial temperature range is 1550-1600° C., and the epitaxial growth thickness is 4-20 μm.
如图7所示,在第一外延层201表面生长一层阻挡层202,并在阻挡层开孔后进行P型离子注入,形成P型离子注入区203结构。作为示例,阻挡层202介质为SiO2,SiO2使用CVD工艺在第一外延层201表面沉积,并使用光刻工艺对SiO2进行刻蚀,然后进行P型离子注入工艺,注入能量范围为200keV~2MeV,而后在氮气氛围进行退火,退火温度为1050℃。As shown in FIG. 7 , a barrier layer 202 is grown on the surface of the first epitaxial layer 201 , and P-type ion implantation is performed after the barrier layer is opened to form a P-type ion implantation region 203 structure. As an example, the medium of the barrier layer 202 is SiO2, and SiO2 is deposited on the surface of the first epitaxial layer 201 using a CVD process, and the SiO2 is etched using a photolithography process, and then a P-type ion implantation process is performed, and the implantation energy ranges from 200keV to 2MeV. Then annealing is carried out in a nitrogen atmosphere, and the annealing temperature is 1050° C.
如图8、9所示,在第一外延层201表面生长碳化硅第二外延层301,并与第二外延层301表面刻蚀出沟槽结构302。作为示例,第二外延层201的掺杂类型为N-型掺杂,掺杂浓度范围为5×1014~1×1017cm-3,外延层浓度的选取需要实际需求选定,外延层生长工艺为碳化硅外延生长工艺,外延温度范围为1550~1600℃,外延生长厚度为5~20μm;沟槽结构使用蚀刻工艺刻蚀完成,其具体步骤如下:As shown in FIGS. 8 and 9 , a silicon carbide second epitaxial layer 301 is grown on the surface of the first epitaxial layer 201 , and a trench structure 302 is etched on the surface of the second epitaxial layer 301 . As an example, the doping type of the second epitaxial layer 201 is N - type doping, and the doping concentration ranges from 5×10 14 to 1×10 17 cm -3 . The concentration of the epitaxial layer is selected according to actual needs. The epitaxial layer The growth process is a silicon carbide epitaxial growth process, the epitaxial temperature range is 1550-1600 °C, and the epitaxial growth thickness is 5-20 μm; the trench structure is etched by etching process, and the specific steps are as follows:
在第二外延层301表面涂覆光刻胶并显影,在光刻胶层蚀刻出沟槽开口的长度和宽度,沟槽长度和宽度除终端区域外与P型离子注入区相等并位于P型离子注入区203正上方;Coat photoresist on the surface of the second epitaxial layer 301 and develop it, etch the length and width of the trench opening on the photoresist layer, the trench length and width are equal to the P-type ion implantation region except the terminal region and are located in the P-type Directly above the ion implantation area 203;
利用干法刻蚀工艺将无光刻胶覆盖的碳化硅材料刻蚀出沟槽形貌,沟槽宽度为1~4μm,深度为1~5μm,而后除去光刻胶。A dry etching process is used to etch the silicon carbide material without photoresist coverage to form grooves with a width of 1-4 μm and a depth of 1-5 μm, and then remove the photoresist.
如图10~12所示,在沟槽表面形成绝缘介质层304,而后填充导电材料305,并除去第二外延层301表面多余的材料,露出碳化硅材料。作为示例,所述沟槽结构表面绝缘介质层304为SiO2材料,通过碳化硅热氧化或化学气相沉积(CVD)工艺形成,SiO2材料厚度为50~500nm,所述导电材料305为P型掺杂多晶硅材料,采用CVD工艺填充;而后采用蚀刻或化学机械平坦化(CMP)方法除去第二外延层301表面的SiO2及多晶硅,露出碳化硅材料。As shown in FIGS. 10-12 , an insulating dielectric layer 304 is formed on the surface of the trench, and then filled with a conductive material 305 , and excess material on the surface of the second epitaxial layer 301 is removed to expose the silicon carbide material. As an example, the insulating dielectric layer 304 on the surface of the trench structure is made of SiO2 material, formed by silicon carbide thermal oxidation or chemical vapor deposition (CVD) process, the thickness of the SiO2 material is 50-500nm, and the conductive material 305 is P-type doped The polysilicon material is filled by CVD process; and then the SiO2 and polysilicon on the surface of the second epitaxial layer 301 are removed by etching or chemical mechanical planarization (CMP) to expose the silicon carbide material.
如图13、14所示,在所述第二外延层301表面形成终端区绝缘介质隔离层401,并保留两侧绝缘介质层作为终端,而后沉积肖特基金属层501和金属电极502;作为示例,所述绝缘介质层材料为SiO2,采用热氧化或CVD工艺生成;通过在终端区绝缘介质隔离层401表面涂覆光刻胶并将中间部分SiO2蚀刻掉,露出碳化硅材料,保留下来的SiO2作为终端区域绝缘层;而后利用金属溅射工艺在第二外延层的碳化硅表面沉积肖特基金属层501,利用快速热退火工艺使肖特基金属层与所述碳化硅材料反应形成肖特基势垒层,其中肖特基金属层材料可包含Ti、Pt、Ni、Cr、W、Mo或Co中的至少一种金属。进一步地,于所述肖特基势垒层501表面形成金属电极502,采用光刻掩膜的方法对金属电极502进行选择性刻蚀,形成正面电极。As shown in Figures 13 and 14, an insulating dielectric isolation layer 401 is formed on the surface of the second epitaxial layer 301, and the insulating dielectric layers on both sides are reserved as terminals, and then a Schottky metal layer 501 and a metal electrode 502 are deposited; as For example, the material of the insulating dielectric layer is SiO2, which is generated by thermal oxidation or CVD process; by coating photoresist on the surface of the insulating dielectric isolation layer 401 in the terminal area and etching away the middle part of SiO2, the silicon carbide material is exposed, and the remaining SiO2 is used as an insulating layer in the terminal region; then, a Schottky metal layer 501 is deposited on the silicon carbide surface of the second epitaxial layer by a metal sputtering process, and a Schottky metal layer 501 is reacted with the silicon carbide material by using a rapid thermal annealing process to form a Schottky metal layer. The Tertky barrier layer, wherein the material of the Schottky metal layer may contain at least one metal of Ti, Pt, Ni, Cr, W, Mo or Co. Further, a metal electrode 502 is formed on the surface of the Schottky barrier layer 501, and the metal electrode 502 is selectively etched by using a photolithography mask to form a front electrode.
如上所述,本发明通过引入浮动结结构与沟槽结构相结合的方式,PN结和沟槽结构将器件的电场分为两个部分来承担,在不影响器件导通电流的情况下,最大程度地提高现有肖特基势垒二极管结构的反向击穿电压,具有极高的应用价值。As mentioned above, the present invention introduces the combination of the floating junction structure and the trench structure. The PN junction and the trench structure divide the electric field of the device into two parts. Without affecting the conduction current of the device, the maximum The method improves the reverse breakdown voltage of the existing Schottky barrier diode structure to a certain extent, and has extremely high application value.
最后说明的是,以上优选实施例仅用以说明发明的技术方案而非限制,尽管通过上述优选实施例已经对本发明进行了详细的描述,但本领域技术人员应当理解,可以在形式上和细节上对其作出各种各样的改变,而不偏离本发明权利要求书所限定的范围。Finally, it should be noted that the above preferred embodiments are only used to illustrate the technical solutions of the invention and not limit them. Although the present invention has been described in detail through the above preferred embodiments, those skilled in the art should understand that it may be possible in form and details. Various changes can be made to it without departing from the scope defined by the claims of the present invention.
Claims (10)
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Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108682695A (en) * | 2018-08-07 | 2018-10-19 | 济南晶恒电子有限责任公司 | A kind of high current low forward voltage drop SiC schottky diode chip and preparation method thereof |
| CN109801958A (en) * | 2019-01-21 | 2019-05-24 | 厦门市三安集成电路有限公司 | A kind of silicon carbide trench schottky diode device and preparation method thereof |
| CN110581181A (en) * | 2019-09-24 | 2019-12-17 | 全球能源互联网研究院有限公司 | A kind of silicon carbide schottky diode and preparation method thereof |
| CN112397566A (en) * | 2019-08-15 | 2021-02-23 | 中兴通讯股份有限公司 | Silicon carbide device and preparation method thereof |
| CN113130625A (en) * | 2021-03-26 | 2021-07-16 | 先之科半导体科技(东莞)有限公司 | High-voltage rapid silicon carbide diode and production method thereof |
| CN113140639A (en) * | 2020-01-19 | 2021-07-20 | 珠海零边界集成电路有限公司 | Silicon carbide power diode and manufacturing method thereof |
| CN113394292A (en) * | 2021-06-02 | 2021-09-14 | 泰科天润半导体科技(北京)有限公司 | Deep Schottky power device with buried layer structure and preparation method thereof |
| CN114864388A (en) * | 2022-04-21 | 2022-08-05 | 西安电子科技大学 | Surrounding N + region floating junction power device based on epitaxial growth process and preparation method thereof |
| CN115188802A (en) * | 2022-09-08 | 2022-10-14 | 深圳芯能半导体技术有限公司 | Floating ring structure, manufacturing method and electronic device |
| CN120174487A (en) * | 2025-05-21 | 2025-06-20 | 青禾晶元(天津)半导体材料有限公司 | Silicon carbide composite substrate and preparation method and application thereof |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101221989A (en) * | 2007-01-11 | 2008-07-16 | 株式会社东芝 | SiC Schottky barrier semiconductor device |
| US20130307111A1 (en) * | 2010-01-05 | 2013-11-21 | Fuji Electric Co., Ltd. | Schottky barrier diode having a trench structure |
| CN103681783A (en) * | 2012-09-14 | 2014-03-26 | 三菱电机株式会社 | Silicon carbide semiconductor device |
| US20180013015A1 (en) * | 2014-02-10 | 2018-01-11 | Rohm Co., Ltd. | Schottky barrier diode and a method of manufacturing the same |
-
2018
- 2018-03-20 CN CN201810229695.9A patent/CN108336152A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101221989A (en) * | 2007-01-11 | 2008-07-16 | 株式会社东芝 | SiC Schottky barrier semiconductor device |
| US20130307111A1 (en) * | 2010-01-05 | 2013-11-21 | Fuji Electric Co., Ltd. | Schottky barrier diode having a trench structure |
| CN103681783A (en) * | 2012-09-14 | 2014-03-26 | 三菱电机株式会社 | Silicon carbide semiconductor device |
| US20180013015A1 (en) * | 2014-02-10 | 2018-01-11 | Rohm Co., Ltd. | Schottky barrier diode and a method of manufacturing the same |
Cited By (16)
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|---|---|---|---|---|
| CN108682695B (en) * | 2018-08-07 | 2023-12-22 | 济南晶恒电子有限责任公司 | High-current low-forward voltage drop silicon carbide Schottky diode chip and preparation method thereof |
| CN108682695A (en) * | 2018-08-07 | 2018-10-19 | 济南晶恒电子有限责任公司 | A kind of high current low forward voltage drop SiC schottky diode chip and preparation method thereof |
| CN109801958A (en) * | 2019-01-21 | 2019-05-24 | 厦门市三安集成电路有限公司 | A kind of silicon carbide trench schottky diode device and preparation method thereof |
| CN109801958B (en) * | 2019-01-21 | 2020-09-15 | 厦门市三安集成电路有限公司 | A kind of silicon carbide trench Schottky diode device and preparation method thereof |
| CN112397566A (en) * | 2019-08-15 | 2021-02-23 | 中兴通讯股份有限公司 | Silicon carbide device and preparation method thereof |
| CN110581181B (en) * | 2019-09-24 | 2024-04-26 | 全球能源互联网研究院有限公司 | A silicon carbide Schottky diode and a method for preparing the same |
| CN110581181A (en) * | 2019-09-24 | 2019-12-17 | 全球能源互联网研究院有限公司 | A kind of silicon carbide schottky diode and preparation method thereof |
| CN113140639A (en) * | 2020-01-19 | 2021-07-20 | 珠海零边界集成电路有限公司 | Silicon carbide power diode and manufacturing method thereof |
| CN113130625B (en) * | 2021-03-26 | 2021-11-12 | 先之科半导体科技(东莞)有限公司 | A kind of high-voltage fast silicon carbide diode and preparation method thereof |
| CN113130625A (en) * | 2021-03-26 | 2021-07-16 | 先之科半导体科技(东莞)有限公司 | High-voltage rapid silicon carbide diode and production method thereof |
| CN113394292A (en) * | 2021-06-02 | 2021-09-14 | 泰科天润半导体科技(北京)有限公司 | Deep Schottky power device with buried layer structure and preparation method thereof |
| CN113394292B (en) * | 2021-06-02 | 2025-08-12 | 泰科天润半导体科技(北京)有限公司 | Deep schottky power device with buried layer structure and preparation method thereof |
| CN114864388A (en) * | 2022-04-21 | 2022-08-05 | 西安电子科技大学 | Surrounding N + region floating junction power device based on epitaxial growth process and preparation method thereof |
| CN115188802A (en) * | 2022-09-08 | 2022-10-14 | 深圳芯能半导体技术有限公司 | Floating ring structure, manufacturing method and electronic device |
| CN120174487A (en) * | 2025-05-21 | 2025-06-20 | 青禾晶元(天津)半导体材料有限公司 | Silicon carbide composite substrate and preparation method and application thereof |
| CN120174487B (en) * | 2025-05-21 | 2025-09-09 | 青禾晶元(天津)半导体材料有限公司 | Silicon carbide composite substrate and its preparation method and application |
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