CN108200365A - A kind of CMOS is from zero circuit - Google Patents

Abstract

The invention discloses a CMOS self-returning zero circuit, which comprises a 0.5PF self-returning zero capacitance, a 1PF integral capacitance and two NMOS transistors for reducing the charge injection effect. When the auto-zero switches S1 and S2 are at high level, the circuit is in the reset period, and the amplifier offset voltage and noise voltage are stored on the auto-zero capacitor. S1‑controls the switch of the compensation tube to reduce the charge injection effect of the S1 switch. The amplifier adopts a one-stage folded cascode structure with differential input, which overcomes the disadvantage that the Miller compensation capacitor used in the traditional two-stage amplifier is easy to cause oscillation at a low temperature of 77K; It can work normally, and the noise is lower than that of the traditional circuit, and can be applied to the readout of the medium-wave linear infrared HgCdTe detector signal with large non-uniformity.

Description

A CMOS auto-return-to-zero circuit

technical field

The invention relates to a CMOS circuit, in particular to a CMOS self-returning zero circuit.

Background technique

Due to its unique advantages, the medium-wave HgCdTe infrared detector has extremely important uses in the field of national defense and aerospace, but it generally works under high background and will generate a large background current; at the same time, the medium-wave HgCdTe infrared device itself The dark current is also relatively large, and there is relatively large non-uniformity. When the signal is read out, the signal of each element is prone to unevenness, and some signals cannot be read out. In addition, the signal-to-noise ratio is also a key parameter of infrared detector components. A good signal-to-noise ratio is the basis for obtaining higher-resolution infrared images. In order to meet the application requirements of domestic aerospace engineering, it is required to consider non-uniformity while designing CMOS circuits. Auto-zero correction, at present, no CMOS auto-zero circuit for medium-wave HgCdTe infrared detectors has been reported in China. Foreign literature has not publicly reported articles on the specific circuit structure of the low-temperature CMOS auto-zeroing of the medium-wave HgCdTe infrared detector.

Because there is a voltage offset at the input of the amplifier in the detector readout circuit, a certain dark current will be generated, and a large dark current voltage will also be generated after integration. The dark current is not uniform between different detectors, which also greatly reduces the dynamic range of the system. For the non-uniformity of the dark current of the detector, on the one hand, it can be studied in the process of making the detector, but limited by the domestic process conditions, the problem of non-uniformity cannot be completely solved in the process, so it can only be solved in the readout circuit Do further research. It has been reported in relevant literature at home and abroad that adding a current suppression structure in the readout circuit can reduce the size of the dark current as a whole, but it cannot solve the problem of non-uniformity of the dark current of different detector elements. The self-returning method can effectively solve this problem. The auto-zero method is to collect the dark current signal of each element and store it on the corresponding sampling capacitor when there is no light, and use the newly collected signal and dark signal to subtract each other to read the real infrared signal when there is light. The offset voltage feedback compensation of the input stage of the circuit eliminates the bias voltage at both ends of the photosensitive element, makes the photosensitive element work at zero bias as much as possible, and suppresses the dark current.

Contents of the invention

The invention adopts the self-returning zero structure, which can effectively reduce the fixed image noise and 1/f noise caused by the dark current, improve the readout signal-to-noise ratio, and increase the dynamic range.

The auto-zero structure (Figure 1 and Figure 2) includes a 0.5pF auto-zero capacitor Caz and a 1pF integral capacitor Cint, NM16 and NM17 are two NMOS transistors that eliminate the charge injection effect, and their width-to-length ratio design It is 0.6μm/1μm. S1 and S2 are self-returning zero switches. When S1 and S2 are high level, the circuit is in the reset period, and the amplifier offset voltage and noise voltage can be stored on the self-returning zero capacitor Caz, and the tube controlled by S1- is a compensation tube, which can reduce the charge injection effect of the S1 switch. reset is to reset the integral switch, when reset is low level, it is the reset phase, and when reset is high level, it is the circuit integration phase.

The low-temperature differential amplifier module (Figure 3) adopts a differential input folded cascode structure amplifier circuit, M5, M6, M13, and M17 form a differential input cascode structure, and M16 and M18 are differential output active loads. M7 and M14 provide current sources for the cascode, bias1, bias2 and bias3 are bias voltage ports, and In- and In+ are positive and negative input terminals of the differential operational amplifier. Among them, the differential input pair tubes M5 and M6 use interdigital transistors to ensure up-down and left-right symmetry as much as possible, and a protective ring is used outside the input pair tubes (Figure 4);

It is characterized in that: CMOS low-temperature self-returning zero circuit, including a 0.5pF self-returning zero capacitor and a 1pF integrating capacitor, also includes two NMOS transistors to eliminate the charge injection effect. When the auto-zero switches S1 and S2 are at high level, the circuit is in the reset period, and the amplifier offset voltage and noise voltage can be stored on the auto-zero capacitor. S1- controls the switch of the compensation tube, which can reduce the charge injection of the S1 switch. effect. The amplifier adopts a one-stage folded cascode structure with differential input, which overcomes the disadvantage that the Miller compensation capacitor used in the traditional two-stage amplifier is easy to cause oscillation at a low temperature of 77K; the self-returning zero readout is between room temperature and low temperature 77K Can work normally, the noise is lower than the traditional readout circuit, and can be applied to the readout of the medium-wave linear infrared HgCdTe detector signal with large non-uniformity.

The advantages of the present invention are as follows:

1. The CMOS low-temperature auto-zero structure can effectively eliminate the non-uniformity of dark current between different picture elements, and increase the dynamic range of the readout circuit.

2. The CMOS low-temperature differential amplifier uses a cascode structure, and the power supply voltage suppression is relatively high, which reduces the noise introduced by the power supply ripple.

3. The CMOS low-temperature self-returning circuit can work normally from normal temperature 300K to low temperature 77K. It can not only be applied to the signal readout of medium-wave linear infrared HgCdTe detectors, but also can be used as other low-temperature detectors with mega-level internal resistance signal readout.

4. The CMOS low-temperature self-returning circuit is manufactured by standard sub-micron CMOS technology, which ensures the repeatability of chip manufacturing.

Description of drawings

Figure 1 is a schematic diagram of a CMOS auto-zero structure.

Figure 2 is a specific structure diagram of CMOS low-temperature auto-zeroing.

Figure 3 is a circuit diagram of a CMOS amplifier.

Figure 4 is a symmetrical layout of the CMOS input pair tube.

Figure 5 is a timing diagram of CMOS low temperature auto-zero operation.

Detailed ways

The specific embodiment of the present invention is described in further detail below in conjunction with accompanying drawing:

Example 1

Figure 1 is a schematic diagram of the CMOS self-returning zero structure. The work of this circuit is divided into two stages: the first is the sampling stage (S1 is closed, S2 is open). At this time, the output of the amplifier and the input negative terminal are short-circuited, so the input offset voltage is stored. On the capacitor Caz. The second is the amplification stage (S2 is off, S1 is on), and the sampled offset voltage is subtracted to obtain a voltage output without the influence of the offset voltage. The auto-zero circuit structure ensures that the voltage of the output voltage out is always the same voltage value at the initial stage of integration, eliminates the influence of offset voltage, and reduces the influence of fixed image noise and 1/f noise.

To achieve the ideal offset compensation of the input stage, it is necessary to compensate the clock feedthrough charge injection of the MOS switching capacitor of the auto-zero circuit. The non-uniformity of the output signal caused by the channel charge injection of the switch can be reduced or eliminated by proper switching timing.

Example 2

The specific structure of self-return to zero (Figure 2), including a 0.5pF self-return to zero capacitor Caz and a 1pF integral capacitor Cint, NM16 and NM17 are two NMOS transistors that eliminate the charge injection effect, and their width-to-length ratio is designed to be 0.6μm /1μm. S1 and S2 are self-returning zero switches.

When S1 and S2 are at high level, the circuit is in the reset stage, and the offset voltage and noise voltage of the amplifier can be stored on the auto-zero capacitor Caz, and the auto-zero compensation switch S1-can reduce the charge injection effect of the S1 switch. reset is to reset the integral switch, when the reset is low, it is the reset stage, and when the reset is high, it is the integral stage. To eliminate the charge injection effect, the aspect ratios of NM16 and NM17 are both designed to be 0.6 μm/1 μm. The other 9 tubes M0, M5, M6, M7, M13, M14, M16, M17, M18 form a differential cryogenic amplifier.

The reference dimensions of some pipes are shown in the table below (in microns).

tube NM16, NM17 NM14, NM14 PM2 M5, M6 M0 W/L 1/0.6 1.6/0.6 3.2/0.6 52/2 25/5

Example 3

The total noise of this differential input circuit (Figure 3) is mainly determined by the input tubes M5 and M6, and the equivalent input noise voltage calculation formula is:

(in )

The first term is channel thermal noise and the second term is 1/f noise.

g _m is the transconductance of the input tube. In order to reduce the total noise, the size of the input tube W/L and the design of the bias current are very important. From the above formula, it can be known that increasing g _m can reduce the thermal noise of the channel. Under the condition of area permitting, increasing the W/L of the input tube, and using a protective ring outside the input tube is beneficial to reduce the input tube. The offset and alien crosstalk come in noise. The 1/f noise of PMOS is smaller than that of NMOS, so the input tubes M5 and M6 choose PMOS to reduce the 1/f noise. In addition, increasing W×L can also reduce 1/f noise. Under the conditions of power consumption and area permitting, other tubes should also be designed with low noise standards in mind as much as possible. When the temperature decreases, the increase of the current and the increase of the threshold voltage V _T may make the device unable to work, so it should be fully considered when designing the W/L of each tube.

The cryogenic amplifier adopts a one-stage folded cascode structure with differential input. Among them, M5 and M6 are input pair tubes, M5, M6, M13, and M17 form a cascode structure for differential input, M16, M18 are active loads for differential output, and M7, M14 provide current sources for cascode, bias1 , bias2, bias3 are bias voltages, In-, In+ are the positive and negative input terminals of the differential operational amplifier. No passive resistors that are particularly sensitive to temperature are used in the circuit, so the circuit can work normally at room temperature and low temperature. The test results show that the current source has a strong ability to suppress the temperature, so the low-temperature CMOS self-returning zero circuit chip operates in the temperature range Very wide, it can work normally from normal temperature 300K to low temperature 77K.

The low-temperature CMOS auto-zero circuit adopts a one-stage folded cascode structure with differential input, and does not use a Miller compensation circuit. This structure overcomes the shortcoming that the conventional two-stage amplifier is easy to cause oscillation at low temperature.

Example 4

When drawing the layout of the amplifier, all pairs of tubes use interdigitated transistors, and try to ensure up-down and left-right symmetry, which can reduce the input offset of the CMOS differential operational amplifier at low temperature, especially the input tube of the differential amplifier, which is particularly important. In this circuit, since the differential input pair tube adopts a large tube of 1500μm/1.5μm, in order to achieve up-down and left-right symmetry, 72 41.7μm/1.5μm tubes are used to form the input pair tube when drawing the layout, as shown in Figure 4 It is shown that this greatly reduces the input offset of the entire differential operational amplifier, and the test results show that the input offset voltage of the low-temperature low-noise CMOS differential operational amplifier is very small, less than 1mV.

Example 5

Figure 5 is the CMOS low-temperature self-returning timing diagram. In the driving timing diagram, switch S1 is turned off 2μs earlier than S2, which can properly reduce the channel charge injection of the switch and affect the uniformity of the output signal. To avoid race hazards, the Vin high pulse must include a clock rising edge. We have carried out preliminary simulation on this circuit, when the offset voltage of the amplifier is increased to 200mV, the circuit can still work normally, and can achieve the effect of self-returning to zero. In the differential amplifier, the PMOS input tube is used to reduce the threshold loss to increase the output signal swing. The PMOS has lower flicker noise. In addition, the REF terminal is grounded to reduce the front-end noise introduced from the input ref terminal, effectively improving the signal of the system. noise ratio.

The CMOS low-temperature self-returning circuit can be applied to the signal of the medium-wave linear infrared HgCdTe detector, and can also be used as the readout of the signal of other low-temperature detectors with mega-level internal resistance.

Because the low-temperature CMOS auto-zero circuit adopts a folded cascode structure, the operating voltage range is large, and it can work normally between ±2.5 volts and ±1.2 volts, but it is necessary to consider that the difference in operating voltage leads to unit power consumption s difference.

The present invention has been described above through specific examples, but the present invention is not limited to these specific examples. Those skilled in the art should understand that various modifications, equivalent replacements, changes, etc. can also be made to the present invention. As long as these changes do not deviate from the spirit of the present invention, they should all be within the protection scope of the present invention.

Claims (1)

1. A CMOS auto-zero circuit is characterized in that: comprise a differential cryogenic amplifier, a 0.5pF auto-zero capacitor Caz, a 1pF integration capacitor Cint, auto-zero switches S1 and S2, auto-zero compensation switch S1-, reset the integral switch reset; it is characterized in that: The input terminal Vin of the auto-zero circuit is connected to the positive input terminal of the differential cryogenic amplifier through the auto-zero switch S2, and the input terminal Vin of the auto-zero circuit is connected to the negative input terminal of the differential low-temperature amplifier through the auto-zero capacitor Caz. The auto-zero switch S1 is connected across the negative input terminal and the output terminal of the differential cryogenic amplifier; The differential cryogenic amplifier adopts a folded cascode structure with differential input, M5, M6, M13, and M17 form a cascode structure with differential input, M16 and M18 are active loads for differential output, and M7 and M14 are Cascode current drive tube.