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CN108090250B - A method and system for assessing thermal damage to an integrated circuit package - Google Patents

A method and system for assessing thermal damage to an integrated circuit package Download PDF

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CN108090250B
CN108090250B CN201711188293.0A CN201711188293A CN108090250B CN 108090250 B CN108090250 B CN 108090250B CN 201711188293 A CN201711188293 A CN 201711188293A CN 108090250 B CN108090250 B CN 108090250B
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万毅
黄海隆
吴承文
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Abstract

本发明实施例公开了一种评估集成电路封装热损伤的方法，包括根据集成电路封装的热损伤度大小，确定依序排列的每一种热损伤度及其对应单向演变的转移概率，且根据转移概率设置热损伤状态转移概率矩阵及构成的热损伤状态分布初始评估模型；获取多个已测集成电路热损伤完全失效的时间，训练初始评估模型来得到最终评估模型；确定待测集成电路封装过程中所需的热损伤评估时间范围，根据最终评估模型，得到热损伤评估时间范围内每一天对应于待测集成电路封装过程中出现的各个热损伤状态分布概率。实施本发明，能把现有评估方法中的不确定性和模糊性特性转化为可靠精确的预测模型，降低封装失效率，从而提高设备的可靠性和安全性。

Figure 201711188293

The embodiment of the present invention discloses a method for evaluating thermal damage of an integrated circuit package. Set the thermal damage state transition probability matrix and the initial evaluation model of thermal damage state distribution formed according to the transition probability; obtain the time when the thermal damage of multiple tested integrated circuits completely fails, train the initial evaluation model to obtain the final evaluation model; determine the integrated circuit to be tested For the thermal damage assessment time range required in the packaging process, according to the final evaluation model, each day within the thermal damage assessment time range corresponds to the distribution probability of each thermal damage state that occurs during the packaging process of the integrated circuit to be tested. By implementing the invention, the uncertainty and ambiguity characteristics in the existing evaluation method can be transformed into a reliable and accurate prediction model, the packaging failure rate can be reduced, and the reliability and safety of the equipment can be improved.

Figure 201711188293

Description

一种评估集成电路封装热损伤的方法及系统A method and system for evaluating thermal damage to an integrated circuit package

技术领域technical field

本发明涉及集成电路封装技术领域，尤其涉及一种评估集成电路封装热损 伤的方法及系统。The present invention relates to the technical field of integrated circuit packaging, and in particular, to a method and system for evaluating thermal damage of integrated circuit packaging.

背景技术Background technique

叠层式封装技术是近年来发展起来的集成电路高密度新封装技术，虽然具 有优良的电气性能，但是在电路周期性通断和芯片热功率的作用下，高密度的 堆叠会导致集成电路封装内部裂纹的萌生和扩展，最终使集成电路封装失效。 由于叠层式封装热循环累积损伤是集成电路封装主要的失效模式，因此有必要 对叠层式封装累积的热损伤进行评估来降低封装失效率，确保集成电路设备应 用于航空、军事和机车等领域具有高可靠性和安全性。Stacked packaging technology is a new high-density integrated circuit packaging technology developed in recent years. Although it has excellent electrical performance, high-density stacking will lead to integrated circuit packaging due to the periodic on-off of the circuit and the thermal power of the chip. The initiation and expansion of internal cracks eventually make the integrated circuit package fail. Since the thermal cycle accumulated damage of the stacked package is the main failure mode of the integrated circuit package, it is necessary to evaluate the accumulated thermal damage of the stacked package to reduce the package failure rate and ensure that the integrated circuit equipment is used in aviation, military and locomotives, etc. The field has high reliability and security.

然而，由于集成电路叠层式封装内部结构微小，且在循环的热负载作用下， 其热－机械耦合关系非常复杂，是一个微观的动态过程，而且存在很强的不确 定性和模糊性，用常规的数学模型很难确立它的热损伤评估方法，迄今为止有 效的高密度叠层式封装热损伤评估和预测方法还没有建立。However, due to the tiny internal structure of the integrated circuit stacking package, and under the action of cyclic thermal load, its thermal-mechanical coupling relationship is very complex, it is a microscopic dynamic process, and there is strong uncertainty and ambiguity. It is difficult to establish its thermal damage assessment method with conventional mathematical models, so far an effective high-density stacked package thermal damage assessment and prediction method has not been established.

因此，亟需一种评估集成电路封装热损伤的方法，把高密度叠层式封装热 损伤评估具有不确定性和模糊性特性转化为可靠精确的预测模型，才能提高先 进电子设备的可靠性和安全性。Therefore, there is an urgent need for a method for evaluating thermal damage of integrated circuit packaging, which transforms the uncertain and fuzzy characteristics of thermal damage evaluation of high-density stacked packaging into a reliable and accurate prediction model, so as to improve the reliability and reliability of advanced electronic equipment. safety.

发明内容SUMMARY OF THE INVENTION

本发明实施例的目的在于提供一种评估集成电路封装热损伤的方法及系 统，能把现有评估方法中的不确定性和模糊性特性转化为可靠精确的预测模型， 降低封装失效率，从而提高设备的可靠性和安全性。The purpose of the embodiments of the present invention is to provide a method and system for evaluating thermal damage of an integrated circuit package, which can convert the uncertainty and ambiguity in the existing evaluation method into a reliable and accurate prediction model, reduce the package failure rate, and thereby Improve equipment reliability and safety.

为了解决上述技术问题，本发明实施例提供了一种评估集成电路封装热损 伤的方法，包括步骤：In order to solve the above-mentioned technical problems, an embodiment of the present invention provides a method for evaluating thermal damage of an integrated circuit package, comprising the steps of:

步骤S1、根据集成电路高密度叠层式封装过程中出现的热损伤度大小，确 定出依序排列的每一种热损伤度及其对应单向演变成下一种热损伤度的转移概 率，并将所述依序排列的每一种热损伤度作为相应的热损伤状态，且根据所述 依序排列的每一种热损伤度各自对应的转移概率，进一步设置热损伤状态转移 概率矩阵及其构成的热损伤状态分布初始评估模型；其中，所述依序排列的每 一种热损伤度各自对应的转移概率均相同；Step S1, according to the degree of thermal damage occurring in the high-density stacked packaging process of the integrated circuit, determine each thermal damage degree arranged in sequence and its corresponding one-way evolution to the transition probability of the next thermal damage degree, Taking each of the sequentially arranged thermal damage degrees as a corresponding thermal damage state, and further setting the thermal damage state transition probability matrix and The initial evaluation model of thermal damage state distribution formed by it; wherein, the corresponding transition probability of each thermal damage degree arranged in sequence is the same;

步骤S2、获取多个已测集成电路封装过程中热损伤完全失效的时间，并根 据所述获取到的多个已测集成电路过程中热损伤完全失效的时间，训练所述热 损伤状态分布初始评估模型，得到热损伤状态分布最终评估模型；Step S2: Obtain the time when the thermal damage completely fails in the packaging process of the multiple tested integrated circuits, and train the initial distribution of the thermal damage state according to the obtained time when the thermal damage completely fails in the multiple tested integrated circuits. Evaluate the model to obtain the final evaluation model of thermal damage state distribution;

步骤S3、确定待测集成电路封装过程中所需的热损伤评估时间范围，并进 一步根据所述热损伤状态分布最终评估模型，得到所述热损伤评估时间范围内 每一天对应于待测集成电路封装过程中出现的各个热损伤状态分布概率。Step S3: Determine the thermal damage evaluation time range required in the packaging process of the integrated circuit to be tested, and further according to the thermal damage state distribution final evaluation model, obtain the corresponding integrated circuit to be tested for each day within the thermal damage evaluation time range. The distribution probability of each thermal damage state that occurs during the packaging process.

其中，所述步骤S1具体包括：Wherein, the step S1 specifically includes:

确定集成电路高密度叠层式封装过程中出现的热损伤度大小有四种，并将 四种热损伤度从小到大进行排列，将四种热损伤度从小到大进行排列，并将所 述排列后的四种热损伤度作为四种热损伤状态，且进一步将所述排列后的热损 伤度分别对应单向演变成下一种热损伤度的转移概率设置为同一概率Pr；It is determined that there are four thermal damage degrees in the process of high-density stacked packaging of integrated circuits, and the four thermal damage degrees are arranged from small to large, and the four thermal damage degrees are arranged from small to large. The four thermal damage degrees after the arrangement are regarded as four thermal damage states, and further the transition probabilities of the thermal damage degrees after the arrangement corresponding to the one-way evolution to the next thermal damage degree are set as the same probability Pr ;

根据所述排列后的热损伤度分别对应单向演变成下一种热损伤度的转移概 率设置为同一概率Pr，设置热损伤状态转移概率矩阵According to the thermal damage degree after the arrangement, the transition probability corresponding to the one-way evolution to the next thermal damage degree is set as the same probability P r , and the thermal damage state transition probability matrix is set

Figure BDA0001480525360000021
Figure BDA0001480525360000021

根据所述热损伤状态转移概率矩阵

Figure BDA0001480525360000022
确定出热损伤状态分布初始评估模型
Figure BDA0001480525360000031
其中，St为t时刻集成电路封装过程中出现的热损伤状态分布，S0为集成电路封装 过程中初始的热损伤状态分布，且S0＝(1,0,0,0)T。According to the thermal damage state transition probability matrix
Figure BDA0001480525360000022
Determine the initial evaluation model of thermal damage state distribution
Figure BDA0001480525360000031
Wherein, S t is the distribution of thermal damage states occurring during the packaging process of the integrated circuit at time t, S 0 is the initial distribution of thermal damage states during the packaging process of the integrated circuit, and S 0 =(1,0,0,0) T .

其中，所述步骤S2具体包括：Wherein, the step S2 specifically includes:

获取N个已测集成电路封装过程中热损伤完全失效的时间t；其中，N为 正整数；Obtain the time t when the thermal damage completely fails in the packaging process of the N tested integrated circuits; wherein, N is a positive integer;

将热损伤完全失效的时间看作是一个服从正态分布的随机变量，根据公式

Figure BDA0001480525360000032
计算出热损伤完全失效的时间的均值tμ，并进一步根据公式
Figure BDA0001480525360000033
计算出热损伤完全失效的时间的方差
Figure BDA0001480525360000034
The time to complete failure of thermal damage is regarded as a random variable obeying a normal distribution, according to the formula
Figure BDA0001480525360000032
The mean value t μ of the time to complete failure of thermal damage is calculated, and further according to the formula
Figure BDA0001480525360000033
Calculate the variance of the time to complete failure of thermal damage
Figure BDA0001480525360000034

根据所述计算出的热损伤完全失效的时间的均值tμ，对公式

Figure BDA0001480525360000035
采用最小二乘法原则确定Pr的值为
Figure BDA0001480525360000036
并进一步根据所述确定的
Figure BDA0001480525360000037
得到热损伤状态分布最终评估模型According to the calculated mean value t μ of the time for complete failure of thermal damage, for the formula
Figure BDA0001480525360000035
Using the principle of least squares to determine the value of Pr
Figure BDA0001480525360000036
and further determined according to the
Figure BDA0001480525360000037
Obtain the final evaluation model of thermal damage state distribution

Figure BDA0001480525360000038
Figure BDA0001480525360000038

其中，所述四种热损伤状态包括A状态、B状态、C状态和D状态；其中，Wherein, the four thermal damage states include A state, B state, C state and D state; wherein,

所述A状态表示为集成电路高密度叠层式封装符合使用要求，热可靠性高， 没有发生热损伤，状态理想；The A state indicates that the integrated circuit high-density stacked package meets the requirements for use, has high thermal reliability, has no thermal damage, and is in an ideal state;

所述B状态表示为在电路周期性通断和芯片热功率的作用下，集成电路高 密度叠层式封装出现了蠕变和裂纹的萌生，热可靠性比所述A状态略低，但并 不影响使用和安全性，热可靠性有一定的保证；The B state is expressed as creep and crack initiation in the integrated circuit high-density stacked package under the action of the circuit periodic on-off and chip thermal power, and the thermal reliability is slightly lower than the A state, but not It does not affect the use and safety, and the thermal reliability is guaranteed to a certain extent;

所述C状态表示为在电路周期性通断和芯片热功率的作用下，在封装内部 出现交变的热应力，导致封装产生微小的裂纹，可能会给电子设备的安全性和 正常使用产生影响和带来隐患，有一定程度的热损伤，热可靠性存在问题；The C-state is expressed as the alternating thermal stress inside the package under the action of periodic on-off of the circuit and the thermal power of the chip, resulting in tiny cracks in the package, which may affect the safety and normal use of electronic equipment. And bring hidden dangers, there is a certain degree of thermal damage, thermal reliability problems;

所述D状态表示为在电路周期性通断和芯片热功率的作用下，在封装内部 出现交变的热应力集中，导致封装微小的裂纹逐渐汇合形成表面裂纹，然后不 断扩展直至整个封装不能承受交变热载荷的作用，发生热疲劳失效，造成整个 电子设备停止工作。The D state is represented by the alternating thermal stress concentration inside the package under the action of the periodic on-off of the circuit and the thermal power of the chip, which causes the tiny cracks in the package to gradually merge to form surface cracks, and then continue to expand until the entire package cannot withstand it. Under the action of alternating thermal loads, thermal fatigue failure occurs, causing the entire electronic equipment to stop working.

本发明实施例还提供了一种评估集成电路封装热损伤的系统，包括：Embodiments of the present invention also provide a system for evaluating thermal damage to an integrated circuit package, including:

模型初始单元，用于根据集成电路高密度叠层式封装过程中出现的热损伤 度大小，确定出依序排列的每一种热损伤度及其对应单向演变成下一种热损伤 度的转移概率，并将所述依序排列的每一种热损伤度作为相应的热损伤状态， 且根据所述依序排列的每一种热损伤度各自对应的转移概率，进一步设置热损 伤状态转移概率矩阵及其构成的热损伤状态分布初始评估模型；其中，所述依 序排列的每一种热损伤度各自对应的转移概率均相同；The initial unit of the model is used to determine each thermal damage degree in sequence and its corresponding one-way evolution to the next thermal damage degree according to the thermal damage degree that occurs in the process of high-density stacked packaging of integrated circuits. transition probability, and use each thermal damage degree arranged in sequence as a corresponding thermal damage state, and further set thermal damage state transition according to the respective transition probability corresponding to each thermal damage degree arranged in sequence The probability matrix and the initial evaluation model of thermal damage state distribution formed by it; wherein, the corresponding transition probabilities of each thermal damage degree arranged in sequence are the same;

模型校正单元，用于获取多个已测集成电路封装过程中热损伤完全失效的 时间，并根据所述获取到的多个已测集成电路过程中热损伤完全失效的时间， 训练所述热损伤状态分布初始评估模型，得到热损伤状态分布最终评估模型；The model calibration unit is used to obtain the complete failure time of thermal damage in the packaging process of the multiple tested integrated circuits, and train the thermal damage according to the obtained time when the thermal damage completely fails in the multiple measured integrated circuit processes The initial evaluation model of the state distribution is obtained, and the final evaluation model of the thermal damage state distribution is obtained;

评估单元，用于确定待测集成电路封装过程中所需的热损伤评估时间范围， 并进一步根据所述热损伤状态分布最终评估模型，得到所述热损伤评估时间范 围内每一天对应于待测集成电路封装过程中出现的各个热损伤状态分布概率。The evaluation unit is used to determine the thermal damage evaluation time range required in the packaging process of the integrated circuit to be tested, and further according to the thermal damage state distribution final evaluation model, obtain the thermal damage evaluation time range for each day corresponding to the test to be tested. The distribution probability of each thermal damage state that occurs during the IC packaging process.

其中，所述模型初始单元包括：Wherein, the model initial unit includes:

排列及概率设置模块，用于确定集成电路高密度叠层式封装过程中出现的 热损伤度大小有四种，将四种热损伤度从小到大进行排列，并将所述排列后的 四种热损伤度作为四种热损伤状态，且进一步将所述排列后的热损伤度分别对 应单向演变成下一种热损伤度的转移概率设置为同一概率Pr；The arrangement and probability setting module is used to determine the degree of thermal damage that occurs in the process of high-density stacked packaging of integrated circuits. There are four types of thermal damage degrees. The thermal damage degrees are used as four types of thermal damage states, and further the transition probabilities of the arranged thermal damage degrees corresponding to the one-way evolution to the next thermal damage degree are set as the same probability P r ;

概率矩阵设置模块，用于根据所述排列后的热损伤度分别对应单向演变成 下一种热损伤度的转移概率设置为同一概率Pr，设置热损伤状态转移概率矩阵The probability matrix setting module is used to set the transition probability corresponding to the one-way evolution to the next thermal damage degree to the same probability P r according to the arranged thermal damage degree, and set the thermal damage state transition probability matrix

Figure BDA0001480525360000051
Figure BDA0001480525360000051

模型初始设置模块，用于根据所述热损伤状态转移概率矩阵

Figure BDA0001480525360000052
确定出热损伤状态分布初始评估模型
Figure BDA0001480525360000053
其中，St为t时刻集成电路封装 过程中出现的热损伤状态分布，S0为集成电路封装过程中初始的热损伤状态分 布，且S0＝(1,0,0,0)T。Model initial setup module for transition probability matrix according to the thermal damage state
Figure BDA0001480525360000052
Determine the initial evaluation model of thermal damage state distribution
Figure BDA0001480525360000053
Wherein, S t is the distribution of thermal damage states occurring during the packaging process of the integrated circuit at time t, S 0 is the initial distribution of thermal damage states during the packaging process of the integrated circuit, and S 0 =(1,0,0,0) T .

其中，所述模型校正单元包括：Wherein, the model correction unit includes:

历史数据获取模块，用于获取N个已测集成电路封装过程中热损伤完全失 效的时间t；其中，N为正整数；The historical data acquisition module is used to acquire the time t when the thermal damage completely fails in the packaging process of the N tested integrated circuits; wherein, N is a positive integer;

均值及方差计算模块，用于将热损伤完全失效的时间看作是一个服从正态 分布的随机变量，根据公式

Figure BDA0001480525360000054
计算出热损伤完全失效的时间的均值tμ， 并进一步根据公式
Figure BDA0001480525360000055
计算出热损伤完全失效的时间的方差
Figure BDA0001480525360000056
The mean and variance calculation module is used to treat the time to complete failure of thermal damage as a random variable obeying a normal distribution, according to the formula
Figure BDA0001480525360000054
Calculate the mean value t μ of the time to complete failure of thermal damage, and further according to the formula
Figure BDA0001480525360000055
Calculate the variance of the time to complete failure of thermal damage
Figure BDA0001480525360000056

模型校正模块，用于根据所述计算出的热损伤完全失效的时间的均值tμ，对 公式

Figure BDA0001480525360000061
采用最小二乘法原则确定Pr的值 为
Figure BDA0001480525360000062
并进一步根据所述确定的
Figure BDA0001480525360000063
得到热损伤状态分布最终评估模型The model correction module is used for calculating the mean value t μ of the time when the thermal damage completely fails, and for the formula
Figure BDA0001480525360000061
Using the principle of least squares to determine the value of Pr
Figure BDA0001480525360000062
and further determined according to the
Figure BDA0001480525360000063
Obtain the final evaluation model of thermal damage state distribution

Figure BDA0001480525360000064
Figure BDA0001480525360000064

其中，所述四种热损伤状态包括A状态、B状态、C状态和D状态；其中，Wherein, the four thermal damage states include A state, B state, C state and D state; wherein,

所述A状态表示为集成电路高密度叠层式封装符合使用要求，热可靠性高， 没有发生热损伤，状态理想；The A state indicates that the integrated circuit high-density stacked package meets the requirements for use, has high thermal reliability, has no thermal damage, and is in an ideal state;

所述B状态表示为在电路周期性通断和芯片热功率的作用下，集成电路高 密度叠层式封装出现了蠕变和裂纹的萌生，热可靠性比所述A状态略低，但并 不影响使用和安全性，热可靠性有一定的保证；The B state is expressed as creep and crack initiation in the integrated circuit high-density stacked package under the action of the circuit periodic on-off and chip thermal power, and the thermal reliability is slightly lower than the A state, but not It does not affect the use and safety, and the thermal reliability is guaranteed to a certain extent;

所述C状态表示为在电路周期性通断和芯片热功率的作用下，在封装内部 出现交变的热应力，导致封装产生微小的裂纹，可能会给电子设备的安全性和 正常使用产生影响和带来隐患，有一定程度的热损伤，热可靠性存在问题；The C-state is expressed as the alternating thermal stress inside the package under the action of periodic on-off of the circuit and the thermal power of the chip, resulting in tiny cracks in the package, which may affect the safety and normal use of electronic equipment. And bring hidden dangers, there is a certain degree of thermal damage, thermal reliability problems;

所述D状态表示为在电路周期性通断和芯片热功率的作用下，在封装内部 出现交变的热应力集中，导致封装微小的裂纹逐渐汇合形成表面裂纹，然后不 断扩展直至整个封装不能承受交变热载荷的作用，发生热疲劳失效，造成整个 电子设备停止工作。The D state is represented by the alternating thermal stress concentration inside the package under the action of the periodic on-off of the circuit and the thermal power of the chip, which causes the tiny cracks in the package to gradually merge to form surface cracks, and then continue to expand until the entire package cannot withstand it. Under the action of alternating thermal loads, thermal fatigue failure occurs, causing the entire electronic equipment to stop working.

实施本发明实施例，具有如下有益效果：Implementing the embodiment of the present invention has the following beneficial effects:

本发明把集成电路高密度叠层式封装热损伤程度划分为多个状态，根据随 机理论和齐次状态链状态转移的无后效性原理，得出封装热损伤的状态转移概 率，进而构建封装热损伤状态转移概率矩阵，并基于热损伤状态转移概率矩阵 和封装在任何时刻的热损伤状态分布，建立了集成电路高密度叠层式封装热损 伤的精确评估模型，从而能把现有评估方法中的不确定性和模糊性特性转化为 可靠精确的预测模型，降低封装失效率，提高了设备的可靠性和安全性，具有 广泛的应用前景。The invention divides the degree of thermal damage of integrated circuit high-density stacked packaging into multiple states, and obtains the state transition probability of thermal damage of the package according to random theory and the principle of no aftereffect of homogeneous state chain state transition, and then constructs the package The thermal damage state transition probability matrix, and based on the thermal damage state transition probability matrix and the thermal damage state distribution of the package at any time, an accurate evaluation model for thermal damage of integrated circuit high-density stacked packaging is established, so that the existing evaluation methods can be used. Uncertainty and ambiguity in the device are transformed into a reliable and accurate prediction model, which reduces the packaging failure rate, improves the reliability and safety of the device, and has a wide range of application prospects.

附图说明Description of drawings

为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施 例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述 中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付 出创造性劳动性的前提下，根据这些附图获得其他的附图仍属于本发明的范畴。In order to explain the embodiments of the present invention or the technical solutions in the prior art more clearly, the following briefly introduces the accompanying drawings that need to be used in the description of the embodiments or the prior art. Obviously, the accompanying drawings in the following description are only These are some embodiments of the present invention, and for those of ordinary skill in the art, obtaining other drawings according to these drawings still belongs to the scope of the present invention without any creative effort.

图1为本发明实施例提供的一种评估集成电路封装热损伤的方法的流程图；1 is a flowchart of a method for evaluating thermal damage to an integrated circuit package provided by an embodiment of the present invention;

图2为本发明实施例提供的一种评估集成电路封装热损伤的方法中热损伤 状态单向转移的应用场景图；Fig. 2 is an application scenario diagram of one-way transfer of thermal damage state in a method for evaluating thermal damage of an integrated circuit package provided by an embodiment of the present invention;

图3为图2中用户a、b和c在非等距线性网络编码中断概率的理论值和模 拟值对比图。Fig. 3 is a comparison diagram of the theoretical value and the simulated value of the interruption probability of users a, b and c in the non-equidistant linear network coding in Fig. 2 .

具体实施方式Detailed ways

为了使本发明的目的、技术方案及优点更加清楚明白，以下结合附图及实 施例，对本发明进行进一步详细说明。应当理解，此处所描述的具体实施例仅 仅用以解释本发明，并不用于限定本发明。In order to make the objects, technical solutions and advantages of the present invention more clearly understood, the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention, but not to limit the present invention.

如图1所示，为本发明实施例中，提出的一种评估集成电路封装热损伤的 方法，包括步骤：As shown in Figure 1, in an embodiment of the present invention, a method for evaluating thermal damage to an integrated circuit package is proposed, comprising the steps of:

步骤S1、根据集成电路高密度叠层式封装过程中出现的热损伤度大小，确 定出依序排列的每一种热损伤度及其对应单向演变成下一种热损伤度的转移概 率，并将所述依序排列的每一种热损伤度作为相应的热损伤状态，且根据所述 依序排列的每一种热损伤度各自对应的转移概率，进一步设置热损伤状态转移 概率矩阵及其构成的热损伤状态分布初始评估模型；其中，所述依序排列的每 一种热损伤度各自对应的转移概率均相同；Step S1, according to the degree of thermal damage occurring in the high-density stacked packaging process of the integrated circuit, determine each thermal damage degree arranged in sequence and its corresponding one-way evolution to the transition probability of the next thermal damage degree, Taking each of the sequentially arranged thermal damage degrees as a corresponding thermal damage state, and further setting the thermal damage state transition probability matrix and The initial evaluation model of thermal damage state distribution formed by it; wherein, the corresponding transition probability of each thermal damage degree arranged in sequence is the same;

具体过程为，步骤S11、根据集成电路高密度叠层式封装在电路周期性通断 和芯片热功率的作用下热累积损伤度，对集成电路高密度叠层式封装分成四个 等级，即确定集成电路高密度叠层式封装过程中出现的热损伤度大小有四种， 并将排列后的四种热损伤度作为四种热损伤状态，具体包括：The specific process is as follows, step S11 , according to the degree of thermal accumulation damage of the high-density integrated circuit package under the action of the periodic on-off of the circuit and the thermal power of the chip, the high-density stacked package of the integrated circuit is divided into four grades, namely determining There are four thermal damage degrees in the process of high-density stacked packaging of integrated circuits, and the four thermal damage degrees after the arrangement are regarded as four thermal damage states, including:

A状态：表示为集成电路高密度叠层式封装符合使用要求，热可靠性高， 没有发生热损伤，状态理想；Status A: Indicates that the integrated circuit high-density stacked package meets the requirements for use, has high thermal reliability, no thermal damage, and is in an ideal state;

B状态：表示为在电路周期性通断和芯片热功率的作用下，集成电路高密度 叠层式封装出现了蠕变和裂纹的萌生，热可靠性比所述A状态略低，但并不影 响使用和安全性，热可靠性有一定的保证；State B: Indicates that creep and cracks have occurred in the high-density stacked package of integrated circuits under the action of periodic on-off of the circuit and thermal power of the chip. The thermal reliability is slightly lower than the state A, but it is not Affecting use and safety, thermal reliability is guaranteed to a certain extent;

C状态：表示为在电路周期性通断和芯片热功率的作用下，在封装内部出现 交变的热应力，导致封装产生微小的裂纹，可能会给电子设备的安全性和正常 使用产生影响和带来隐患，有一定程度的热损伤，热可靠性存在问题；C state: It is expressed as the alternating thermal stress inside the package under the action of the periodic on-off of the circuit and the thermal power of the chip, resulting in tiny cracks in the package, which may affect the safety and normal use of electronic equipment and Bring hidden dangers, a certain degree of thermal damage, thermal reliability problems;

D状态：表示为在电路周期性通断和芯片热功率的作用下，在封装内部出 现交变的热应力集中，导致封装微小的裂纹逐渐汇合形成表面裂纹，然后不断 扩展直至整个封装不能承受交变热载荷的作用，发生热疲劳失效，造成整个电 子设备停止工作。D state: It means that under the action of the periodic on-off of the circuit and the thermal power of the chip, the alternating thermal stress concentration occurs inside the package, causing the tiny cracks in the package to gradually merge to form surface cracks, and then continue to expand until the entire package cannot withstand the alternating current. Under the action of variable thermal load, thermal fatigue failure occurs, causing the entire electronic device to stop working.

由于集成电路高密度叠层式封装热失效是不可修复的，因此热损伤状态转 移是单向的(如图2所示)，并且这种转换过程基本上是一个连续均匀过程，因 此将四种热损伤度从小到大进行排列，且进一步将排列后的热损伤度分别对应 单向演变成下一种热损伤度的转移概率设置为同一概率Pr，那么维持现状态的 概率为1-Pr；Since the thermal failure of integrated circuit high-density stacked packaging is irreparable, the thermal damage state transfer is unidirectional (as shown in Figure 2), and this conversion process is basically a continuous uniform process, so the four The thermal damage degree is arranged from small to large, and the transition probability of the thermal damage degree after the arrangement corresponding to the one-way evolution to the next thermal damage degree is set to the same probability P r , then the probability of maintaining the current state is 1-P r ;

步骤S12、根据排列后的热损伤度分别对应单向演变成下一种热损伤度的转 移概率设置为同一概率Pr，设置热损伤状态转移概率矩阵

Figure BDA0001480525360000081
使得
Figure BDA0001480525360000082
Step S12 , set the transition probability corresponding to the one-way evolution to the next thermal damage degree as the same probability P r according to the arranged thermal damage degree, and set the thermal damage state transition probability matrix
Figure BDA0001480525360000081
make
Figure BDA0001480525360000082

步骤S13、根据热损伤状态转移概率矩阵

Figure BDA0001480525360000091
确定出热损伤状态分布初始评估模型
Figure BDA0001480525360000092
其中，St为t时刻集成电路封装 过程中出现的热损伤状态分布，S0为集成电路封装过程中初始的热损伤状态分 布，且S0＝(1,0,0,0)T。Step S13, according to the thermal damage state transition probability matrix
Figure BDA0001480525360000091
Determine the initial evaluation model of thermal damage state distribution
Figure BDA0001480525360000092
Wherein, S t is the distribution of thermal damage states occurring during the packaging process of the integrated circuit at time t, S 0 is the initial distribution of thermal damage states during the packaging process of the integrated circuit, and S 0 =(1,0,0,0) T .

步骤S2、获取多个已测集成电路封装过程中热损伤完全失效的时间，并根 据所述获取到的多个已测集成电路过程中热损伤完全失效的时间，训练所述热 损伤状态分布初始评估模型，得到热损伤状态分布最终评估模型；Step S2: Obtain the time when the thermal damage completely fails in the packaging process of the multiple tested integrated circuits, and train the initial distribution of the thermal damage state according to the obtained time when the thermal damage completely fails in the multiple tested integrated circuits. Evaluate the model to obtain the final evaluation model of thermal damage state distribution;

具体过程为，步骤S21、获取N个已测集成电路封装过程中热损伤完全失 效的时间t；其中，N为正整数；The specific process is, in step S21, obtaining the time t that the thermal damage completely fails in the packaging process of N measured integrated circuits; wherein, N is a positive integer;

步骤S22、将热损伤完全失效的时间看作是一个服从正态分布的随机变量， 根据公式

Figure BDA0001480525360000093
计算出热损伤完全失效的时间的均值tμ，并进一步根据公式
Figure BDA0001480525360000094
计算出热损伤完全失效的时间的方差
Figure BDA0001480525360000095
Step S22, regard the time when the thermal damage completely fails as a random variable obeying a normal distribution, according to the formula
Figure BDA0001480525360000093
The mean value t μ of the time to complete failure of thermal damage is calculated, and further according to the formula
Figure BDA0001480525360000094
Calculate the variance of the time to complete failure of thermal damage
Figure BDA0001480525360000095

步骤S23、根据所述计算出的热损伤完全失效的时间的均值tμ，对公式

Figure BDA0001480525360000096
采用最小二乘法原则确定Pr的值为
Figure BDA0001480525360000097
并进一步根据所述确定的
Figure BDA0001480525360000098
得到热损伤状态分布最终评估模型Step S23: According to the calculated mean value t μ of the time when the thermal damage completely fails, compare the formula
Figure BDA0001480525360000096
Using the principle of least squares to determine the value of Pr
Figure BDA0001480525360000097
and further determined according to the
Figure BDA0001480525360000098
Obtain the final evaluation model of thermal damage state distribution

Figure BDA0001480525360000101
Figure BDA0001480525360000101

在一个实施例中，取10个高密度叠层式封装的芯片MSD6A828进行加速热 循环试验，达到热损伤失效状态(D状态)的时间分别为：10天，20天，15天， 14天，15天，14天，13天，16天，13天，15天。10个高密度叠层式封装的 芯片MSD6A828加速热循环试验2-10天处于四个状态的个数如下表1所示：In one embodiment, 10 high-density stacked packaged chips MSD6A828 are taken to conduct an accelerated thermal cycle test, and the time to reach the thermal damage failure state (D state) is respectively: 10 days, 20 days, 15 days, 14 days, 15 days, 14 days, 13 days, 16 days, 13 days, 15 days. The number of 10 high-density stacked-package chips MSD6A828 accelerated thermal cycle test in four states for 2-10 days is shown in Table 1 below:

表1：Table 1:

Figure BDA0001480525360000102
Figure BDA0001480525360000102

则热损伤失效的平均时间：

Figure BDA0001480525360000103
Then the mean time to thermal damage failure is:
Figure BDA0001480525360000103

则有：

Figure BDA0001480525360000104
Then there are:
Figure BDA0001480525360000104

采用最小二乘法求得Pr的值为

Figure BDA0001480525360000105
则热损伤状态分布最终评估模型在任何t时刻的状态分布：Using the least squares method to find the value of P r
Figure BDA0001480525360000105
Then the thermal damage state distribution finally evaluates the state distribution of the model at any time t:

Figure BDA0001480525360000106
Figure BDA0001480525360000106

步骤S3、确定待测集成电路封装过程中所需的热损伤评估时间范围，并进 一步根据所述热损伤状态分布最终评估模型，得到所述热损伤评估时间范围内 每一天对应于待测集成电路封装过程中出现的各个热损伤状态分布概率。Step S3: Determine the thermal damage evaluation time range required in the packaging process of the integrated circuit to be tested, and further obtain the thermal damage evaluation time range corresponding to the integrated circuit to be tested for each day in the thermal damage evaluation time range according to the final evaluation model of the thermal damage state distribution. The distribution probability of each thermal damage state that occurs during the packaging process.

具体过程为，确定热损伤评估时间范围为1-10天，根据步骤S2的实施例， 可以得到热损伤评估时间范围内每一天对应于待测集成电路封装过程中出现的 各个热损伤状态分布概率，具体如下表2所示：The specific process is to determine the thermal damage evaluation time range of 1-10 days. According to the embodiment of step S2, the distribution probability of each thermal damage state corresponding to each day in the thermal damage evaluation time range corresponding to the packaging process of the integrated circuit to be tested can be obtained. , as shown in Table 2 below:

表2：Table 2:

Figure BDA0001480525360000111
Figure BDA0001480525360000111

如图3所示，为本发明实施例中，提供的一种评估集成电路封装热损伤的 系统，包括：As shown in Figure 3, in an embodiment of the present invention, a system for evaluating thermal damage to an integrated circuit package is provided, including:

模型初始单元110，用于根据集成电路高密度叠层式封装过程中出现的热损 伤度大小，确定出依序排列的每一种热损伤度及其对应单向演变成下一种热损 伤度的转移概率，并将所述依序排列的每一种热损伤度作为相应的热损伤状态， 且根据所述依序排列的每一种热损伤度各自对应的转移概率，进一步设置热损 伤状态转移概率矩阵及其构成的热损伤状态分布初始评估模型；其中，所述依 序排列的每一种热损伤度各自对应的转移概率均相同；The model initial unit 110 is used to determine each thermal damage degree arranged in sequence and its corresponding one-way evolution into the next thermal damage degree according to the thermal damage degree that occurs during the high-density stacked packaging process of the integrated circuit The transition probability of each thermal damage degree arranged in sequence is regarded as the corresponding thermal damage state, and the thermal damage state is further set according to the corresponding transition probability of each thermal damage degree arranged in sequence. The transition probability matrix and the initial evaluation model of thermal damage state distribution formed by it; wherein, the respective transition probabilities corresponding to each thermal damage degree arranged in sequence are the same;

模型校正单元120，用于获取多个已测集成电路封装过程中热损伤完全失效 的时间，并根据所述获取到的多个已测集成电路过程中热损伤完全失效的时间， 训练所述热损伤状态分布初始评估模型，得到热损伤状态分布最终评估模型；The model calibration unit 120 is configured to obtain the time when thermal damage completely fails in the packaging process of a plurality of measured integrated circuits, and train the thermal The initial evaluation model of damage state distribution is obtained, and the final evaluation model of thermal damage state distribution is obtained;

评估单元130，用于确定待测集成电路封装过程中所需的热损伤评估时间范 围，并进一步根据所述热损伤状态分布最终评估模型，得到所述热损伤评估时 间范围内每一天对应于待测集成电路封装过程中出现的各个热损伤状态分布概 率。The evaluation unit 130 is configured to determine the thermal damage evaluation time range required in the packaging process of the integrated circuit to be tested, and further according to the thermal damage state distribution final evaluation model, obtain each day in the thermal damage evaluation time range corresponding to the thermal damage evaluation time range. Measure the distribution probability of each thermal damage state that occurs in the packaging process of integrated circuits.

其中，所述模型初始单元110包括：Wherein, the model initial unit 110 includes:

排列及概率设置模块1101，用于确定集成电路高密度叠层式封装过程中出 现的热损伤度大小有四种，将四种热损伤度从小到大进行排列，并将所述排列 后的四种热损伤度作为四种热损伤状态，且进一步将所述排列后的热损伤度分 别对应单向演变成下一种热损伤度的转移概率设置为同一概率Pr；The arrangement and probability setting module 1101 is used to determine the thermal damage degree that occurs during the high-density stacked packaging of integrated circuits. There are four types of thermal damage degrees. One thermal damage degree is used as four thermal damage states, and further the transition probability corresponding to the one-way evolution of the arranged thermal damage degree to the next thermal damage degree is set as the same probability P r ;

概率矩阵设置模块1102，用于根据所述排列后的热损伤度分别对应单向演 变成下一种热损伤度的转移概率设置为同一概率Pr，设置热损伤状态转移概率 矩阵

Figure BDA0001480525360000121
The probability matrix setting module 1102 is configured to set the transition probability corresponding to the one-way evolution to the next thermal damage degree to the same probability P r according to the arranged thermal damage degree, and set the thermal damage state transition probability matrix
Figure BDA0001480525360000121

模型初始设置模块1103，用于根据所述热损伤状态转移概率矩阵

Figure BDA0001480525360000122
确定出热损伤状态分布初始评估模型
Figure BDA0001480525360000123
其中，St为t时刻集成电路封装 过程中出现的热损伤状态分布，S0为集成电路封装过程中初始的热损伤状态分 布，且S0＝(1,0,0,0)T。The model initial setting module 1103 is used to transition the probability matrix according to the thermal damage state
Figure BDA0001480525360000122
Determine the initial evaluation model of thermal damage state distribution
Figure BDA0001480525360000123
Wherein, S t is the distribution of thermal damage states occurring during the packaging process of the integrated circuit at time t, S 0 is the initial distribution of thermal damage states during the packaging process of the integrated circuit, and S 0 =(1,0,0,0) T .

其中，所述模型校正单元120包括：Wherein, the model correction unit 120 includes:

历史数据获取模块1201，用于获取N个已测集成电路封装过程中热损伤完 全失效的时间t；其中，N为正整数；The historical data acquisition module 1201 is used to acquire the time t when the thermal damage completely fails in the packaging process of the N tested integrated circuits; wherein, N is a positive integer;

均值及方差计算模块1202，用于将热损伤完全失效的时间看作是一个服从 正态分布的随机变量，根据公式

Figure BDA0001480525360000131
计算出热损伤完全失效的时间的均值 tμ，并进一步根据公式
Figure BDA0001480525360000132
计算出热损伤完全失效的时间的方差
Figure BDA0001480525360000133
The mean and variance calculation module 1202 is used to regard the time of complete failure of thermal damage as a random variable obeying a normal distribution, according to the formula
Figure BDA0001480525360000131
The mean value t μ of the time to complete failure of thermal damage is calculated, and further according to the formula
Figure BDA0001480525360000132
Calculate the variance of the time to complete failure of thermal damage
Figure BDA0001480525360000133

模型校正模块1203，用于根据所述计算出的热损伤完全失效的时间的均值 tμ，对公式

Figure BDA0001480525360000134
采用最小二乘法原则确定Pr的值为
Figure BDA0001480525360000135
并进一步根据所述确定的
Figure BDA0001480525360000136
得到热损伤状态分布最终评估模型The model correction module 1203 is used for calculating the mean value t μ of the time when the thermal damage completely fails.
Figure BDA0001480525360000134
Using the principle of least squares to determine the value of Pr
Figure BDA0001480525360000135
and further determined according to the
Figure BDA0001480525360000136
Obtain the final evaluation model of thermal damage state distribution

Figure BDA0001480525360000137
Figure BDA0001480525360000137

其中，所述四种热损伤状态包括A状态、B状态、C状态和D状态；其中，Wherein, the four thermal damage states include A state, B state, C state and D state; wherein,

所述A状态表示为集成电路高密度叠层式封装符合使用要求，热可靠性高， 没有发生热损伤，状态理想；The A state indicates that the integrated circuit high-density stacked package meets the requirements for use, has high thermal reliability, has no thermal damage, and is in an ideal state;

所述B状态表示为在电路周期性通断和芯片热功率的作用下，集成电路高 密度叠层式封装出现了蠕变和裂纹的萌生，热可靠性比所述A状态略低，但并 不影响使用和安全性，热可靠性有一定的保证；The B state is expressed as creep and crack initiation in the integrated circuit high-density stacked package under the action of the circuit periodic on-off and chip thermal power, and the thermal reliability is slightly lower than the A state, but not It does not affect the use and safety, and the thermal reliability is guaranteed to a certain extent;

所述C状态表示为在电路周期性通断和芯片热功率的作用下，在封装内部 出现交变的热应力，导致封装产生微小的裂纹，可能会给电子设备的安全性和 正常使用产生影响和带来隐患，有一定程度的热损伤，热可靠性存在问题；The C-state is expressed as the alternating thermal stress inside the package under the action of periodic on-off of the circuit and the thermal power of the chip, resulting in tiny cracks in the package, which may affect the safety and normal use of electronic equipment. And bring hidden dangers, there is a certain degree of thermal damage, thermal reliability problems;

所述D状态表示为在电路周期性通断和芯片热功率的作用下，在封装内部 出现交变的热应力集中，导致封装微小的裂纹逐渐汇合形成表面裂纹，然后不 断扩展直至整个封装不能承受交变热载荷的作用，发生热疲劳失效，造成整个 电子设备停止工作。The D state is represented by the alternating thermal stress concentration inside the package under the action of the periodic on-off of the circuit and the thermal power of the chip, which causes the tiny cracks in the package to gradually merge to form surface cracks, and then continue to expand until the entire package cannot withstand it. Under the action of alternating thermal loads, thermal fatigue failure occurs, causing the entire electronic equipment to stop working.

实施本发明实施例，具有如下有益效果：Implementing the embodiment of the present invention has the following beneficial effects:

本发明把集成电路高密度叠层式封装热损伤程度划分为多个状态，根据随 机理论和齐次状态链状态转移的无后效性原理，得出封装热损伤的状态转移概 率，进而构建封装热损伤状态转移概率矩阵，并基于热损伤状态转移概率矩阵 和封装在任何时刻的热损伤状态分布，建立了集成电路高密度叠层式封装热损 伤的精确评估模型，从而能把现有评估方法中的不确定性和模糊性特性转化为 可靠精确的预测模型，降低封装失效率，提高了设备的可靠性和安全性，具有 广泛的应用前景。The invention divides the degree of thermal damage of integrated circuit high-density stacked packaging into multiple states, and obtains the state transition probability of thermal damage of the package according to random theory and the principle of no aftereffect of homogeneous state chain state transition, and then constructs the package The thermal damage state transition probability matrix, and based on the thermal damage state transition probability matrix and the thermal damage state distribution of the package at any time, an accurate evaluation model for thermal damage of integrated circuit high-density stacked packaging is established, so that the existing evaluation methods can be used. Uncertainty and ambiguity in the device are transformed into a reliable and accurate prediction model, which reduces the packaging failure rate, improves the reliability and safety of the device, and has a wide range of application prospects.

值得注意的是，上述系统实施例中，所包括的各个系统单元只是按照功能 逻辑进行划分的，但并不局限于上述的划分，只要能够实现相应的功能即可； 另外，各功能单元的具体名称也只是为了便于相互区分，并不用于限制本发明 的保护范围。It is worth noting that, in the above system embodiment, each system unit included is only divided according to functional logic, but is not limited to the above division, as long as the corresponding function can be realized; The names are only for the convenience of distinguishing from each other, and are not used to limit the protection scope of the present invention.

本领域普通技术人员可以理解实现上述实施例方法中的全部或部分步骤是 可以通过程序来指令相关的硬件来完成，所述的程序可以存储于一计算机可读 取存储介质中，所述的存储介质，如ROM/RAM、磁盘、光盘等。Those skilled in the art can understand that all or part of the steps in the methods of the above embodiments can be implemented by instructing relevant hardware through a program, and the program can be stored in a computer-readable storage medium, and the storage Media such as ROM/RAM, magnetic disk, optical disk, etc.

以上所述仅为本发明的较佳实施例而已，并不用以限制本发明，凡在本发 明的精神和原则之内所作的任何修改、等同替换和改进等，均应包含在本发明 的保护范围之内。The above descriptions are only preferred embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent replacements and improvements made within the spirit and principles of the present invention shall be included in the protection of the present invention. within the range.

Claims (8)

1. A method of evaluating thermal damage of an integrated circuit package, comprising:
step S1, determining each thermal damage degree arranged in sequence and the transition probability of the corresponding unidirectional evolution to the next thermal damage degree according to the size of the thermal damage degree occurring in the high-density laminated packaging process of the integrated circuit, taking each thermal damage degree arranged in sequence as the corresponding thermal damage state, and further setting a thermal damage state transition probability matrix and a thermal damage state distribution initial evaluation model formed by the thermal damage state transition probability matrix according to the transition probability of the corresponding unidirectional evolution to the next thermal damage degree of each thermal damage degree arranged in sequence; wherein, the transition probability of each heat damage degree corresponding to the one-way evolution of the sequentially arranged heat damage degrees to the next heat damage degree is the same;
step S2, acquiring the time of complete failure of thermal damage in the packaging process of the tested integrated circuits, and training the initial evaluation model of the distribution of the thermal damage state according to the acquired time of complete failure of thermal damage in the packaging process of the tested integrated circuits to obtain a final evaluation model of the distribution of the thermal damage state;
step S3, determining a thermal damage evaluation time range required in the packaging process of the ic to be tested, and further obtaining each thermal damage state distribution probability occurring in the packaging process of the ic to be tested every day in the thermal damage evaluation time range according to the final evaluation model of the thermal damage state distribution.
2. The method according to claim 1, wherein the step S1 specifically includes:
determining four heat damage degrees in the high-density laminated packaging process of the integrated circuit, arranging the four heat damage degrees from small to large, taking the four arranged heat damage degrees as four heat damage states, and further setting the transition probability that the four arranged heat damage degrees respectively correspond to one-way evolution to the next heat damage degree as the same probability Pr；
Setting the transition probability that the four arranged heat damage degrees respectively correspond to one-way evolution to the next heat damage degree as the same probability PrSetting a heat damage state transition probability matrix
Figure FDA0002962221470000011
According to the heat damage state transition probability matrix
Figure FDA0002962221470000021
Determining an initial evaluation model of thermal damage state distribution
Figure FDA0002962221470000022
Wherein S istDistribution of thermal damage states, S, occurring during the packaging of the integrated circuit at time t0Is the initial distribution of thermal damage states during the packaging of the integrated circuit, and S0＝(1，0，0，0)T。
3. The method according to claim 2, wherein the step S2 specifically includes:
obtaining the time t of complete failure of thermal damage in the packaging process of N tested integrated circuitsj(ii) a Wherein j is 1 to N, and N is a positive integer;
the time of complete failure of the thermal damage is regarded as a random variable which follows normal distribution according to a formula
Figure FDA0002962221470000023
Calculating the mean value t of the time of complete failure of the thermal damageμAnd further according to the formula
Figure FDA0002962221470000024
Calculating the variance of time to complete failure of thermal damage
Figure FDA0002962221470000025
According to the calculated mean value t of the time of complete failure of the thermal damageμTo formula
Figure FDA0002962221470000026
Determining P by least square methodrHas a value of
Figure FDA0002962221470000027
And further based on said determination
Figure FDA0002962221470000028
Obtaining a final evaluation model of the distribution of the thermal damage state
Figure FDA0002962221470000031
4. The method of claim 3, wherein said four thermal damage states include an A state, a B state, a C state, and a D state; wherein,
the state A indicates that the integrated circuit high-density laminated package meets the use requirement and does not generate heat damage;
the state B shows that under the action of periodic on-off of a circuit and thermal power of a chip, creep deformation and crack initiation occur in the high-density laminated packaging of the integrated circuit, but the use and the safety are not influenced;
the state C represents that alternating thermal stress occurs in the package under the action of periodic on-off of a circuit and thermal power of a chip, so that the package generates tiny cracks, the safety and normal use of electronic equipment can be influenced and hidden dangers can be brought, and the thermal reliability is problematic;
and the state D is expressed as that alternating thermal stress concentration occurs in the package under the action of periodic on-off of a circuit and thermal power of the chip, so that tiny cracks of the package gradually converge to form surface cracks, and then the cracks continuously expand until the whole package cannot bear the action of alternating thermal load, thermal fatigue failure occurs, and the whole electronic equipment stops working.
5. A system for evaluating thermal damage of an integrated circuit package, comprising:
the model initial unit is used for determining each sequentially arranged heat damage degree and the transition probability of the corresponding unidirectional evolution to the next heat damage degree according to the heat damage degree size generated in the high-density laminated packaging process of the integrated circuit, taking each sequentially arranged heat damage degree as the corresponding heat damage state, and further setting a heat damage state transition probability matrix and a heat damage state distribution initial evaluation model formed by the matrix according to the transition probability of the corresponding unidirectional evolution to the next heat damage degree of each sequentially arranged heat damage degree; wherein, the transition probability of each heat damage degree corresponding to the one-way evolution of the sequentially arranged heat damage degrees to the next heat damage degree is the same;
the model correction unit is used for acquiring the time for complete failure of thermal damage in the packaging process of the tested integrated circuits, and training the initial evaluation model of the thermal damage state distribution according to the acquired time for complete failure of thermal damage in the packaging process of the tested integrated circuits to obtain a final evaluation model of the thermal damage state distribution;
and the evaluation unit is used for determining the thermal damage evaluation time range required in the packaging process of the integrated circuit to be tested, and further obtaining the distribution probability of each thermal damage state corresponding to the integrated circuit to be tested in the packaging process every day in the thermal damage evaluation time range according to the final evaluation model of the thermal damage state distribution.
6. The system of claim 5, wherein the model initialization unit comprises:
an arrangement and probability setting module for determining four kinds of heat damage degree in the high-density laminated packaging process of the integrated circuit, arranging the four kinds of heat damage degree from small to large, taking the arranged four kinds of heat damage degree as four heat damage states, and further setting the transition probability that the arranged four kinds of heat damage degree respectively and correspondingly unidirectionally evolve into the next heat damage degree as the same probability Pr；
A probability matrix setting module for setting the transition probability of the four arranged heat damage degrees corresponding to the one-way evolution into the next heat damage degree as the same probability PrSetting a heat damage state transition probability matrix
Figure FDA0002962221470000041
A model initial setting module for transferring probability matrix according to the heat damage state
Figure FDA0002962221470000042
Determining an initial evaluation model of thermal damage state distribution
Figure FDA0002962221470000043
Wherein S istDistribution of thermal damage states, S, occurring during the packaging of the integrated circuit at time t0Is the initial distribution of thermal damage states during the packaging of the integrated circuit, and S0＝(1，0,0，0)T。
7. The system of claim 6, wherein the model correction unit comprises:
a historical data acquisition module for acquiring the time t of complete failure of thermal damage in the packaging process of N tested integrated circuitsj(ii) a Wherein j is 1 to N, and N is a positive integer;
the mean value and variance calculation module is used for regarding the time when the thermal damage completely fails as a random variable obeying normal distribution according to a formula
Figure FDA0002962221470000051
Calculating the mean value t of the time of complete failure of the thermal damageμAnd further according to the formula
Figure FDA0002962221470000052
Calculating the variance of time to complete failure of thermal damage
Figure FDA0002962221470000053
A model correction module for calculating the mean value t of the time for complete failure of thermal damageμTo formula
Figure FDA0002962221470000054
Determining P by least square methodrHas a value of
Figure FDA0002962221470000055
And further based on said determination
Figure FDA0002962221470000056
Obtaining a final evaluation model of the distribution of the thermal damage state
Figure FDA0002962221470000057
8. The system of claim 7, wherein the four thermal damage states include an a state, a B state, a C state, and a D state; wherein,
the state A indicates that the integrated circuit high-density laminated package meets the use requirement and does not generate heat damage;
the state B shows that under the action of periodic on-off of a circuit and thermal power of a chip, creep deformation and crack initiation occur in the high-density laminated packaging of the integrated circuit, but the use and the safety are not influenced;
the state C represents that alternating thermal stress occurs in the package under the action of periodic on-off of a circuit and thermal power of a chip, so that the package generates tiny cracks, the safety and normal use of electronic equipment can be influenced and hidden dangers can be brought, and the thermal reliability is problematic;
and the state D is expressed as that alternating thermal stress concentration occurs in the package under the action of periodic on-off of a circuit and thermal power of the chip, so that tiny cracks of the package gradually converge to form surface cracks, and then the cracks continuously expand until the whole package cannot bear the action of alternating thermal load, thermal fatigue failure occurs, and the whole electronic equipment stops working.
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