CN107884559A - System for the electrical properties of molecular detection complex - Google Patents

Abstract

A system for probing electrical properties of molecular complexes is disclosed. The system includes an electrode electrically coupled to a molecular complex that outputs an electrical signal influenced by an electrical property of the molecular complex, wherein the influence of the electrical property of the molecular complex on the electrical signal is characterized by a desired bandwidth. The system further includes an integrating amplifier circuit configured to receive an electrical signal from the electrode. The integrating amplifier circuit is further configured to selectively amplify and temporally integrate a portion of the electrical signal within a predetermined bandwidth, wherein the predetermined bandwidth is selected based at least in part on the desired bandwidth.

Description

System for probing electrical properties of molecular complexes

This application is a divisional application, and the invention name of its parent case is "system for detecting electrical properties of molecular complexes", the application date is December 12, 2011, and the application number is 201180065839.8.

Cross References to Other Applications

This application claims priority to U.S. Provisional Patent Application No. 61/435,700 (Attorney Docket No. GENIP009+), entitled "SYSTEM FOR COMMUNICATING INFORMATION FROM AN ARRAY OF SENSORS," filed January 24, 2011, the U.S. The Provisional Patent Application is hereby incorporated by reference for all purposes.

Background technique

Advances in miniaturization within the semiconductor industry in recent years have enabled biotechnologists to begin packaging their traditionally bulky sensing tools into smaller and smaller form factors, onto so-called biochips. It would be desirable to develop technologies for biochips.

Description of drawings

Various embodiments of the invention are disclosed in the following detailed description and accompanying drawings.

FIG. 1 is a block diagram illustrating an embodiment of a sensor circuit 100 for measuring physical properties within individual cells in a biochip.

FIG. 2 shows that, with a constant noise floor, as the measurement signal bandwidth decreases, the signal-to-noise ratio increases, thereby improving the sensitivity of the sensor circuit 100 of FIG. 1 .

FIG. 3 is a circuit diagram illustrating an embodiment of a sensor circuit 300 for measuring a physical property (eg, current) within a single cell in an array of nanopores.

FIG. 4 is a circuit diagram illustrating a second embodiment of a sensor circuit 400 for measuring physical properties within individual cells in an array of nanopores.

FIG. 5 is a graph showing a graph of the voltage at the output of the integrating amplifier in circuit 300 or circuit 400 as a function of time.

FIG. 6 is a block diagram showing an example of a cell array in a biochip.

Detailed ways

The invention can be realized in various ways, including as: a process; an apparatus; a system; a composition of matter; a computer program product embodied on a computer-readable storage medium; and/or a processor, such as configured to execute to the processor for instructions on and/or provided by the memory of the processor. In this specification, these implementations, or any other form that the invention may take, may be referred to as techniques. In general, the order of steps of disclosed processes may be altered within the scope of the invention. Unless otherwise stated, a component such as a processor or a memory described as configured to perform a task may be implemented as a general component temporarily configured to perform the task at a given time or manufactured to perform the task specific components. As used herein, the term "processor" refers to one or more devices, circuits and/or processing cores configured to process data, such as computer program instructions.

In various embodiments, the techniques described herein are implemented in a variety of systems or formats. In some embodiments, the technology is implemented in hardware as an Application Specific Integrated Circuit (ASIC) or Field Programmable Gate Array (FPGA). In some embodiments, a processor is used (eg, an embedded processor such as an ARM core) provided or loaded with instructions for performing the techniques described herein. In some embodiments, the techniques are implemented as a computer program product embodied in a computer-readable storage medium and including computer instructions.

A detailed description of one or more embodiments of the invention is provided below along with accompanying figures that illustrate the principles of the invention. The present invention is described in conjunction with these examples, but the present invention is not limited to any example. The scope of the invention is limited only by the claims and the invention encompasses numerous alternatives, modifications and equivalents. In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention. These details are provided for the purpose of example and the invention may be practiced according to the claims without some or all of these specific details. For the purpose of clarity, technical material that is known in the technical fields related to the invention has not been described in detail so that the present invention is not unnecessarily obscured.

Advances in miniaturization within the semiconductor industry in recent years have enabled biotechnologists to begin packaging their traditionally bulky sensing tools into smaller and smaller form factors, onto so-called biochips. These chips are essentially miniaturized laboratories that can perform hundreds or thousands of simultaneous biochemical reactions. Biochips allow researchers to rapidly screen large numbers of biological analytes for purposes ranging from disease diagnosis to detection of bioterrorism agents.

Typically, biochips include large arrays of cells. For example, biochips for nucleotide sequencing can contain thousands or millions of individual cells in an array. Each cell includes a molecular complex consisting of the monomers that make up the oligomeric nanopore and single-stranded DNA, as well as anything that is bound to the single-stranded DNA. Nanopores are small pores in electrically insulating membranes that can be used as single-molecule detectors. Biomaterials such as alpha-hemolysin or MspA can be used to form nanopores. Nanopores can be formed using solid-state materials, such as semiconductor materials. When a small voltage is applied across the molecular complex comprising the nanopore, the ionic current through the molecular complex can be measured to provide information about the structure of the molecule passing through the molecular complex. In individual cells of the array, circuits can be used to control electrical stimulation applied across the lipid bilayer containing the nanopore and to detect the electrical pattern or signature of molecules passing through the nanopore. These patterns or signatures identify events of interest, such as increases or decreases or conformational changes to the molecular complex. To reduce the cost of arrays, physically small individual cells within highly sensitive sensors are desired.

FIG. 1 is a block diagram illustrating an embodiment of a sensor circuit 100 for measuring physical properties within individual cells in a biochip. As shown in FIG. 1 , a physical property such as current, voltage or charge is detected by a detector 102 as a detection signal 104 . As described further below, the sensor circuit 100 may be used to measure the mean value of the detection signal 104 without sampling.

In some embodiments, initiation flag 106 resets integrating amplifier 108 and begins continuous integration of detection signal 104 over time. The integral output 110 is compared to a trip threshold 114 using a comparator 112 . When the integrated output 110 reaches the trip threshold 114 , the trip flag 116 may be used as a feedback signal to the integrating amplifier 108 to terminate the integration of the detection signal 104 . For example, integration is terminated when the trip flag 116 is "on" or asserted. The duration between the assertion of the initiate flag 106 and the assertion of the trip flag 116 is proportional to the mean value of the detection signal 104 (eg, the mean value of the current). Accordingly, the "on" and "off" of the trip flag 116 (only 1 bit of information) can be sent from the cell to an external processor to calculate the mean value of the detection signal 104 . Alternatively, "on/off" information can be sent from the cell to an external memory for delayed processing. For example, the clock cycles in which the initiate flag 106 and the trip flag 116 are each asserted may be recorded in an external memory. The number of clock cycles between two asserted flags can then be used to determine the mean value of the probe signal 104 at a later time.

In some embodiments, more accurate results may be obtained by integrating the detection signal 104 over multiple integration periods. For example, the determined mean value of the detection signal 104 may be further averaged over a plurality of integration periods. In some embodiments, initiation flag 106 is based at least in part on trip flag 116 . For example, initiate flag 106 may be re-asserted in response to trip flag 116 being asserted. In this example, trip flag 116 may be used as a feedback signal for reinitializing integrating amplifier 108 so that another integration period of detection signal 104 may begin once a previous integration period has been terminated. Reasserting initiate flag 106 immediately after trip flag 116 is asserted reduces the portion of time when detector 102 generates a signal that is not integrated and therefore not measured. Integrate over approximately the entire time the signal is available. Thereby, most of the information of the signal is captured, thereby minimizing the time to obtain an average value of the measured signal.

Shot noise may corrupt the trip flag 116 during a particular integration period. Accordingly, some embodiments may include logic to determine whether the trip flag 116 has been corrupted by shot noise for a particular integration period before the trip flag 116 is stored or used in any calculations.

The sensitivity of the sensor circuit 100 is maximized by continuously integrating the detection signal 102 without sampling. This is used to limit the bandwidth of the measurement signal. With continued reference to FIG. 1 , the trip threshold 114 and the integration factor A set the bandwidth of the measurement signal. As the integration factor A decreases or as the trip threshold 114 increases, the measurement signal bandwidth decreases. FIG. 2 shows that, with a constant noise floor, as the measurement signal bandwidth decreases, the signal-to-noise ratio increases, thereby improving the sensitivity of the sensor circuit 100 . In some embodiments, the measurement signal bandwidth may be dynamically adjusted by changing the trip threshold 114 .

FIG. 3 is a circuit diagram illustrating an embodiment of a sensor circuit 300 for measuring a physical property (eg, voltage) within a single cell in an array of nanopores. FIG. 4 is a circuit diagram illustrating a second embodiment of a sensor circuit 400 for measuring physical properties within individual cells in an array of nanopores.

Referring to Figures 3 and 4, the S1 control circuit includes a comparator and other logic, such as logic for switching. Other components of circuit 300 (or circuit 400 ), including the differential pair, implement an integrating amplifier similar to that in FIG. 1 . The input of circuit 300 (or circuit 400 ) is connected to the nanopore system local electrodes.

FIG. 5 is a graph showing a graph of voltage at 310 (or 410 ) in circuit 300 (or circuit 400 ) as a function of time. In Figure 5, t _trip indicates the average current flowing through the nanopore. Reducing the noise bandwidth reduces the noise associated with t _trip . Accordingly, the average current measurement will have a higher signal-to-noise ratio (SNR) and be more accurate.

The integrating amplifier generates a signal within the desired bandwidth comprising the event of interest of the molecular complex. Integrating amplifiers are configured to amplify only signals within the bandwidth of interest and to reject signals outside that bandwidth. Since the wanted signal has a much smaller bandwidth than the probed signal, amplifying all the signal largely amplifies the noise, resulting in poor SNR. The bandwidth of interest can be limited by choosing appropriate values for C ₁ and I ₀ in circuits 300 and 400 . In some embodiments, C ₁ and I ₀ are chosen to limit the bandwidth of interest to between 0.3 Hz and 300 Hz. In some embodiments, the bandwidth of interest can be dynamically adjusted by changing the value of C ₁ .

In some embodiments, the trip flag 116 for each cell is further synchronized with a global clock shared by all cells within the biochip. For example, trip flag 116 may be generated by a pulse generation circuit that is synchronized to a global clock. After synchronization, the trip flag 116 is a single pulse in phase with the global clock.

FIG. 6 is a block diagram showing an example of a cell array in a biochip. Each cell may contain sensor circuitry 100 as described above for measuring physical properties within the cell. As shown in Figure 6, the cell array has m columns by n rows of individual cells. All cells in a given column share the same column line 302 and all cells in a given row share the same row line 304 . When the trip flag 116 for a particular cell is asserted, that cell asserts its particular column line 302 and row line 304 . To reduce the pin count of the biochip, a column multiplexer 306 may be used to output a column number (0 - 2 ^m -1 ) indicating which column line 302 has been asserted. Similarly, row multiplexer 308 may be used to output a row number (0 - 2 ⁿ -1 ) indicating which row line 304 has been asserted. For example, if the trip flag 116 of a cell in the second column and row is asserted, the column and row numbers of the output are (1, 1). As long as only one cell asserts its trip flag 116 at a time, the reported column and row numbers are sufficient to uniquely identify which particular cell was asserted at a particular time.

The techniques described above have several advantages over other approaches. Integrating amplifiers require extremely small die area and allow each array site to have its own dedicated measurement circuitry. This feature reduces noise by removing the need to route sensitive analog signals to the periphery of the array and avoids the need for multiplexing. The integrating amplifier does not require preamplifiers, sample-and-hold, or antialiasing filters, further reducing die area and potential error sources. Since only a single flag is required to indicate the completion of a measurement, this integration method is an efficient way to transfer data from each array site. Measurements are taken continuously (except for the brief time required to reset the integrating capacitor), so data is collected almost 100% of the time. Furthermore, each cell and its associated measurement circuitry operates autonomously, allowing each cell to track the state of the measurement molecule. As mentioned above, this integration method also has inherent signal averaging and noise advantages.

Although the foregoing embodiments have been described in some detail for purposes of clarity of understanding, the invention is not limited to the details provided. There are many alternative ways of implementing the invention. The disclosed embodiments are illustrative and not restrictive.

Claims (17)

1. A system for communicating information from a nanopore sensor array comprising: a nanopore sensor array comprising a plurality of nanopore sensors, wherein each sensor senses a physical property of a material in communication with the sensor; signal processing circuitry associated with each sensor that integrates the output of that sensor over time and compares the integrated output to a threshold; and a communication network coupled to the signal processing circuit that outputs information indicating that the integrated output corresponding to a given sensor has reached a threshold, wherein the information includes a 1-bit flag; and wherein the sensor array includes a first plurality of rows of sensors and a second plurality of columns of sensors, and wherein a 1-bit flag for each row of sensors shares a row signal line, and wherein a 1-bit flag for each column of sensors bit flags share a column signal line, and wherein each row signal line is asserted if at least one 1-bit flag sharing that row signal line is asserted, and wherein each column signal line is asserted on at least one of the column signal lines sharing that column signal line A 1-bit flag is asserted when the condition is asserted. 2. The system of claim 1 , wherein integrating the output of the sensor over time comprises: initiating integration based on an initiation flag; and terminating integration based on information indicating that the integrated output corresponding to the sensor has reached a threshold . 3. The system of claim 2, wherein the communication network further outputs the status of the initiation flag. 4. The system of claim 2, wherein the time period between initiation and termination of the credit corresponds to the mean value of the physical property. 5. The system of claim 2, wherein integrating the output of the sensor over time is repeated by deriving a trigger based at least in part on information indicating that the integrated output corresponding to the sensor has reached a threshold value. mark. 6. The system of claim 5, wherein the initiate flag is re-asserted in response to information indicating that the integrated output corresponding to the sensor has reached a threshold. 7. The system of claim 1, wherein the bandwidth of the integrated output is adjusted based at least in part on adjusting coefficients associated with the signal processing circuit. 8. The system of claim 1, wherein the bandwidth of the integrated output is adjusted based at least in part on adjusting the threshold. 9. The system of claim 1, wherein the bandwidth of the integrated output is adjusted based at least in part on adjusting a capacitance associated with the signal processing circuit. 10. The system of claim 1, wherein increasing a signal-to-noise ratio of the integrated output is based at least in part on reducing a bandwidth of the integrated output. 11. The system of claim 1, wherein the physical property comprises one of: current, voltage, or charge. 12. The system of claim 1, wherein the information corresponds to a mean value of a physical property. 13. The system of claim 1, wherein the 1-bit flag for a given sensor is synchronized to a global clock shared by multiple sensors. 14. The system of claim 13, wherein the 1-bit flag is generated by a pulse generation circuit. 15. The system of claim 1, further comprising a row multiplexer to output a row number in response to the asserted row signal line, the row number corresponding to the asserted row signal line. 16. The system of claim 1, further comprising a column multiplexer to output a column number in response to the asserted column signal line, the column number corresponding to the asserted column signal line. 17. A method for communicating information from a nanopore sensor array, comprising: sensing a physical property of a material in communication with each sensor in the nanopore sensor array; integrating the output of each sensor over time and comparing the integrated output to a threshold; and outputting information indicating that the integrated output corresponding to the given sensor has reached a threshold, wherein the information includes a 1-bit flag; and wherein the sensor array includes a first plurality of rows of sensors and a second plurality of columns of sensors, and wherein a 1-bit flag for each row of sensors shares a row signal line, and wherein a 1-bit flag for each column of sensors bit flags share a column signal line, and wherein each row signal line is asserted if at least one 1-bit flag sharing that row signal line is asserted, and wherein each column signal line is asserted on at least one of the column signal lines sharing that column signal line A 1-bit flag is asserted when the condition is asserted.