CN107808899A - Lateral power with hybrid conductive pattern and preparation method thereof - Google Patents

Abstract

The present invention provides a kind of lateral power with hybrid conductive pattern and preparation method thereof, including P type substrate, buries oxide layer, N-type drift region, p-type base, N-type buffering area, N-type source region, p-type contact zone, p-type collector area, emitter stage, colelctor electrode, gate dielectric layer, gate electrode, N-type drift region surface has N-type bar and p-type bar, N-type bar and p-type bar are spaced perpendicular to orientation on device drift region surface, have p-type RESURF layers in drift region below N-type bar and p-type bar；There is medium slot structure between N-type bar, p-type bar and p-type RESURF layers three and N-type buffering area；The concentration of N-type bar and p-type bar is more than the concentration of N-type drift region；The depth of medium slot structure is not less than the depth of N-type bar, p-type bar and p-type collector area；The present invention realizes surface SJ LDMOS and LIGBT hybrid conductive, can obtain lower conduction voltage drop, and higher is pressure-resistant, faster switching speed, lower turn-off power loss, and eliminates snapback effects, greatly improves device performance.

Description

Lateral power device with mixed conduction mode and method of making same

technical field

The invention belongs to the technical field of power semiconductor devices, and in particular relates to a lateral power semiconductor device with a mixed conduction mode and a preparation method thereof.

Background technique

Lateral Insulated Gate Bipolar Transistor (LIGBT) is a lateral power device that combines the advantages of lateral power MOSFETs and bipolar transistors, and has the characteristics of high input impedance and reduced conduction voltage. , are widely used in various power integrated circuits. Compared with traditional devices based on bulk silicon technology, devices manufactured using SOI technology have many advantages such as fast speed, low power consumption, high integration density, strong anti-latch ability, low cost, and good radiation resistance. Therefore, LIGBT devices based on SOI materials also have the advantages of good insulation performance, low substrate leakage current, small parasitic capacitance and high integration, and their manufacturing process is compatible with SOI-CMOS process and easy to implement, so it has become a power integrated circuit. One of the core components. When the LIGBT device is turned on, due to the conductance modulation effect in the drift region, a low turn-on voltage drop can be obtained, but when it is turned off, due to the existence of a large number of unbalanced carriers stored in the drift region, the turn-off time is long, The turn-off loss is large. At the same time, due to the existence of the PN junction in the collector area of the device, when the device is conducting forward, in the low collector voltage region, and at the same current density, the conduction voltage drop of LIGBT is larger than that of LDMOS devices, which is not conducive to the reduction of device loss characteristics. Small.

Contents of the invention

In view of the shortcomings of the prior art described above, the object of the present invention is to provide a lateral power semiconductor device with mixed conduction modes and a manufacturing method thereof.

In order to realize the foregoing invention object, the technical scheme of the present invention is as follows:

A lateral power device with a mixed conduction mode, comprising a P-type substrate 1, a buried oxide layer 2, and an N-type drift region 3 arranged sequentially from bottom to top; one end of the N-type drift region 3 is provided with a P-type base region 4. An N-type buffer zone 8 is provided at the other end; an N-type source region 5 and a P-type contact region 6 are provided above the inside of the P-type base region 4, and a P-type collector is provided above the inside of the N-type buffer region 8 region 9; an emitter 10 is provided above the P-type contact region 6 and part of the N-type source region 5; part of the upper surface of the P-type collector region 9 has a collector 12; the P-type base region 4 is also provided with A gate dielectric layer 7, with a gate electrode 11 above the gate dielectric layer 7, the length of the gate structure formed by the gate dielectric layer 7 and the gate electrode 11 is greater than the length of the surface of the P-type base region 4, and the two ends of the gate structure are respectively It is in contact with the upper surface of the N-type source region 5 and the upper surface of the N-type drift region 3; the surface of the N-type drift region 3 has an N-type bar 13 and a P-type bar 14, and the N-type bar 13 and the P-type bar 14 are in The surface of the device drift region is arranged alternately perpendicular to the channel length direction, and there is a P-type RESURF layer 16 in the drift region below the N-type strip 13 and the P-type strip 14; the N-type strip 13, P-type strip 14 and P-type RESURF There is a dielectric groove structure 17 between the three layers 16 and the N-type buffer zone 8; the N-type strip 13 has an electrode 15 on the upper surface near the dielectric groove structure 17, and the electrode 15 is connected to the collector electrode 12; The concentration of the N-type strip 13 and the P-type strip 14 is greater than the concentration of the N-type drift region 3; the depth of the dielectric trench structure 17 is not less than the depth of the N-type strip 13, the P-type strip 14 and the P-type collector region 9 .

Compared with the traditional LIGBT structure shown in Figure 1, the present invention introduces a 3-dimensional structure of high-concentration N/P strips arranged alternately on the surface of the drift region of the device perpendicular to the channel length direction (Z direction), and introduces a P Type RESURF layer, when the device is forward-conducting, realize the mixed conduction of surface SJ-LDMOS and LIGBT, and at the same time use the surface N/P strip and the 3-dimensional RESURF function of the P-type RESURF layer to improve the breakdown voltage of the device and use the depletion layer The three-dimensional expansion of the device improves the turn-off speed of the device and reduces the turn-off loss of the device. In the forward conduction process of the structure of the present invention, as the collector voltage increases, due to the isolation of the dielectric trench structure and the P-type RESURF layer during the transition from the SJ-LDMOS conduction mechanism to the SJ-LDMOS and LIGBT mixed conduction mechanism Function, there will be no snapback effect of conventional RC-IGBT. In addition, the manufacturing process of the present invention is compatible with the traditional LIGBT process without increasing the difficulty of manufacturing.

As a preferred mode, the P-type RESURF layer 16, N-type strip 13 and P-type strip 14 are not in contact with the P-type base region 4, and the concentration of the N-type strip 13 and P-type strip 14 is not less than that of the P-type RESURF layer 16 concentration.

As a preferred manner, there is an N-type layer 18 between the N-type strip 13 and the P-type strip 14 and the P-type RESURF layer 16, and the concentration of the N-type layer 18 is greater than the concentration of the N-type drift region 3 .

As a preferred manner, the P-type RESURF layer 16 is composed of a first sub-region 161, a second sub-region 162 and a third sub-region 163 whose concentrations decrease from left to right.

As a preferred manner, the N-type drift region 3 is composed of a first doped region 31 and a second doped region 32 whose concentration increases sequentially from left to right.

As a preferred mode, the width of the N-type strip 13 gradually increases from left to right, and the width of the P-type strip 14 gradually decreases from left to right; or the concentration of the N-type strip 13 gradually increases from left to right, and the P-type strip The concentration of 14 decreases gradually from left to right.

As a preferred manner, the MOS structure of the device is a trench structure.

As a preferred manner, the MOS structure of the device is a double-gate composite structure composed of a planar structure and a trench structure.

As a preferred mode, the dielectric trench structure 17 is directly in contact with the P-type collector region 9, the N-type buffer zone 8 is only below the P-type collector region 9, and the depth of the dielectric trench structure 17 is greater than the P-type RESURF layer 16 and the N-type The depth of buffer 8.

In order to achieve the purpose of the above invention, the present invention also provides a method for preparing the above-mentioned lateral power device with a mixed conduction mode, comprising the following steps:

Step 1: Select a silicon-on-insulator material, in which the thickness of the substrate is 300-500 microns, the doping concentration is 10 ^{14-10 15} /cm ³ , the thickness of the buried oxide layer on the substrate is 0.5-3 microns, SOI The thickness of the layer is 5-20 microns;

The second step: photolithography, by ion-implanting N-type impurities in the right area of the silicon wafer surface and annealing to make an N-type buffer zone 8, the thickness of the formed N-type buffer zone 8 is 2 to 4 microns;

Step 3: Thermal oxidation and deposition of gate electrode material on the surface of the silicon wafer, photolithography, etching part of the gate electrode material and gate oxide layer to form a gate electrode;

The fourth step: photolithography, on the left side of the drift region on the surface of the silicon wafer, ion-implant P-type impurities and anneal to make a P-type base region, and the thickness of the formed P-type base region is 2 to 3 microns;

The fifth step: photolithography, forming a P-type RESURF layer by implanting P-type impurities with high-energy ions in the middle of the drift region on the surface of the silicon wafer;

Step 6: Photolithography, in the middle of the drift region on the surface of the silicon wafer, ion-implant N-type impurities and anneal to make N-striped regions, and the width of the formed N-striped regions is 0.5 to 1 micron;

The seventh step: photolithography, in the middle of the drift region on the surface of the silicon wafer, ion-implant P-type impurities and anneal to make a P-strip region, and the width of the formed P-strip region is 0.5 to 1 micron;

The eighth step: photolithography, etching and filling medium to form a dielectric groove, the depth of the formed dielectric groove is not less than the depth of the P-type collector region;

Step 9: Photolithography, respectively ion-implanting N-type impurities and P-type impurities in the left area of the silicon wafer surface and annealing to make N-type source regions and P-type contact regions, and the formed N-type source regions and P-type contact regions The thickness is about 0.2-0.3 microns;

Step 10: Photolithography, ion-implanting P-type impurities on the right side of the silicon wafer surface and annealing to make a P-type collector region, the thickness of the formed P-type collector region is 0.3-0.5 microns;

The eleventh step: depositing, photolithography, and etching a dielectric layer to form a dielectric layer;

Step 12: Depositing, photolithography, and etching metal to form a metal emitter and a metal collector on the surface of the device; that is, a lateral power device with a mixed conduction mode is prepared.

The beneficial effects of the present invention are as follows: the present invention introduces a 3-dimensional structure of high-concentration N/P strips arranged alternately on the surface of the device drift region perpendicular to the channel length direction, and introduces a P-type RESURF layer below it, and passes through the dielectric trench structure The N/P strip 3-dimensional structure is isolated from the N-buffer area and the P-type collector area. When the device is in the blocking state, the breakdown voltage of the device is improved by using the 3-dimensional RESURF effect of the surface N/P strip and the P-type RESURF layer, and at the same time the doping of the surface N/P strip, the P-type RESURF layer and the N-type drift region is increased. impurity concentration; when the device is forward-conducting, when the collector voltage is low, the super-junction MOS structure formed by the 3-dimensional structure of high-concentration N/P strips on the surface is turned on. Due to the high concentration of N strips, the on-resistance of the device is small, When the collector voltage reaches and exceeds 0.7V, the LIGBT and the super junction MOS structure are turned on at the same time, and have a large conduction current under a certain collector voltage. Due to the shielding effect of the dielectric trench structure and the P-type RESURF layer, the super junction MOS structure The existence of the junction MOS structure will not affect the conduction characteristics of LIGBT, and the snapback effect of conventional RC-IGBT will not appear; when the device is turned off, due to the three-dimensional expansion of the depletion layer of the surface N/P strip and the P-type RESURF layer, The turn-off speed of the device is improved, and the turn-off loss of the device is reduced. At the same time, due to the effect of the super-junction MOS structure, the number of excess carriers injected into the N-type drift region 3 of the device is reduced at a certain on-current density. The device is small, which further improves the turn-off speed of the device and reduces the turn-off loss of the device; at the same time, the present invention also has the function of reverse conduction due to the integration of the super-junction MOS structure. Therefore, compared with the traditional SOI-LIGBT, the present invention realizes the mixed conduction of surface SJ-LDMOS and LIGBT, and can obtain lower turn-on voltage drop, higher withstand voltage, faster switching speed, and lower turn-off Break loss, and eliminate the snapback effect, greatly improving device performance.

Description of drawings

Figure 1 is a schematic diagram of a traditional SOI-LIGBT cell structure.

FIG. 2 is a schematic diagram of the cell structure of a lateral power device with a mixed conduction mode according to Embodiment 1 of the present invention.

Fig. 3 is an interface diagram along the line AA' of the lateral power device cell structure with mixed conduction modes according to Embodiment 1 of the present invention.

FIG. 4 is a schematic diagram of the cell structure of a lateral power device with a mixed conduction mode according to Embodiment 2 of the present invention.

Fig. 5 is an interface diagram along line AA' of a lateral power device cell structure with a mixed conduction mode according to Embodiment 2 of the present invention.

FIG. 6 is a schematic diagram of a cell structure of a lateral power device with a mixed conduction mode according to Embodiment 3 of the present invention.

FIG. 7 is a schematic diagram of a cell structure of a lateral power device with a mixed conduction mode according to Embodiment 4 of the present invention.

FIG. 8 is a schematic diagram of the cell structure of a lateral power device with a mixed conduction mode according to Embodiment 5 of the present invention.

FIG. 9 is a schematic diagram of the cell structure of a lateral power device with a mixed conduction mode according to Embodiment 6 of the present invention.

Among them, 1 is the P-type substrate, 2 is the buried oxide layer, 3 is the N-type drift region, 4 is the P-type base region, 5 is the N+ source region, 6 is the P+ contact region, 7 is the gate dielectric layer, 8 is the N 9 is the P-type collector area, 10 is the gate electrode, 11 is the gate electrode, 12 is the collector, 13 is the N-type strip, 14 is the P-type strip, 15 is the electrode, 16 is the P-type RESURF layer, 17 is the dielectric groove structure, 18 is the N-type layer, 161 is the first sub-region of the P-type RESURF layer, 162 is the second sub-region of the P-type RESURF layer, 163 is the third sub-region of the P-type RESURF layer, and 31 is the N-type drift The first doped region, 32, is the first doped region of the N-type drift region.

Detailed ways

Embodiments of the present invention are described below through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific implementation modes, and various modifications or changes can be made to the details in this specification based on different viewpoints and applications without departing from the spirit of the present invention.

Example 1

A lateral power device with a mixed conduction mode, the cellular structure and the cross-sectional views along the line AA' are shown in Figure 2 and Figure 3, respectively, including a P-type substrate 1, a buried oxide layer 2 and a N-type drift region 3; one end of the N-type drift region 3 is provided with a P-type base region 4, and the other end is provided with an N-type buffer zone 8; an N-type source region 5 and an N-type source region 5 are arranged above the interior of the P-type base region 4. A P-type contact region 6, a P-type collector region 9 is provided above the inside of the N-type buffer zone 8; an emitter 10 is provided above the P-type contact region 6 and part of the N-type source region 5; the P-type collector Part of the upper surface of the region 9 has a collector electrode 12; a gate dielectric layer 7 is also arranged above the P-type base region 4, and a gate electrode 11 is arranged above the gate dielectric layer 7, and the gate dielectric layer 7 and the gate electrode 11 are composed of The length of the gate structure is greater than the length of the surface of the P-type base region 4, and the two ends of the gate structure are respectively in contact with the upper surface of the N-type source region 5 and the upper surface of the N-type drift region 3; the surface of the N-type drift region 3 has N Type strips 13 and P-type strips 14, the N-type strips 13 and P-type strips 14 are arranged alternately on the device drift region surface perpendicular to the channel length direction, and the drift region below the N-type strips 13 and P-type strips 14 has P-type RESURF layer 16; there is a dielectric groove structure 17 between the N-type strip 13, P-type strip 14 and P-type RESURF layer 16 and the N-type buffer zone 8; the N-type strip 13 is close to the dielectric groove structure There is an electrode 15 on the upper surface of one side of 17, and the electrode 15 is connected to the collector electrode 12; the concentration of the N-type strip 13 and the P-type strip 14 is greater than the concentration of the N-type drift region 3; the dielectric groove structure 17 The depth is not less than the depth of the N-type strip 13 , the P-type strip 14 and the P-type collector region 9 . The thickness of the N-type drift region 3 is 5-20 microns; the depth of the P-type RESURF delamination surface is 1-4 microns, and the thickness is 0.5-2 microns; the width of the N-type strip 13 and the P-type strip 14 is 0.5-1 micron ; The distance between the P-type RESURF layer 16, the N-type strip 13 and the P-type strip 14 and the P-type base region 4 is 0.5-5 microns.

This example works as follows:

Blocking state: When the collector is positively biased and the emitter and gate are connected to zero potential, the device is in blocking mode. Using the 3-dimensional RESURF function of the surface N/P strip and the P-type RESURF layer, the surface N/P strip, the P-type RESURF layer, and the N-type drift region are all depleted before the device breaks down, thereby optimizing the electric field in the drift region. A higher device withstand voltage is obtained under a longer drift region length, and the doping concentration of the surface N/P strip, P-type RESURF layer, and N-type drift region is increased. At the same time, the MOS structure introduced on the surface reduces the gain of the parasitic PNP transistor in the P-type collector region/N-type drift region/P-type base region, further improving the breakdown voltage of the device.

In the forward conduction state: the emitter is connected to zero potential. When the voltage applied to the gate is greater than the threshold voltage of the device, the semiconductor on the surface of the P-type base region under the gate is inverted, the channel of the device is turned on, and the collector is positively biased. At this time, the lateral superjunction MOSFET formed by the 3-dimensional structure of high-concentration N/P strips on the left surface of the dielectric trench 17 is turned on. Due to the high concentration of N strips, the device has a small on-resistance and a large current. When the voltage applied to the collector is greater than the turn-on voltage of the PN junction, the P-type collector region 9 injects holes into the N-type drift region 3, at this time the LIGBT structure starts to conduct, and forms a conductance modulation effect in the N-type drift region 3 . At this time, the LIGBT and the superjunction MOS structure are turned on at the same time, and have a large conduction current under a certain collector voltage. Due to the shielding effect of the dielectric trench structure and the P-type RESURF layer, the existence of the superjunction MOS structure will not affect The conduction characteristic of LIGBT does not appear the snapback effect of conventional RC-IGBT.

Off state: When the gate voltage starts to decrease from the voltage during forward conduction, the device starts to turn off. Since the SJ-MOSFET structure and the LIGBT structure can be turned on at the same time when the device is conducting forward, the holes stored in the drift region will be reduced in the conducting state, which can make the turn-off faster and the turn-off loss smaller; and because the surface The three-dimensional expansion of the depletion layer of the N/P bar and the P-type RESURF layer accelerates the depletion of the drift region, making the carrier extraction faster, and the device's turn-off performance is more excellent, which further improves the turn-off speed of the device. The turn-off loss of the device is reduced.

Reverse conduction state: Due to the formation of the surface SJ-MOSFET structure, when the emitter is connected to a high potential and the collector is connected to a low potential, the body diode of the surface SJ-MOSFET structure starts to conduct, which can realize reverse conduction and reverse conduction function .

Therefore, compared with the traditional SOI-LIGBT, the present invention realizes the mixed conduction of surface SJ-LDMOS and LIGBT, and can obtain lower turn-on voltage drop, higher withstand voltage, faster switching speed, and lower turn-off Break loss, and eliminate the snapback effect, greatly improving device performance.

The P-type RESURF layer 16, the N-type strip 13 and the P-type strip 14 are not in contact with the P-type base region 4, and the concentration of the N-type strip 13 and the P-type strip 14 is not less than the concentration of the P-type RESURF layer 16 .

Example 2

As shown in Figures 4 and 5, the difference between this example and Example 1 is that there is an N-type layer 18 between the N-type strip 13 and the P-type strip 14 and the P-type RESURF layer 16, and the N-type layer 18 is The concentration of the N-type layer 18 is greater than that of the N-type drift region 3 . Compared with Embodiment 1, this embodiment can further improve the current conduction capability of the lateral MOSFET.

Example 3

As shown in FIG. 6 , the difference between this example and Example 1 is that the P-type RESURF layer 16 consists of a first subregion 161 , a second subregion 162 and a third subregion 163 whose concentrations decrease from left to right. composition. Compared with Embodiment 1, this embodiment can further improve the breakdown voltage of the device.

Example 4

As shown in FIG. 7 , the difference between this example and Example 3 is that the N-type drift region 3 is composed of a first doped region 31 and a second doped region 32 whose concentration increases from left to right. Compared with Embodiment 3, this embodiment can further increase the breakdown voltage of the device, increase the turn-off speed of the device, and reduce the turn-off loss.

Example 5

As shown in FIG. 8 , the difference between this example and Example 4 is that the MOS structure of the device is a trench structure. Compared with Embodiment 4, this embodiment can further reduce the turn-on voltage drop of the device. In this embodiment, a double-gate composite structure composed of a planar MOS structure and a trench MOS structure may also be used.

Example 6

As shown in Figure 9, the difference between this example and Embodiment 5 is that the dielectric groove structure 17 is directly in contact with the P-type collector region 9, the N-type buffer zone 8 is only below the P-type collector region 9, and the dielectric groove structure The depth of 17 is greater than the depth of P-type RESURF layer 16 and N-type buffer 8 . Compared with Embodiment 5, this embodiment can further reduce the area of the device.

Example 7

The method for preparing a lateral power device with a mixed conduction mode described in the above six embodiments includes the following steps:

Step 1: Select a silicon-on-insulator material, in which the thickness of the substrate is 300-500 microns, the doping concentration is 10 ^{14-10 15} /cm ³ , the thickness of the buried oxide layer on the substrate is 0.5-3 microns, SOI The thickness of the layer is 5-20 microns;

The second step: photolithography, by ion-implanting N-type impurities in the right area of the silicon wafer surface and annealing to make an N-type buffer zone 8, the thickness of the formed N-type buffer zone 8 is 2 to 4 microns;

Step 3: Thermal oxidation and deposition of gate electrode material on the surface of the silicon wafer, photolithography, etching part of the gate electrode material and gate oxide layer to form a gate electrode;

The fourth step: photolithography, on the left side of the drift region on the surface of the silicon wafer, ion-implant P-type impurities and anneal to make a P-type base region, and the thickness of the formed P-type base region is 2 to 3 microns;

The fifth step: photolithography, forming a P-type RESURF layer by implanting P-type impurities with high-energy ions in the middle of the drift region on the surface of the silicon wafer;

Step 6: Photolithography, in the middle of the drift region on the surface of the silicon wafer, ion-implant N-type impurities and anneal to make N-striped regions, and the width of the formed N-striped regions is 0.5 to 1 micron;

The seventh step: photolithography, in the middle of the drift region on the surface of the silicon wafer, ion-implant P-type impurities and anneal to make a P-strip region, and the width of the formed P-strip region is 0.5 to 1 micron;

The eighth step: photolithography, etching and filling medium to form a dielectric groove 17, the depth of the formed dielectric groove is not less than the depth of the P-type collector region;

Step 9: Photolithography, respectively ion-implanting N-type impurities and P-type impurities in the left area of the silicon wafer surface and annealing to make N-type source regions and P-type contact regions, and the formed N-type source regions and P-type contact regions The thickness is about 0.2-0.3 microns;

Step 10: Photolithography, ion-implanting P-type impurities on the right side of the silicon wafer surface and annealing to make a P-type collector region, the thickness of the formed P-type collector region is 0.3-0.5 microns;

The eleventh step: depositing, photolithography, and etching a dielectric layer to form a dielectric layer;

Step 12: Deposit, photolithography, and etch metal to form metal emitter and metal collector at appropriate positions on the surface of the device; that is, to prepare a lateral power device with a mixed conduction mode.

In addition, as a preferred manner, the width of the N-type strip 13 gradually increases from left to right, and the width of the corresponding P-type strip 14 gradually decreases from left to right; or the concentration of the N-type strip 13 gradually increases from left to right, The concentration of P-type bars 14 gradually decreases from left to right.

It should be stated that: the technical solution of the present invention is only described by taking an N-channel device as an example, and only the doping type of each region needs to be exchanged, and the present invention is also applicable to a P-channel device. The dielectric material of the present invention is not limited to silicon dioxide, but also includes: silicon nitride (Si ₃ N ₄ ), hafnium dioxide (HfO ₂ ), aluminum oxide (Al ₂ O ₃ ) and other dielectric materials. The semiconductor material can be silicon, or wide bandgap materials such as silicon carbide, gallium nitride, and diamond. At the same time, the specific implementation of the manufacturing process can also be adjusted according to actual needs.

The above-mentioned embodiments only illustrate the principles and effects of the present invention, but are not intended to limit the present invention. Anyone skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or changes made by those skilled in the art without departing from the spirit and technical ideas disclosed in the present invention shall still be covered by the claims of the present invention.

Claims (10)

1. a lateral power device with a mixed conduction mode, comprising a P-type substrate (1) arranged in sequence from bottom to top, a buried oxide layer (2) and an N-type drift region (3); said N-type drift region ( 3) One end of the interior is provided with a P-type base area (4), and the other end is provided with an N-type buffer zone (8); the inside of the P-type base area (4) is provided with an N-type source area (5) and a P-type contact region (6), a P-type collector region (9) is provided above the inside of the N-type buffer zone (8); an emitter ( 10); the upper surface of the P-type collector region (9) has a collector electrode (12); the P-type base region (4) is also provided with a gate dielectric layer (7), and the gate dielectric layer (7 ) above has a gate electrode (11), the length of the gate structure formed by the gate dielectric layer (7) and the gate electrode (11) is greater than the length of the surface of the P-type base region (4), and the two ends of the gate structure are respectively connected to the N The upper surface of the type source region (5) is in contact with the upper surface of the N-type drift region (3); it is characterized in that: the surface of the N-type drift region (3) has N-type strips (13) and P-type strips (14), The N-type strips (13) and P-type strips (14) are arranged alternately on the surface of the device drift region perpendicular to the channel length direction, and there are P in the drift region below the N-type strips (13) and P-type strips (14). Type RESURF layer (16); There is a dielectric groove structure (17) between the N type strip (13), the P type strip (14) and the P type RESURF layer (16) three and the N type buffer zone (8); The N-type strip (13) has an electrode (15) on the upper surface near the dielectric tank structure (17), and the electrode (15) is connected to the collector (12); the N-type strip (13) and the P The concentration of the type strip (14) is greater than the concentration of the N-type drift region (3); the depth of the dielectric groove structure (17) is not less than the N-type strip (13), the P-type strip (14) and the P-type collector Depth of zone (9). 2. The lateral power device with mixed conduction mode according to claim 1, characterized in that: the P-type RESURF layer (16), the N-type strip (13) and the P-type strip (14) are not connected with the P-type The base area (4) is in contact with each other, and the concentration of the N-type strips (13) and the P-type strips (14) is not less than the concentration of the P-type RESURF layer (16). 3. The lateral power device with mixed conduction mode according to claim 1, characterized in that: there is a gap between the N-type strip (13), the P-type strip (14) and the P-type RESURF layer (16). An N-type layer (18) is provided, and the concentration of the N-type layer (18) is greater than the concentration of the N-type drift region (3). 4. The lateral power device with mixed conduction mode according to claim 1, characterized in that: the P-type RESURF layer (16) consists of the first sub-region (161), the first sub-region (161), and the second sub-region whose concentration decreases from left to right. The second sub-region (162) and the third sub-region (163) are composed. 5. The lateral power device with mixed conduction mode according to claim 1, characterized in that: the N-type drift region (3) consists of the first doped region (31) and the second doped region (31) whose concentration increases from left to right Two doped regions (32) are formed. 6. The lateral power device with mixed conduction mode according to claim 1, characterized in that: the width of the N-type strip (13) gradually increases from left to right, and the width of the P-type strip (14) increases from left to right The right gradually decreases; or the concentration of N-type bars (13) gradually increases from left to right, and the concentration of P-type bars (14) gradually decreases from left to right. 7. The lateral power device with mixed conduction mode according to claim 1, characterized in that: the MOS structure of the device is a trench structure. 8 . The lateral power device with mixed conduction mode according to claim 1 , wherein the MOS structure of the device is a double-gate compound structure composed of a planar structure and a trench structure. 9. The lateral power device with mixed conduction mode according to claim 1, characterized in that: the dielectric trench structure (17) is directly in contact with the P-type collector region (9), and the N-type buffer zone (8) is only in Below the P-type collector region (9), and the depth of the dielectric groove structure (17) is greater than the depth of the P-type RESURF layer (16) and the N-type buffer zone (8). 10. The method for preparing a lateral power device with a mixed conduction mode according to any one of claims 1 to 9, characterized in that it comprises the following steps: Step 1: Select a silicon-on-insulator material, in which the thickness of the substrate is 300-500 microns, the doping concentration is 10 ^{14-10 15} /cm ³ , the thickness of the buried oxide layer on the substrate is 0.5-3 microns, SOI The thickness of the layer is 5-20 microns; The second step: photolithography, by ion-implanting N-type impurities in the right area of the silicon wafer surface and annealing to make an N-type buffer zone, the thickness of the formed N-type buffer zone is 2 to 4 microns; Step 3: Thermal oxidation and deposition of gate electrode material on the surface of the silicon wafer, photolithography, etching part of the gate electrode material and gate oxide layer to form a gate electrode; The fourth step: photolithography, on the left side of the drift region on the surface of the silicon wafer, ion-implant P-type impurities and anneal to make a P-type base region, and the thickness of the formed P-type base region is 2 to 3 microns; The fifth step: photolithography, forming a P-type RESURF layer by implanting P-type impurities with high-energy ions in the middle of the drift region on the surface of the silicon wafer; Step 6: Photolithography, in the middle of the drift region on the surface of the silicon wafer, ion-implant N-type impurities and anneal to make N-striped regions, and the width of the formed N-striped regions is 0.5 to 1 micron; The seventh step: photolithography, in the middle of the drift region on the surface of the silicon wafer, ion-implant P-type impurities and anneal to make a P-strip region, and the width of the formed P-strip region is 0.5 to 1 micron; The eighth step: photolithography, etching and filling medium to form a dielectric groove, the depth of the formed dielectric groove is not less than the depth of the P-type collector region; Step 9: Photolithography, respectively ion-implanting N-type impurities and P-type impurities in the left area of the silicon wafer surface and annealing to make N-type source regions and P-type contact regions, and the formed N-type source regions and P-type contact regions The thickness is about 0.2-0.3 microns; Step 10: Photolithography, ion-implanting P-type impurities on the right side of the silicon wafer surface and annealing to make a P-type collector region, the thickness of the formed P-type collector region is 0.3-0.5 microns; The eleventh step: depositing, photolithography, and etching a dielectric layer to form a dielectric layer; Step 12: Depositing, photolithography, and etching metal to form a metal emitter and a metal collector on the surface of the device; that is, a lateral power device with a mixed conduction mode is prepared.