CN107733568A - The method and device of CRC parallel computations is realized based on FPGA - Google Patents
The method and device of CRC parallel computations is realized based on FPGA Download PDFInfo
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- CN107733568A CN107733568A CN201710864655.7A CN201710864655A CN107733568A CN 107733568 A CN107733568 A CN 107733568A CN 201710864655 A CN201710864655 A CN 201710864655A CN 107733568 A CN107733568 A CN 107733568A
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
- H04L1/0056—Systems characterized by the type of code used
- H04L1/0061—Error detection codes
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
- H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
- H03M13/09—Error detection only, e.g. using cyclic redundancy check [CRC] codes or single parity bit
- H03M13/091—Parallel or block-wise CRC computation
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Abstract
The invention discloses a kind of method and device that CRC parallel computations are realized based on FPGA, this method includes：In interface transmitting terminal, message to be calculated is inputted by corresponding CRC generator polynomials according to the valid data bit wide of input, different straight formulas is obtained from different parallel input valid data bit wides according to CRC generator polynomials and carries out CRC calculating, message to be calculated and the CRC code calculated are carried out registration process and be integrated into message to be sent to send to interface iSCSI receiving end；In interface iSCSI receiving end, message to be sent is inputted by corresponding CRC generator polynomials according to the valid data bit wide received, different straight formulas is obtained from different parallel input valid data bit wides according to CRC generator polynomials and carries out CRC calculating, the CRC code calculated is contrasted with the CRC code carried in message to be sent, obtains CRC check result.The present invention supports the real-time change of valid data bit wide, and compatibility is preferably.
Description
Technical field
The present invention relates to ethernet technology field, and in particular to it is a kind of based on FPGA realize CRC parallel computations method and
Device.
Background technology
CRC (Cyclic Redundancy Check, CRC) is a kind of according to the brief fixed bit of data generation
The hash function of number check code, the mistake for being mainly used to detection or inspection data transmission or being likely to occur after preserving.CRC check
It is widely used in ethernet technology field, the correctness of the Ethernet message content of transmission is detected for receiving terminal.
The core of CRC algorithm is generator polynomial, a variety of generator polynomials such as including CRC8, CRC16 and CRC32, can be fitted
For the multiple interfaces agreement such as Ethernet, video and USB, the realization of CRC check is divided into serial mode and parallel mode, for simultaneously
Row CRC check can generate straight formula according to generator polynomial, and for identical generator polynomial, valid data bit wide difference is then
The straight formula of generation also differs.
, it is necessary to be entered based on internal mac layer interface form to ether network packet in the logic realization in ethernet technology field
Row CRC check.The least unit of Ethernet message length is the number of byte, 1Gbps speed and following ethernet mac layer interface
It it is 4 or 8 according to bit wide, i.e. the valid data bit wide of interface is constant；And the ethernet mac layer interface of 10Gbps speed and the above
A width of more than 32 of data bit, i.e. the valid data bit wide of interface may change in real time.
In view of this, it is badly in need of a kind of CRC Implementation Method for Parallel Computing that can support valid data bit wide real-time change.
The content of the invention
The technical problems to be solved by the invention are to provide a kind of CRC that can support valid data bit wide real-time change simultaneously
Row calculates implementation method.
In order to solve the above-mentioned technical problem, the technical solution adopted in the present invention is to provide one kind and based on FPGA realizes CRC
The method of parallel computation, comprises the following steps：
It is according to the valid data bit wide of input that the corresponding CRC generations of message to be calculated input is multinomial in interface transmitting terminal
Formula, different straight formulas is obtained from different parallel input valid data bit wides according to CRC generator polynomials and carries out CRC meters
Calculate, message to be calculated and the CRC code calculated are carried out registration process and be integrated into message to be sent to send to interface iSCSI receiving end；
It is according to the valid data bit wide received that the corresponding CRC generations of message to be sent input is more in interface iSCSI receiving end
Item formula, obtains different straight formulas from different parallel input valid data bit wides according to CRC generator polynomials and carries out CRC meters
Calculate, the CRC code calculated is contrasted with the CRC code carried in message to be sent, obtains CRC check result.
In the above-mentioned technical solutions, CRC calculating is carried out in interface transmitting terminal or interface iSCSI receiving end, specifically includes following step
Suddenly：
When receiving heading indication signal, carry out initial configuration and CRC calculating is carried out to heading, initialization is matched somebody with somebody
Put and support full 0 or complete 1；
When receiving valid data and when heading indication signal and invalid message trailer indication signal, valid data carried out
CRC is calculated；
When receiving message trailer indication signal, CRC calculating is carried out to message trailer and the CRC code to calculating latches
As CRC result of calculations.
In the above-mentioned technical solutions, heading indication signal and message trailer indication signal use back-to-back input mode.
In the above-mentioned technical solutions, when receiving invalid data, calculated without CRC.
In the above-mentioned technical solutions, when the CRC code that interface iSCSI receiving end calculates and the CRC code phase that is carried in message to be sent
Meanwhile then CRC check is correct, on the contrary then CRC check mistake.
Present invention also offers a kind of device that CRC parallel computations are realized based on FPGA, including：
The CRC generator for being arranged at interface transmitting terminal and the CRC check device for being arranged at interface iSCSI receiving end, the CRC generations
Device includes the first CRC calculators, data delay module and data aggregation module；The CRC check device includes the 2nd CRC calculators
With magic number detection module；
Message to be calculated is inputted corresponding CRC generator polynomials by interface transmitting terminal according to the valid data bit wide of input,
And send to the first CRC calculators；The first CRC calculators are according to CRC generator polynomials and different parallel inputs
Valid data bit wide obtains different straight formulas and carries out CRC calculating, latches the CRC code calculated and sends to the data and prolongs
Slow module；The CRC code that the data delay module calculates to message to be calculated and the first CRC calculators is carried out at alignment
Reason；Message and CRC code to be calculated after data delay module alignment processing is integrated into pending by the data aggregation module
Text of delivering newspaper is sent to interface iSCSI receiving end；
Interface iSCSI receiving end is multinomial by the corresponding CRC generations of message to be sent input according to the valid data bit wide received
Formula, and send to the 2nd CRC calculators；The 2nd CRC calculators according to CRC generator polynomials from it is different parallel defeated
Enter valid data bit wide to obtain different straight formulas and carry out CRC calculating, latch the CRC code calculated and send to the magic number
Detection module；Carried in CRC code and message to be sent that the magic number detection module calculates the 2nd CRC calculators
CRC code is contrasted, and obtains CRC check result.
In the above-mentioned technical solutions, the first CRC calculators or the 2nd CRC calculators refer to according to the heading received
Show that signal carries out initial configuration, and CRC calculating is carried out to heading, initial configuration supports full 0 or complete 1；According to reception
The valid data arrived and invalid heading indication signal and message trailer indication signal, CRC calculating is carried out to valid data；Root
According to the message trailer indication signal received, CRC calculating is carried out to message trailer and the CRC code to calculating latch and is used as CRC
Result of calculation.
In the above-mentioned technical solutions, the heading instruction letter that the first CRC calculators and the 2nd CRC calculators receive
Number and message trailer indication signal use back-to-back input mode.
Message is inputted corresponding CRC generator polynomials by the present invention according to the valid data bit wide of input, is generated according to CRC
Multinomial obtains different straight formulas from different parallel input valid data bit wides and carries out CRC calculating, supports valid data
The real-time change of bit wide, compatibility is preferable, the compatible constant 1Gbps speed of valid data bit wide and following interface, and
The interface of the variable 10Gbps speed of valid data bit wide and the above.
Brief description of the drawings
Fig. 1 is a kind of method flow diagram that CRC parallel computations are realized based on FPGA provided in an embodiment of the present invention；
Fig. 2 is a kind of apparatus structure schematic diagram that CRC parallel computations are realized based on FPGA provided in an embodiment of the present invention；
Fig. 3 is input/output interface timing diagram provided in an embodiment of the present invention.
Embodiment
The present invention is described in detail with reference to specification drawings and specific embodiments.
The embodiments of the invention provide a kind of method that CRC parallel computations are realized based on FPGA, as shown in figure 1, including with
Lower step：
S1, in Ethernet interface transmitting terminal, message to be calculated is inputted by corresponding CRC according to the valid data bit wide of input
Generator polynomial, different straight formulas is obtained from different parallel input valid data bit wides according to CRC generator polynomials and gone forward side by side
Row CRC is calculated.
Message to be calculated includes heading indication signal, message trailer indication signal, message valid data indication signal, message
Valid data bit wide indication signal and message valid data.
S2, registration process is carried out to message to be calculated and the CRC code calculated and is integrated into message to be sent, selection is corresponding
Data path the message to be sent after integration is sent to Ethernet interface receiving terminal.
S3, in Ethernet interface receiving terminal, message to be sent is inputted to corresponding according to the valid data bit wide received
CRC generator polynomials, different straight formulas is obtained from different parallel input valid data bit wides according to CRC generator polynomials
And carry out CRC calculating.
S4, the CRC code calculated contrasted with the CRC code carried in message to be sent, CRC check is being just if identical
Really, on the contrary then CRC check mistake.
The embodiment of the present invention additionally provides a kind of device that CRC parallel computations are realized based on FPGA, as shown in Fig. 2 including：
It is arranged at the CRC generator of Ethernet interface transmitting terminal and is arranged at the CRC check device of Ethernet interface receiving terminal,
The CRC generator includes the first CRC calculators 10, data delay module 11 and data aggregation module 12；The CRC check device includes
2nd CRC calculators 20 and magic number detection module 21；
Ethernet interface transmitting terminal is more by the corresponding CRC generations of message to be calculated input according to the valid data bit wide of input
Item formula, and send to the first CRC calculators 10；First CRC calculators 10 are according to CRC generator polynomials and different parallel inputs
Valid data bit wide obtains different straight formulas and carries out CRC calculating, latches the CRC code calculated and sends to data delay mould
Block 11；The CRC code that data delay module 11 calculates to message to be calculated and the first CRC calculators 10 carries out registration process；Number
The message and CRC code to be calculated after the registration process of data delay module 11 are integrated into completely pending deliver newspaper according to convergence module 12
Text, corresponding data path is selected to send message to be sent to Ethernet interface receiving terminal；
Message to be sent is inputted corresponding CRC according to the valid data bit wide received and generated by Ethernet interface receiving terminal
Multinomial, and send to the second CRC calculators 20；2nd CRC calculators 20 according to CRC generator polynomials from it is different parallel defeated
Enter valid data bit wide to obtain different straight formulas and carry out CRC calculating, latch the CRC code calculated and send to magic number and detect
Module 21；The CRC code that magic number detection module 21 calculates the 2nd CRC calculators 20 and the CRC code carried in message to be sent
Contrasted, CRC check is correct if identical, on the contrary then CRC check mistake.
Magic number detection module 21 is realized without being re-fed into second after the message to be sent after integration is isolated into CRC code
CRC calculators 20, substantially increase treatment effeciency.
With reference to Fig. 3 input/output interface timing diagram, to the first CRC calculators 10 or the 2nd CRC in the present embodiment
The realization principle of calculator 20 is described in further detail：
When the first CRC calculators 10 or the 2nd CRC calculators 20 receive heading indication signal, carry out initialization and match somebody with somebody
Put and CRC calculating is carried out to heading, initial configuration supports full 0 or complete 1；Indicated when receiving valid data and heading
When signal and invalid message trailer indication signal, normal CRC calculating is carried out to valid data；When receiving message trailer indication signal
When, CRC calculating is carried out to message trailer and the CRC code to calculating carries out latching the CRC result of calculations as this message.When connecing
When receiving invalid data, calculated without CRC.
The first CRC calculators 10 and the 2nd CRC calculators 20 are based on pipelined architecture, better performances, branch in the present embodiment
The back-to-back input of the heading indication signal and message trailer indication signal of message is held, transmission delay is smaller and constant, does not expend
Cache resources.And the present embodiment also supports " the breach transmission " of message, i.e., CRC is only carried out when message data effectively indicates
Calculate, otherwise keep.
The present embodiment supports the valid data bit wide real-time variable of message, and due to Ethernet, minimum unit of transfer is word
Section, so achieving that the bit wide real-time, tunable that big bit wide inputs parallel using less straight formula.Therefore compatibility preferably, can
The constant 1Gbps speed of compatible valid data bit wide and following ethernet mac layer interface, and valid data bit wide are variable
The ethernet mac layer interface of 10Gbps speed and the above.
The present embodiment does not limit to applied to Ethernet interface, by straight formula, input initial value, output XOR and line sequence
Flexible configuration, can apply to the various interface protocols using CRC check, and application scenarios are extensive.
The present embodiment is applied on IPRAN and PTN device, and it is configured flexibly and performance is excellent, can be applied to various needs
The application scenarios that CRC is calculated.
The present invention is not limited to above-mentioned preferred forms, anyone structure change made under the enlightenment of the present invention,
The technical schemes that are same or similar to the present invention, each fall within protection scope of the present invention.
Claims (8)
- A kind of 1. method that CRC parallel computations are realized based on FPGA, it is characterised in that comprise the following steps：In interface transmitting terminal, message to be calculated is inputted by corresponding CRC generator polynomials, root according to the valid data bit wide of input Different straight formulas is obtained from different parallel input valid data bit wides according to CRC generator polynomials and carry out CRC calculating, treat Calculate message and the CRC code calculated carries out registration process, and be integrated into message to be sent and send to interface iSCSI receiving end；In interface iSCSI receiving end, message to be sent is inputted by corresponding CRC generator polynomials according to the valid data bit wide received, Different straight formulas is obtained from different parallel input valid data bit wides according to CRC generator polynomials and carries out CRC calculating, will The CRC code calculated is contrasted with the CRC code carried in message to be sent, obtains CRC check result.
- 2. the method as described in claim 1, it is characterised in that carry out CRC calculating, tool in interface transmitting terminal or interface iSCSI receiving end Body comprises the following steps：When receiving heading indication signal, carry out initial configuration and CRC calculating, initial configuration branch are carried out to heading Hold full 0 or complete 1；When receiving valid data and when heading indication signal and invalid message trailer indication signal, CRC carried out to valid data Calculate；When receiving message trailer indication signal, CRC calculating is carried out to message trailer and the CRC code to calculating carries out latch conduct CRC result of calculations.
- 3. method as claimed in claim 2, it is characterised in that heading indication signal and message trailer indication signal are used and leaned against The input mode of the back of the body.
- 4. method as claimed in claim 2, it is characterised in that when receiving invalid data, calculated without CRC.
- 5. the method as described in claim 1, it is characterised in that when the CRC code that interface iSCSI receiving end calculates and message to be sent When the CRC code of middle carrying is identical, then CRC check is correct, on the contrary then CRC check mistake.
- A kind of 6. device that CRC parallel computations are realized based on FPGA, it is characterised in that including：The CRC generator for being arranged at interface transmitting terminal and the CRC check device for being arranged at interface iSCSI receiving end, the CRC generator bag Include the first CRC calculators, data delay module and data aggregation module；The CRC check device includes the 2nd CRC calculators and evil spirit Number detection module；Message to be calculated is inputted corresponding CRC generator polynomials by interface transmitting terminal according to the valid data bit wide of input, concurrently Deliver to the first CRC calculators；The first CRC calculators are effective according to CRC generator polynomials and different parallel inputs Data bit width obtains different straight formulas and carries out CRC calculating, latches the CRC code calculated and sends to the data delay mould Block；The CRC code that the data delay module calculates to message to be calculated and the first CRC calculators carries out registration process； Message and CRC code to be calculated after data delay module alignment processing is integrated into pending deliver newspaper by the data aggregation module Text is sent to interface iSCSI receiving end；Message to be sent is inputted corresponding CRC generator polynomials by interface iSCSI receiving end according to the valid data bit wide received, and Send to the 2nd CRC calculators；The 2nd CRC calculators have according to CRC generator polynomials from different parallel inputs Effect data bit width obtains different straight formulas and carries out CRC calculating, latches the CRC code calculated and sends to the magic number and detects Module；The CRC code that the magic number detection module calculates the 2nd CRC calculators and the CRC carried in message to be sent Code is contrasted, and obtains CRC check result.
- 7. device as claimed in claim 6, it is characterised in that the first CRC calculators or the 2nd CRC calculators are according to connecing The heading indication signal that receives carries out initial configuration, and CRC calculating is carried out to heading, initial configuration support full 0 or Person complete 1；According to the valid data and invalid heading indication signal and message trailer indication signal received, to valid data Carry out CRC calculating；According to the message trailer indication signal received, CRC calculating is carried out to message trailer and the CRC code to calculating enters Row latches and is used as CRC result of calculations.
- 8. device as claimed in claim 7, it is characterised in that the first CRC calculators and the 2nd CRC calculators receive Heading indication signal and message trailer indication signal use back-to-back input mode.
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| CN115987460A (en) * | 2023-03-21 | 2023-04-18 | 深圳华锐分布式技术股份有限公司 | Data transmission method, device, equipment and medium based on check code |
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