CN107463126A - Unmanned plane double-core control system and digital independent and wiring method - Google Patents
Unmanned plane double-core control system and digital independent and wiring method Download PDFInfo
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- G—PHYSICS
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- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B19/00—Programme-control systems
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- G05B19/04—Programme control other than numerical control, i.e. in sequence controllers or logic controllers
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- G—PHYSICS
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- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
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Abstract
The invention discloses a kind of unmanned plane double-core control system and digital independent and wiring method：Primary processor, the flight for unmanned plane controls, including reads steering wheel and each sensing data, and carries out flight control and resolve, and exports steering wheel desired locations；Communication module, for the primary processor and the data exchange from processor；From processor, for the control of steering wheel, including steering wheel desired locations and each sensing data are read, and carry out servos control resolving, output steering wheel current location.The present invention is distributed by hardware resource, steering wheel configuration interface function and high-speed communication interface function are reasonable in design, disclosure satisfy that the requirement of the high speed reliable collaborative work of double-core chip.
Description
Technical field
The present invention relates to unmanned aerial vehicle (UAV) control technical field, and in particular to a kind of unmanned plane double-core control system and digital independent
With wiring method.
Background technology
With the rapid development of IC designing techniques, modern micro-chip processor towards on-chip system (System On Chip,
SOC direction) is developed, and function is also stronger and stronger.Such as this paper research object --- Xilinx companies released in 2012
7000 serial SOCs of ZYNQ, there are 2 ARM A9 stones (CPU), substantial amounts of FPGA resource (wherein also includes abundant
DSP resources), about 512K SRAM (high-speed memory in piece), abundant interface logic, and the bus on chip resource of high speed.This
The key technology of 2 ARM A9 CPU reliable collaborative work in the literary main SOCs of research Xilinx ZYNQ 7000.
The content of the invention
Instant invention overcomes the deficiencies in the prior art, there is provided a kind of unmanned plane double-core control system and digital independent and write-in
Method, it is intended to reach the purpose of high speed reliable collaborative work.
In view of the above mentioned problem of prior art, according to one side disclosed by the invention, the present invention uses following technology
Scheme：
A kind of unmanned plane double-core control system, including：
Primary processor, the flight for unmanned plane controls, including reads steering wheel and each sensing data, and carries out flight control
System resolves, and exports steering wheel desired locations；
Communication module, for the primary processor and the data exchange from processor；
From processor, for the control of steering wheel, including steering wheel desired locations and each sensing data are read, and carry out steering wheel
Control resolves, output steering wheel current location.
In order to which the present invention is better achieved, further technical scheme is：
According to one embodiment of the invention, the primary processor and/or it is described from processor be Xilinx ZYNQ
7000 SOCs.
According to another embodiment of the invention, the primary processor and/or it is described matched somebody with somebody out of processor it is independent
External memory space.
According to another embodiment of the invention, in the case of system starts, the primary processor and/or institute
State from processor and open on-chip cache and second level cache.
According to another embodiment of the invention, the primary processor and the SRAM that configured from processor store money
Source, forbid refreshings of the CACHE to OCM resources, what the SRAM storage resources exchanged for primary processor and from processor data
Shared drive and the stack space for primary processor and from processor.
According to another embodiment of the invention, the primary processor and described independent in start-up course from processor
Initialized.
According to another embodiment of the invention, by the primary processor and the variable from the needs that communicated between processor
Or array distribution in OCM common memory sections to realize the primary processor and high-speed communication from processor.
The present invention can also be：
A kind of method for reading data in unmanned plane double-core control system, including：
1) from processor before rudder control amount HELMCTR is accessed, first by accessing rudder control mark HELMCTRFLAG, really
Determine whether rudder control amount HELMCTR can access；
If 2) rudder control amount may have access to, qualification is accessed obtaining HELMCTR from processor；If rudder control amount can not visit
Ask, show that primary processor accesses HELMCTR, then after waiting for a period of time, go to step 5)；
3) in the case of from processor modification rudder control mark HELMCTRFLAG, it should wait for a period of time, then sentence again
The disconnected access qualification that HELMCTR whether is remained in that from processor；
4) if HELMCTR is finally obtained from processor accesses qualification, step 5) is gone to；Otherwise, after waiting for a period of time,
Go to step 5)；
5) rudder control amount is read.
The present invention can also be：
A kind of method for writing data in unmanned plane double-core control system, it is characterised in that including：
1) primary processor is before rudder control amount HELMCTR is accessed, first by accessing rudder control mark HELMCTRFLAG, really
Determine whether rudder control amount HELMCTR can access；
If 2) rudder control amount may have access to, primary processor obtains HELMCTR and accesses qualification；If rudder control amount inaccessible, table
It is bright to access HELMCTR from processor, then after waiting for a period of time, go to step 5)；
3) during primary processor modification rudder control mark HELMCTRFLAG, it should wait for a period of time, then sentence again
The disconnected access qualification that HELMCTR whether is remained in that from processor；
4) in the case where finally obtaining HELMCTR from core and accessing qualification, step 5) is gone to；Otherwise, wait for a period of time
Afterwards, step 5) is gone to；
5) rudder control amount is write.
Compared with prior art, one of beneficial effects of the present invention are：
A kind of unmanned plane double-core control system and digital independent and wiring method of the present invention, distributed by hardware resource,
Steering wheel configures interface function and high-speed communication interface function is reasonable in design, almost loses several phenomenons without communication, disclosure satisfy that
The requirement of the high speed reliable collaborative work of double-core chip.
Brief description of the drawings
, below will be to embodiment for clearer explanation present specification embodiment or technical scheme of the prior art
Or the required accompanying drawing used is briefly described in the description of prior art, it should be apparent that, drawings in the following description are only
It is the reference to some embodiments in present specification, for those skilled in the art, is not paying creative work
In the case of, other accompanying drawings can also be obtained according to these accompanying drawings.
Fig. 1 is the system architecture block diagram according to one embodiment of the invention.
Fig. 2 is that main core external storage resources distribute schematic diagram.
Fig. 3 is to distribute schematic diagram from core external storage resources.
Fig. 4 is main core and distributes schematic diagram from core stack segment space.
Fig. 5 is schematic flow sheet of the main core startup from core.
Fig. 6 is OCM digital independent schematic flow sheets.
Fig. 7 is that OCM data write schematic flow sheet.
Fig. 8 is that Dinuclear Systems rudder control rudder returns curve synoptic diagram.
Fig. 9 is that Dinuclear Systems rudder control rudder returns curve (partial enlargement) schematic diagram.
Embodiment
The present invention is described in further detail with reference to embodiment, but the implementation of the present invention is not limited to this.
The application scenarios of the present invention can be that the flight of unmanned plane controls, and its system architecture is as shown in figure 1, using Xilinx
The CPU0 (hereinafter main core) of the SOCs of ZYNQ 7000 realizes flight control (the main core hardware initialization completion of unmanned plane
Afterwards, start from core, then read steering wheel and other sensors data, and carry out flight control and resolve, finally export steering wheel
Desired locations), realized using CPU1 (hereinafter from core) servos control (after core startup, complete hardware initialization first,
Then steering wheel desired locations and other sensors data are read, and carry out servos control resolving, finally export steering wheel present bit
Put), wherein main core and between core pass through multiple nucleus system high speed reliable communication module carry out data exchange.Obviously, above-mentioned framework
Miniaturization and low power dissipation design for unmanned aerial vehicle control system have a clear superiority.
1) how implementation below to shared hardware resource by from dividing according to the actual requirements2) it is how effective
Scheduling hardware resource, avoid access conflict3) main core and reality is discussed how in terms of the high speed reliable communication between core is several
The reliable collaborative work of the existing SOC Dinuclear Systems of Xilinx ZYNQ 7000.
Hardware resource distributes：
Outside SDRAM resources：Main core flight control program and from core servos control journey during the operation of outside SDRAM resource systems
The memory space of sequence (including data), in order to avoid access conflict, independent external memory space is assigned with for main core and from core,
(memory allocation of ZYNQ SOC family chips is completed in lscript.ld files) as shown in Figure 2 and Figure 3, main core it is outer
Portion's ram space is Base Address (0x01000000), Size (0x03000000)；The external RAM space of main core is Base
Address(0x04000000),Size(0x01000000)。
Cache CACHE resources：After system starts, main core and the code from core are run in outside SDRAM,
The speed of service is slower.ZYNQ SOC family chips possess on-chip cache (L1) and second level cache (L2) and high-performance
Cache algorithm, in order to ensure main core and code execution speed from core, it is necessary to open L1 and L2 caches (experiment table for it
Bright, after opening L1 and L2 caches, the execution speed ratio of code is not turned on about 10 times soon of L1 and L2 caches).
Can be by opening L1 and L2 caches with minor function：
OCM resources in piece：ZYNQ 7000SOC are configured with high performance upper SRAM storage resources (On Chip
Memroy,OCM)., it is necessary to forbid refreshings of the CACHE to OCM resources in the design, and use it for：
1) main core and from Nuclear Data exchange shared drive (shown in Fig. 2, Fig. 3 as shown, Base Address
(0xFFFF0000),Size(0x00001000))；
2) main core and from the stack space of core (shown in Fig. 2, Fig. 3 as shown, Base Address (0Xffff1000),
Size(0x0000EE00).Experiment shows, uses outside SDRAM to make as the execution speed ratio of stack space code using OCM
It is fast about 30%) for stack space.Main core and as shown in Figure 4 from the distribution of the stack segment space of core.
Hardware resource access conflict：Due to the Xilinx main cores of ZYNQ 7000SOC chips (Flight Control Software) and from core
Most peripheral resources are have shared, share the hard of part peripheral resources (such as L2, CAN, UART, GPIO and global TIMER)
Part initialization is completed by main core.If main core and from core to shared peripheral hardware, such as UART, initialized, due to from core
What is started is more late, then is worked from the configuration of core, and main core then can not the normal use peripheral resources.Main core and from the non-common of core
Resource (such as L1, privately owned TIMER) is enjoyed independently to be initialized by each core.
Double-core high-speed reliable communication Mechanism Design：
The hardware foundation of communication：As described above, using OCM as main core and from the high-speed communication shared drive between core.
The address of shared drive is Base Address (0xFFFF0000), Size (0x00001000), this be one section with
0xFFFF0000 is the 4K address spaces of initial address, is available for main core and below 4K data exchange is carried out from core.If main core
The data volume that exchanges is needed more than 4K with from core, then can configure data space length (such as data volume of shared drive according to demand
For 15K, then it is 0x00004000 to configure Size).
The secondary distribution of OCM shared drive resources：As shown in Figure 3, program and data store and operate in outside SDRAM
Space (0x01000000~0x04000000), the speed of service is relatively slow.In order to realize main core and lead to from the high speed between core
Letter, it can be distributed by code below by main core and from the variable or array of the needs that communicated between core in OCM common memory sections
(speed that 0Xffff0000~0Xffff1000, CPU access OCM spaces is more much faster than outside SDRAM).
#define HELMCTRFLAG(*(volatile int*)(0xFFFF0000))
#define HELMCTR(*(volatile float*)(0xFFFF0004))
#define HELMBACKFLAG(*(volatile int*)(0xFFFF0010))
#define HELMBACK(*(volatile float*)(0xFFFF0014))
#define HELMCFGOCMADDR(unsigned char*)(0xFFFF0020)
#define HELMCFGLEN 32
Wherein：
HELMCTRFLAG distributes 4 bytes since 0xFFFF0000, can store 1 int data, is grasped for rudder control
Work indicates, 0x00 represents operable (read-write) states of HELMCTR, non-zero x00 expressions HELMCTR by other CPU operations, when
Preceding cpu is not available for operating；0x01 represents that cpu0 operates HELMCTR, and 0x02 represents that cpu1 operates HELMCTR；
HELMBACKFLAG distributes 4 bytes since 0xFFFF0010, can store 1 int data, and behaviour is returned for rudder
Work indicates, 0x00 represents operable (read-write) states of HELMBACK, non-zero x00 expressions HELMBACK by other CPU operations,
Current cpu is not available for operating, and 0x01 represents that cpu0 operates HELMBACK, and 0x02 represents that cpu1 is operated
HELMBACK；
HELMCTR distributes 4 bytes since 0xFFFF0004, can store 1 float data, be rudder control amount.It is main
Rudder control amount is write HELMCTR by core, and HELMCTR is read from core, so as to realize main core to the high-speed communication for sending data from core；
HELMBACK distributes 4 bytes since 0xFFFF0014, can store 1 float data, be the rudder amount of returning.
HELMBACK is write from core by the rudder amount of returning, main core reads HELMBACK, so as to realize the high-speed communication that data are sent from core to main core；；
HELMCFGOCMADDR is unsigned char pointers, since 0xFFFF0020,32 byte spaces afterwards
For storing 8 float data (steering wheel configuration parameter).System initialization configure when, main core by steering wheel configuration parameter write with
The address space that HELMCFGOCMADDR starts, after core startup, HELMCFGOCMADDR address spaces are read, obtain steering wheel
Configuration parameter, then complete the initialization operation from core；
HELMCFGLEN is steering wheel configuration parameter length, 8 float parameters, totally 32 byte.
Interface function designs：
Designed from core run function：The double-core working mechanism of Xilinx ZYNQ 7000SOC chips is that main core (cpu0) is first
Start, after completing hardware initialization, main core, which is performed from core (cpu1), starts code, starts and is started working from core.Main core start from
The flow of core is returned shown in curve such as Fig. 8 Dinuclear Systems rudder control rudders：
Main core starts as follows from core programming：
Wherein, A9_CPU_RST_CTRL etc. is predefined from core startup relative address, u32 expression unsigned int
Type (identical hereinafter).
In the design, OCM spaces are used for main core and from the shared drives between core, it is necessary to call Xil_
SetTlbAttributes (0xFFFF0000,0x14de2), forbid access of the CACHE to OCM.Resetted from core and start code
The standardization program provided for xilinx officials.
As shown in figure 1, on main core after electricity, the hardware initialization of itself is completed first, then performs cpu1Start () interface
Function, start from core.Then main core enters flight control circulation, and starts since core is then, at the beginning of the hardware for then completing itself
Beginningization, subsequently enter servos control circulation.Afterwards, main core and from core it is parallel it is independent carry out the work, and pass through OCM shared drives
Carry out data exchange (seeing below text).
High Speed Communication Interface Design：From Dinuclear Systems framework and the above, main core and from core by accessing identical
(rudder control amount is write HELMCTR to OCM address spaces by main core, and HELMCTR is read from core, so as to realize that main core sends number to from core
According to high-speed communication) enter row data communication, and main core and from core be it is separate organize work, may from certain probability
There is main core and from core while access the situation of identical OCM address spaces：When such as main core is currently written into rudder control data, exist from core
Same time point reads rudder control data；When being currently written into rudder from core and returning data, main core reads rudder in same time point and returns data.It is right
The access conflict of OCM shared drives, rudder control and rudder can be caused to return corrupt data, so as to have a strong impact on systemic-function and performance.
Main core and from verification identical OCM address spaces conduct interviews when, in fact it could happen that following several situations (are needed with main core
Exemplified by accessing)：
When main core accesses, accessed from core, now obtaining access right from core, main core, which should wait accessing from core, to be terminated, so
After visit again；
1st, when main core accesses, do not access from core, after main core waits one section of tiny time, still do not accessed from core, this
When main core obtain access right；
2nd, when main core accesses, do not access from core, after main core waits one section of tiny time, accessed from core, now from
Core obtains access right, and main core, which should wait accessing from core, to be terminated, and is then visited again.
3rd, main core and from core generally each controlling cycle (such as 10ms) access OCM once, access time is typically us
Level.So in above-mentioned 3 in situation, 2 be Great possibility (more than 95%), and 1 and 3 be small probability event.Wherein, 3 main core is represented
Almost OCM is accessed with from core in same time, main core and successively have modified access flag from core, and thinks oneself to obtain
Access right, if dealt with improperly, necessarily there are access errors.
In order to thoroughly avoid the access conflict of OCM shared drives, main core and the browsing process from verification OCM are devised, and
Based on this, devise OCM digital independents interface function and (main core and OCM shared drives are not directly accessed from core, it is necessary to logical
Cross calling interface function and access OCM shared drives).
OCM digital independents flow is as shown in fig. 6, the core concept of above-mentioned flow is following (exemplified by reading rudder control amount from core)：
1st, first by accessing rudder control mark HELMCTRFLAG, rudder is determined before rudder control amount HELMCTR is accessed from core
Whether control amount HELMCTR can access (HELMCTRFLAG is that 0 expression can access)；
If the 2, rudder control amount may have access to, it is 2 to put HELMCTRFLAG, shows that HELMCTR is tentatively obtained from core accesses money
Lattice；If rudder control amount inaccessible, shows that main core accesses HELMCTR, then after waiting the tWait times, step 5 is gone to；
3rd, during in order to avoid being 2 from core modification HELMCTRFLAG, main core is also in modification HELMCTRFLAG marks
(i.e. main core and almost need to access rudder control amount at the same time from core), should wait 1us, then judge whether remain in that again from core
HELMCTR access qualification (HELMCTRFLAG 2)；
If the 4, HELMCTRFLAG is 2, show that HELMCTR is finally obtained from core accesses qualification, goes to step 5；Otherwise,
After waiting the tWait times, step 5 is gone to；
5th, rudder control amount is read；
6th, read rudder control amount to terminate, put HELMCTRFLAG as 0.
It is as follows to read the design of OCM shared drives interface function：
Wherein, val represents rudder control or the rudder amount of returning；Type is that 0x00 represents rudder control, and 0x01 represents that rudder returns；TWait is represented
Stand-by period during access conflict, because OCM access speeds are very fast, tWait is usually Microsecond grade.Main core can pass through
ReadHelm (s ＆HelmBack, 1) reading rudder from OCM returns data, from core can by ReadHelm (s ＆HelmCtl, 0) read from OCM
Take rudder control data.
OCM data write flow as shown in fig. 7, the core concept of above-mentioned flow it is following (using main core write rudder control amount as
Example)：
1st, main core, first by accessing rudder control mark HELMCTRFLAG, determines rudder before rudder control amount HELMCTR is accessed
Whether control amount HELMCTR can access (HELMCTRFLAG is that 0 expression can access)；
If the 2, rudder control amount may have access to, it is 1 to put HELMCTRFLAG, shows that main core tentatively obtains HELMCTR and accesses money
Lattice；If rudder control amount inaccessible, shows to access HELMCTR from core, then after waiting the tWait times, step 5 is gone to；
3rd, during being 1 in order to avoid main core modification HELMCTRFLAG, from core also in modification HELMCTRFLAG marks
(i.e. main core and almost need to access rudder control amount at the same time from core), should wait 1us, then judge whether remain in that again from core
HELMCTR access qualification (HELMCTRFLAG 1)；
If the 4, HELMCTRFLAG is 1, show that HELMCTR is finally obtained from core accesses qualification, goes to step 5；Otherwise,
After waiting the tWait times, step 5 is gone to；
5th, rudder control amount is write；
6th, write-in rudder control amount terminates, and puts HELMCTRFLAG as 0.
It is as follows to write the design of OCM shared drives interface function：
Wherein, val, type and tWait are same as above.From core can by SetHelm (s ＆HelmBack, 1) rudder returned into number
Is used according to write-in OCM for main core, main core can by SetHelm (s ＆HelmCtl, 0) by rudder control data write-in OCM for from core use.
Design verification：
In application of the design of the present invention by experiment, main core performs Flight Control Software, is controlled from core performing steering wheel soft
Part, main core and carries out high-speed data communication between core by OCM.
The operation result of Dinuclear Systems is as shown in Figure 8 and Figure 9.Red curve is rudder control data, and main core controls by flight
After resolving, call SetHelm (s ＆HelmCtl, 0) rudder control data are write into OCM, from core (call ReadHelm (s ＆HelmCtl, 0)
Rudder control data are read from OCM) rudder control data are tracked by servos control algorithm；Black curve is that rudder returns data, from core
After the rudder for reading and resolving to obtain returns data, call SetHelm (s ＆HelmBack, 1) rudder is returned into data write-in OCM, main core is adjusted
With ReadHelm (s ＆HelmBack, 1) reading rudder from OCM returns data, and is sent to slave computer after rudder control rudder is returned into data packing,
Slave computer can draw out Fig. 8 and Fig. 9.
As shown in Figure 9, rudder returns curve and has perfectly tracked rudder control curve, and communication does not occur and loses several phenomenons, double-core system
The hardware resource distribution of system, steering wheel configure interface function and high-speed communication interface function is reasonable in design, disclosure satisfy that Xilinx
The requirement of 7000 SOCs of ZYNQ, 2 ARM A9 CPU high speed reliable collaborative work.
Each embodiment is described by the way of progressive in this specification, what each embodiment stressed be with it is other
The difference of embodiment, identical similar portion cross-reference between each embodiment.
" one embodiment " for being spoken of in this manual, " another embodiment ", " embodiment ", etc., refer to tying
Specific features, structure or the feature for closing embodiment description are included at least one embodiment of the application generality description
In.It is not necessarily to refer to same embodiment that statement of the same race, which occur, in multiple places in the description.Appoint furthermore, it is understood that combining
When one embodiment describes a specific features, structure or feature, what is advocated is this to realize with reference to other embodiment
Feature, structure or feature are also fallen within the scope of the present invention.
Although reference be made herein to invention has been described for multiple explanatory embodiments of the invention, however, it is to be understood that
Those skilled in the art can be designed that a lot of other modifications and embodiment, and these modifications and embodiment will fall in this Shen
Please be within disclosed spirit and spirit.More specifically, can be to master in the range of disclosure and claim
The building block and/or layout for inscribing composite configuration carry out a variety of variations and modifications.Except what is carried out to building block and/or layout
Outside variations and modifications, to those skilled in the art, other purposes also will be apparent.
Claims (9)
- A kind of 1. unmanned plane double-core control system, it is characterised in that including：Primary processor, the flight for unmanned plane controls, including reads steering wheel and each sensing data, and carries out flight control solution Calculate, export steering wheel desired locations；Communication module, for the primary processor and the data exchange from processor；From processor, for the control of steering wheel, including steering wheel desired locations and each sensing data are read, and carry out servos control Resolve, output steering wheel current location.
- 2. unmanned plane double-core control system according to claim 1, it is characterised in that the primary processor and/or it is described from Processor is Xilinx ZYNQ 7000SOC chips.
- 3. unmanned plane double-core control system according to claim 1, it is characterised in that the primary processor and/or it is described from Independent external memory space is matched somebody with somebody in processor.
- 4. unmanned plane double-core control system according to claim 1, it is characterised in that in the case of system starts, The primary processor and/or described open on-chip cache and second level cache from processor.
- 5. unmanned plane double-core control system according to claim 1, it is characterised in that the primary processor and described from Manage and SRAM storage resources are configured on device, forbid refreshings of the CACHE to OCM resources, the SRAM storage resources are used for primary processor Stack space with the shared drive exchanged from processor data and for primary processor and from processor.
- 6. unmanned plane double-core control system according to claim 1, it is characterised in that the primary processor and described from Reason device is independently initialized in start-up course.
- 7. unmanned plane double-core control system according to claim 1, it is characterised in that by the primary processor and from processing Communicate the variable of needs between device or array is distributed in OCM common memory sections to realize the primary processor and height from processor Speed communication.
- A kind of 8. method for reading data in unmanned plane double-core control system, it is characterised in that including：1), first by accessing rudder control mark HELMCTRFLAG, rudder is determined before rudder control amount HELMCTR is accessed from processor Whether control amount HELMCTR can access；If 2) rudder control amount may have access to, qualification is accessed obtaining HELMCTR from processor；If rudder control amount inaccessible, Show that primary processor accesses HELMCTR, then after waiting for a period of time, go to step 5)；3) in the case of from processor modification rudder control mark HELMCTRFLAG, should wait for a period of time, then judge again from Whether processor remains in that HELMCTR access qualification；4) if HELMCTR is finally obtained from processor accesses qualification, step 5) is gone to；Otherwise, after waiting for a period of time, go to Step 5)；5) rudder control amount is read.
- A kind of 9. method for writing data in unmanned plane double-core control system, it is characterised in that including：1) primary processor, first by accessing rudder control mark HELMCTRFLAG, determines rudder before rudder control amount HELMCTR is accessed Whether control amount HELMCTR can access；If 2) rudder control amount may have access to, primary processor obtains HELMCTR and accesses qualification；If rudder control amount inaccessible, show from Processor accesses HELMCTR, then after waiting for a period of time, goes to step 5)；3) during primary processor modification rudder control mark HELMCTRFLAG, should wait for a period of time, then judge again from Whether processor remains in that HELMCTR access qualification；4) in the case where finally obtaining HELMCTR from core and accessing qualification, step 5) is gone to；Otherwise, after waiting for a period of time, turn To step 5)；5) rudder control amount is write.
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