CN107396009B - Pulse frequency modulation type image sensor circuit and processing method thereof - Google Patents

Abstract

The present invention relates to integrated circuit technology. The invention solves the problem of complex structure of the prior PFM type image sensor when in high precision, provides a pulse frequency modulation type image sensor circuit and a processing method thereof, and the technical scheme can be summarized as follows: the pulse frequency modulation type image sensor circuit comprises a power supply input end, a photoelectric detector, an integral node capacitor, a comparator, a first integral node reset switch, a counter, a circuit output end, a ground wire, an external control signal input end, a second integral node reset switch, a group of gating control switches, a logic module and a group of fixed reference voltage input ends. The invention has the advantages of reducing the difficulty and complexity of circuit design and being suitable for the pulse frequency modulation type image sensor.

Description

Pulse frequency modulation type image sensor circuit and processing method thereof

technical field

The present invention relates to integrated circuit technology, in particular to a processing circuit of a pulse frequency modulation type image sensor.

Background technique

CMOS image sensors have been widely used in traditional fields such as space remote sensing, industrial machine vision and commercial digital cameras due to their high integration, low power consumption and low cost. Typical CMOS image sensors output signals in the form of voltage or current, and active pixel sensors occupy the mainstream due to their superior comprehensive performance. The working process is as follows: First, the photodetector produces a corresponding response to the ambient light intensity. photocurrent; then, the photocurrent charges (or discharges) the integral capacitor to obtain the corresponding integral voltage; then, the integral voltage controls the output voltage or current by controlling the active stage; The output voltage or current is quantized for output. Dynamic Range (DR, Dynamic Range), as one of the important indicators of the performance of CMOS image sensors, is defined as follows: Dynamic Range is the ratio of the maximum signal that can be processed by the image sensor to the minimum signal amplitude that can be processed. Due to the limited capacitance value of the integrating capacitor, when the integrated current generated by the photodetector is greater than a certain fixed value, the integrating capacitor reaches a saturation state, that is, it cannot continue to produce correct output results for larger optical signals. With the development of manufacturing technology, the process size of integrated circuit manufacturing is getting smaller and smaller, and the power supply voltage on the entire integrated circuit is getting lower and lower. will be reduced, which is not conducive to the performance enhancement of the entire CMOS image sensor.

With the development and improvement of CMOS image sensor technology, many designers gradually apply CMOS image sensors to many technological fields. However, different application environments have different requirements for the design of CMOS image sensors. For example, in the emerging field of artificial vision, in order to detect light signals in the natural environment, CMOS image sensors are required to have a large dynamic range. The dynamic range of light in natural environment can reach 140dB, while most traditional voltage-type or current-type CMOS image sensors only have a linear response range of 60-70dB, so large dynamic range is called an urgent need in the field of CMOS image sensor research. problem solved. In order to realize a CMOS image sensor with a large dynamic range, current researchers have mainly proposed two ways to increase the dynamic range of a CMOS image sensor. One is to change the linear response of the traditional voltage-type or current-type CMOS image sensor to a logarithmic response, thereby increasing the dynamic range. However, this mode of CMOS image sensor is in the logarithmic operating mode, and it is difficult to greatly eliminate it. Fixed pattern noise (FPN, FixedPattern Noise), resulting in a serious deterioration of the final output image quality, this technology needs further improvement; the other is to use the pulse modulation (PM, Pulse Modulation) principle for output, because it no longer uses voltage The value or current value is used to characterize the value of the effective signal, so it does not have the problem of limited dynamic range faced by traditional voltage-type or current-type CMOS image sensors.

PM-type CMOS image sensors can be broadly divided into two types: Pulse Width Modulation (PWM, Pulse Width Modulation) and Pulse Frequency Modulation (PFM, Pulse Frequency Modulation). The typical basic pixel unit circuit structure is shown in Figures 1 and 2. , where Reset in Figure 1 is the reset control signal, Vint is the integration node voltage and Cint is the integration node capacitance, Vref is the reference voltage of the comparator, Vo is the output signal; in Figure 2 Vint is the integration node voltage and Cint is the integration node capacitance , Vref is the reference voltage of the comparator, Vo is the output signal. The pixel unit of the PWM type CMOS image sensor generally includes a photodetector Det1, an integrating capacitor Cint and a comparator. The PWM type CMOS image sensor is characterized by the time difference between the detection reset signal and the comparator inversion signal (ie the integration time). The size of the current generated by the photodetector Det1, the greater the intensity of the light, the greater the current generated by the photodetector Det1, and the smaller the output time difference of the PWM pixel, and vice versa; the pixel unit of the PFM CMOS image sensor generally includes a photoelectric The detector Det1, an integrating capacitor Cint, a comparator and a delay unit, the PFM CMOS image sensor characterizes the current generated by the photodetector Det1 by detecting the frequency of the digital pulse signal at the output end. When the integrated voltage reaches the value of the reference level, the output state of the comparator is reversed to generate a pulse, the greater the light intensity, the greater the current generated by the photodetector Det1, the higher the output pulse frequency of the PFM type pixel, and vice versa Of course. Since the PFM image sensor uses the number of pulses output by the comparator as the quantization result to characterize the light intensity of the actual environment, the PFM image sensor cannot always output an integer number of pulses in a fixed integration time. At the end, there is often a residual voltage on the integrating node (the output of the comparator is not triggered to toggle). Especially in the low light intensity environment, the number of pulses output by the PFM image sensor is small, and even several pulses may occur. imaging.

H.Kayahan et al. (Literature 1, H.Kayahan et al. "A new digital readout integrated circuit (DROIC) with pixel parallel A/D conversion and reduced quantizationnoise," Infrared Physics & Technology, vol. 63, pp. 125–132, Mar. 2014.) proposed a method for extended counting of residual voltage, which is to quantize the residual voltage by additionally increasing the quantization time period, thereby increasing the signal-to-noise ratio of the output result. Its working sequence is shown in Figure 3, in which CLKint and CLKres are the control signals for the integration time period and the extension time period, respectively, and the high level is active; Vint and Vcom are the voltage of the integration node capacitor and the output of the comparator, respectively. The specific working method is as follows: : During the integration time period T _INT , the circuit in this scheme is the same as the traditional PFM structure, and obtains X-bit weighted quantized data by counting the number of times the voltage at the output terminal of the comparator is flipped; during the next extension time period T _RESIDUE , Continue to keep the integration node capacitor charged (or discharged) until the residual voltage value on the integration capacitor is charged (or discharged) to the comparator fixed reference voltage value at the end of the integration time period T _INT , while a fixed clock CLK is used to drive the same counter Count and quantify the required time to obtain Y-bit weighted quantization data; finally, use the peripheral auxiliary circuit and complete the synthetic calculation of the final output data according to the calculation formula, and the calculation formula is as follows:

Wherein N _count is calculated from the X-bit weighted quantized data obtained in the integration time period T _INT , and T _RESIDUE is calculated from the Y-bit weighted quantized data combined with the period of the fixed clock CLK. This method additionally adds an extension time period T _RESIDUE to perform extension counting, which requires an additional control signal, and also wastes a part of the time, which slows down the imaging speed; on the other hand, the two time periods (that is, the integration time period T The quantized data of _INT and the extended time period T _RESIDUE ) need to synthesize the final output result according to the above formula, so an additional peripheral auxiliary circuit for synthesizing the final data is added, which not only occupies additional area, but also increases the complexity of the system-on-chip design with difficulty.

Shahbaz Abbasi et al. (Document 2, Shahbaz Abbasi et al. "A PFM Based DigitalPixel with Off-Pixel Residue Measurement for Small Pitch FPAs". IEEE Transactions on Circuits and Systems II: Express Briefs. Volume: PP, Issue: 99, 2016.) A signal-to-noise ratio (SNR, Signal to Noise Rate) enhancement method for small-sized pixels is proposed. The method is to add a column analog-to-digital converter (ADC, Analog to Digital Converter) outside the pixel to realize the residual voltage. quantification. Its specific working method is as follows: the traditional PFM structure part quantizes the most significant bit (MSB, Most Significant Bit) of the input signal current, and the column analog-to-digital converter structure part quantizes the residual voltage output by the PFM to obtain the least significant bit (LSB, Least Significant Bit). Bit), and finally the MSB data and LSB data are synthesized through the subsequent processing circuit to obtain the final quantized output result. Although this method does not add additional circuits inside the pixels, it adds an analog-to-digital converter and a register (used to store the quantization result of the residual voltage by the analog-to-digital converter) in each column of pixels, which naturally occupies additional layout area ; This method is the same as the method in the above document 1, which requires an additional peripheral auxiliary circuit for the final data synthesis, which not only occupies the area, but also has relatively high design requirements for its speed, which increases the design of the entire system. difficulty.

Y.Chen et al. (Literature 3, Y.Chen et al. "A New Wide Dynamic Range CMOS Pulse-Frequency-Modulation Digital Image Sensor with In-Pixel Variable Reference Voltage" 51st Midwest Symposium on Circuits and Systems, pp.129–132, Aug. 2008) proposed a method of changing the reference voltage, which is to adjust the reference voltage of the comparator by introducing a reference capacitor Cref to the reference voltage input end of the comparator inside the pixel, and to control an adjustment circuit by the potential of the output end of the comparator (that is, the charge/discharge circuit and an inverter, the charge/discharge circuit is mainly composed of the PMOS switch M1 and the NMOS switch M2 in FIG. 4), and a reference voltage whose amplitude increases with the increase of time is generated, and its specific structure is shown in the figure 4 shown. For small photo-generated currents, since the adjustment circuit charges the reference capacitor Cref for a long time, the reference voltage of the comparator is high (closer to the reset voltage of the integrating node capacitor), and the integrating node voltage only needs to change within a small range. The output end of the comparator is triggered to be inverted, so the inversion times of the comparator can be increased, the influence of the residual voltage on the final output result is reduced, the dynamic range of the pixel is widened, and the signal-to-noise ratio of the output is increased. However, this method has a similar reset process to the traditional PFM type image sensor, that is, once the voltage at the output terminal of the comparator is turned over, the integration node will be reset once. It takes a certain amount of time to reset the integrating node capacitance. During the reset time, the integrating node still has photo-generated current flowing in, and the charge flowing into the integrating capacitor will be cleared during this period, which will cause a certain error. Therefore, resetting the integrating node capacitor more times will cause the final output result to be different. On the other hand, the variable reference voltage in this method is adjusted by the charging/discharging circuit by charging/discharging the drain current of its internal transistor, so the variable reference voltage is not a precise linear ramp voltage, which is determined by When it is used as a reference voltage for signal quantization, the linearity of the output result is poor.

SUMMARY OF THE INVENTION

The purpose of the present invention is to solve the problem that the structure of the current PFM type image sensor is complex when the high precision is present, and to provide a pulse frequency modulation type image sensor circuit and a processing method thereof.

The present invention solves its technical problem and adopts the technical scheme that a pulse frequency modulation type image sensor circuit includes a power input end, a photodetector, an integrating node capacitor, a comparator, a first integrating node reset switch, a counter, a circuit output end and a The ground wire is characterized in that it also includes an external control signal input terminal, a set of gating control switches, a logic module and a set of fixed reference voltage input terminals. The integration node reset switch is connected to the power input terminal, one end of the integration node capacitor is connected to the ground wire, and the other end is connected to the negative electrode of the photodetector; among the set of gating control switches and a set of fixed reference voltage terminals, each gating The control switch is in one-to-one correspondence with each fixed reference voltage input terminal, the negative phase input terminal of the comparator is connected to the negative pole of the photodetector, and its positive phase input terminal is respectively connected to the corresponding fixed reference voltage input terminal through each gating control switch. , the output end of the comparator is connected with the counting input end of the counter; the reset end of the counter is connected with the input end of the external control signal, the reset control end of the integral node is connected with the control end of the reset switch of the first integral node, and the output end is used as the control end of the reset switch of the first integral node. The output end of the circuit is connected with the input end of the logic module, each output end of the logic module is in one-to-one correspondence with each gating control switch, and each output end is respectively connected with the control end of the corresponding gating control switch;

In the group of fixed reference voltage terminals, the fixed reference voltage input by each fixed reference voltage terminal is different from the fixed reference voltage input by other fixed reference voltage terminals;

In the counter, every time N pulses are input to the counting input terminal, the reset control terminal of the integration node triggers a pulse to turn on the reset switch of the first integration node, wherein N is a positive integer greater than or equal to 2;

Each of the gating control switches is controlled by the logic module, and only one gating control switch is turned on at the same time, and the rest are turned off;

When the reset control signal is input to the external control signal input terminal to reset the counter, the reset control terminal of the integration node of the counter triggers a pulse to turn on the reset switch of the first integration node, and at the same time, the output terminal of the counter outputs the initial reset signal;

The logic module sorts each gating control switch, and when the count value output by the output end of the detection counter adds L, the next gating control switch is selected to be turned on in sequence, and if there is no next gating control switch, it returns to The first gating control switch is cyclically turned on. When the count value output by the output terminal of the counter is mN or the initial reset signal, the logic module directly returns to the first gating control switch for cyclic conduction, where L is a positive integer greater than or equal to 1, and m is a positive integer greater than or equal to 1.

Specifically, the comparator is a two-stage comparator or an OTA-based symmetric comparator or a dynamic latch comparator or a controllable Schmitt trigger.

Further, the first integration node reset switch is a PMOS switch or an NMOS switch or a CMOS switch or a bootstrap switch.

Specifically, the values of the fixed reference voltages input to the fixed reference voltage terminals are all between the reset voltage of the integration node and the lowest input voltage of the non-inverting input terminal of the comparator, and the fixed reference voltages input to the fixed reference voltage terminals are arranged in sequence , and increase or decrease sequentially according to a fixed amount of change.

Still further, in the set of fixed reference voltage terminals, the number of fixed reference voltage terminals is greater than or equal to N.

A pulse frequency modulation type image sensor circuit, comprising a power input end, a photodetector, an integrating node capacitor, a comparator, a first integrating node reset switch, a counter, a circuit output end and a ground wire, and is characterized in that it also includes an external control signal input terminal, a set of gating control switches, a logic module and a set of fixed reference voltage input terminals, the positive pole of the photodetector is connected to the ground wire, and its negative pole is connected to the power input terminal through the first integration node reset switch, and the integration node capacitance One end is connected to the ground wire, and the other end is connected to the negative electrode of the photodetector; in the set of gating control switches and a set of fixed reference voltage terminals, each gating control switch corresponds to each fixed reference voltage input terminal one-to-one, The negative phase input terminal of the comparator is connected to the negative terminal of the photodetector, the positive phase input terminal is respectively connected to the corresponding fixed reference voltage input terminal through each gating control switch, and the output terminal of the comparator is connected to the counting input terminal of the counter. The reset terminal of the counter is connected with the input terminal of the external control signal, the reset control terminal of the integration node is connected with the control terminal of the reset switch of the first integration node, and the output terminal is used as the output terminal of the circuit and is connected with the input terminal of the logic module, Each output end of the logic module is in one-to-one correspondence with each gating control switch, each output end is respectively connected with the control end of the corresponding gating control switch, and the external control signal input end is connected with the reset input end of the logic module;

In the group of fixed reference voltage terminals, the fixed reference voltage input by each fixed reference voltage terminal is different from the fixed reference voltage input by other fixed reference voltage terminals;

In the counter, every time N pulses are input to the counting input terminal, the reset control terminal of the integration node triggers a pulse to turn on the reset switch of the first integration node, wherein N is a positive integer greater than or equal to 2;

Each of the gating control switches is controlled by the logic module, and only one gating control switch is turned on at the same time, and the rest are turned off;

When the reset control signal is input to the external control signal input terminal to reset the counter, the reset control terminal of the integration node of the counter triggers a pulse to turn on the reset switch of the first integration node;

The logic module sorts each gating control switch, and when the count value output by the output end of the detection counter adds L, the next gating control switch is selected to be turned on in sequence, and if there is no next gating control switch, it returns to The first gating control switch is cyclically turned on. When the count value output by the output terminal of the counter is mN or the reset input terminal receives the reset control signal to reset the counter, the logic module directly returns to the first gating control The switch is cyclically turned on, wherein L is a positive integer greater than or equal to 1, and m is a positive integer greater than or equal to 1.

Specifically, the comparator is a two-stage comparator or an OTA-based symmetric comparator or a dynamic latch comparator or a controllable Schmitt trigger.

Further, the first integration node reset switch is a PMOS switch or an NMOS switch or a CMOS switch or a bootstrap switch.

Specifically, the values of the fixed reference voltages input to the fixed reference voltage terminals are all between the reset voltage of the integration node and the lowest input voltage of the non-inverting input terminal of the comparator, and the fixed reference voltages input to the fixed reference voltage terminals are arranged in sequence , and increase or decrease sequentially according to a fixed amount of change.

Still further, in the set of fixed reference voltage terminals, the number of fixed reference voltage terminals is greater than or equal to N.

A pulse frequency modulation type image sensor circuit, comprising a power input end, a photodetector, an integrating node capacitor, a comparator, a first integrating node reset switch, a counter, a circuit output end and a ground wire, and is characterized in that it also includes an external control signal input terminal, the second integration node reset switch, a set of gating control switches, a logic module and a set of fixed reference voltage input terminals, the positive pole of the photodetector is connected to the ground wire, and its negative pole is connected through the first integration node reset switch and the ground wire respectively. The second integrating node reset switch is connected to the power input terminal, one end of the integrating node capacitor is connected to the ground wire, and the other end is connected to the negative electrode of the photodetector; among the set of gating control switches and a set of fixed reference voltage terminals, each The gating control switch is in one-to-one correspondence with each fixed reference voltage input terminal, the negative phase input terminal of the comparator is connected to the negative pole of the photodetector, and its positive phase input terminal is respectively connected to the corresponding fixed reference voltage input through each gating control switch. The output end of the comparator is connected with the counting input end of the counter; the reset end of the counter is connected with the input end of the external control signal, and the reset control end of the integration node is connected with the control end of the reset switch of the first integration node, and its output The terminal is used as the output terminal of the circuit and is connected to the input terminal of the logic module. The control terminal of the reset switch of the second integration node is connected to the input terminal of the external control signal, and each output terminal of the logic module is in one-to-one correspondence with each gating control switch. Each output terminal is respectively connected with the control terminal of the corresponding gating control switch;

In the group of fixed reference voltage terminals, the fixed reference voltage input by each fixed reference voltage terminal is different from the fixed reference voltage input by other fixed reference voltage terminals;

In the counter, every time N pulses are input to the counting input terminal, the reset control terminal of the integration node triggers a pulse to turn on the reset switch of the first integration node;

Each of the gating control switches is controlled by the logic module, and only one gating control switch is turned on at the same time, and the rest are turned off;

When the reset control signal is input to the external control signal input terminal to reset the counter, the reset switch of the second integration node can be turned on, and the output terminal of the counter outputs the initial reset signal;

The logic module sorts each gating control switch, and when the count value output by the output end of the detection counter adds L, the next gating control switch is selected to be turned on in sequence, and if there is no next gating control switch, it returns to The first gating control switch is cyclically turned on. When the count value output by the output terminal of the counter is mN or the initial reset signal, the logic module directly returns to the first gating control switch for cyclic conduction, where L is a positive integer greater than or equal to 1, and m is a positive integer greater than or equal to 1.

Specifically, the comparator is a two-stage comparator or an OTA-based symmetric comparator or a dynamic latch comparator or a controllable Schmitt trigger.

Further, the first integration node reset switch and/or the second integration node reset switch is a PMOS switch or an NMOS switch or a CMOS switch or a bootstrap switch.

Specifically, the values of the fixed reference voltages input to the fixed reference voltage terminals are all between the reset voltage of the integration node and the lowest input voltage of the non-inverting input terminal of the comparator, and the fixed reference voltages input to the fixed reference voltage terminals are arranged in sequence , and increase or decrease sequentially according to a fixed amount of change.

Still further, in the set of fixed reference voltage terminals, the number of fixed reference voltage terminals is greater than or equal to N. A pulse frequency modulation type image sensor circuit, comprising a power input end, a photodetector, an integrating node capacitor, a comparator, a first integrating node reset switch, a counter, a circuit output end and a ground wire, and is characterized in that it also includes an external control signal input terminal, the second integration node reset switch, a set of gating control switches, a logic module and a set of fixed reference voltage input terminals, the positive pole of the photodetector is connected to the ground wire, and its negative pole is connected through the first integration node reset switch and the ground wire respectively. The second integrating node reset switch is connected to the power input terminal, one end of the integrating node capacitor is connected to the ground wire, and the other end is connected to the negative electrode of the photodetector; among the set of gating control switches and a set of fixed reference voltage terminals, each The gating control switch is in one-to-one correspondence with each fixed reference voltage input terminal, the negative phase input terminal of the comparator is connected to the negative pole of the photodetector, and its positive phase input terminal is respectively connected to the corresponding fixed reference voltage input through each gating control switch. The output end of the comparator is connected with the counting input end of the counter; the reset end of the counter is connected with the input end of the external control signal, and the reset control end of the integration node is connected with the control end of the reset switch of the first integration node, and its output The terminal is used as the output terminal of the circuit and is connected to the input terminal of the logic module. The control terminal of the reset switch of the second integration node is connected to the input terminal of the external control signal, and each output terminal of the logic module is in one-to-one correspondence with each gating control switch. Each output terminal is respectively connected with the control terminal of the corresponding gating control switch, and the external control signal input terminal is connected with the reset input terminal of the logic module;

In the group of fixed reference voltage terminals, the fixed reference voltage input by each fixed reference voltage terminal is different from the fixed reference voltage input by other fixed reference voltage terminals;

In the counter, every time N pulses are input to the counting input terminal, the reset control terminal of the integration node triggers a pulse to turn on the reset switch of the first integration node;

Each of the gating control switches is controlled by the logic module, and only one gating control switch is turned on at the same time, and the rest are turned off;

When the reset control signal is input to the external control signal input terminal to reset the counter, the reset switch of the second integration node can be turned on;

The logic module sorts each gating control switch, and when the count value output by the output end of the detection counter adds L, the next gating control switch is selected to be turned on in sequence, and if there is no next gating control switch, it returns to The first gating control switch is cyclically turned on. When the count value output by the output terminal of the counter is mN or the reset input terminal receives the reset control signal to reset the counter, the logic module directly returns to the first gating control The switch is cyclically turned on, wherein L is a positive integer greater than or equal to 1, and m is a positive integer greater than or equal to 1.

Specifically, the comparator is a two-stage comparator or an OTA-based symmetric comparator or a dynamic latch comparator or a controllable Schmitt trigger.

Further, the first integration node reset switch and/or the second integration node reset switch is a PMOS switch or an NMOS switch or a CMOS switch or a bootstrap switch.

Specifically, the values of the fixed reference voltages input to the fixed reference voltage terminals are all between the reset voltage of the integration node and the lowest input voltage of the non-inverting input terminal of the comparator, and the fixed reference voltages input to the fixed reference voltage terminals are arranged in sequence , and increase or decrease sequentially according to a fixed amount of change.

Still further, in the set of fixed reference voltage terminals, the number of fixed reference voltage terminals is greater than or equal to N. A processing method for a pulse frequency modulation type image sensor circuit, which is applied to the above pulse frequency modulation type image sensor circuit, is characterized by comprising the following steps:

Step 1. Input the reset control signal to the input terminal of the external control signal, reset the capacitor of the integration node to the reset level, reset the counter according to the input reset control signal, reset the logic module, control the first gating control switch to be turned on, and the rest are turned off ;

Step 2. The input reset control signal disconnects the integrating node capacitor from the power input terminal and starts counting;

Step 3. Under the action of the photodetector, the voltage on the capacitor of the integrating node changes. When the voltage is equal to the current conduction fixed reference voltage, the output voltage of the comparator is reversed, and the process goes to step 4;

Step 4. Add L to the output count value of the counter, the logic module controls the current gating control switch to turn off, and turns on the next gating control switch at the same time, and returns to step 3;

Step 5. When the count value of the counter is mN, the reset control terminal of the integration node of the counter outputs a pulse to turn on the reset switch S0 of the first integration node, reset the capacitance of the integration node, and reset the logic module to control the first integration node. The gating control switch is turned on, and the rest are turned off, returning to step 3.

The beneficial effect of the present invention is that, through the above-mentioned pulse frequency modulation type image sensor circuit, it can be seen that by changing the reference voltage input by the non-inverting input terminal of the comparator, it is possible to ensure that the number of resets of the capacitor of the integrating node is not increased while making the comparison The output of the device is flipped more times, which not only reduces the residual voltage on the capacitor of the integration node, but also slows down the degradation of image quality caused by the residual voltage, and avoids complex peripheral auxiliary circuits to synthesize the final output data, reducing the The difficulty and complexity of circuit design.

Description of drawings

FIG. 1 is a schematic structural diagram of a basic pixel unit unit of a PWM type image sensor;

FIG. 2 is a schematic structural diagram of a basic pixel unit unit of a PFM type image sensor;

3 is a schematic diagram of the working sequence of the extended count quantization circuit described in Document 1;

4 is a schematic structural diagram of the variable reference voltage circuit described in Document 3;

5 is a schematic structural diagram of a first pulse frequency modulation type image sensor circuit in an embodiment of the present invention;

6 is a schematic structural diagram of a second pulse frequency modulation type image sensor circuit in an embodiment of the present invention;

7 is a schematic structural diagram of a third pulse frequency modulation type image sensor circuit in an embodiment of the present invention;

8 is a schematic structural diagram of a fourth pulse frequency modulation type image sensor circuit in an embodiment of the present invention;

9 is a schematic structural diagram of a specific example of a third pulse frequency modulation type image sensor circuit in an embodiment of the present invention;

FIG. 10 is a schematic diagram of a working sequence and an output result of the pulse frequency modulation type image sensor circuit in FIG. 9;

Among them, Vint is the voltage of the integration node, Cint is the capacitance of the integration node, Vref is the reference voltage of the comparator, Vo is the output signal, S0 is the reset switch of the first integration node, Det1 is the photodetector, M1 is the PMOS switch, and M2 is the NMOS Switch, M1 and M2 form a charge/discharge circuit, Cref is the reference capacitor, CLKint is the control signal of the integration time period, CLKres is the control signal of the extended time period, Vcom is the voltage of the comparator output, CLK is the fixed clock, Sr is the first Two integration node reset switches, Reset is the reset control signal input from the external control signal input terminal, Vc1 is the first fixed reference voltage, Vc2 is the second fixed reference voltage, Vc3 is the third fixed reference voltage, VcN is the Nth fixed reference voltage , Sc1 is the first gating control switch, Sc2 is the second gating control switch, Sc3 is the third gating control switch, ScN is the Nth gating control switch, VCC is the power input terminal, and Vvref is the reference voltage of the comparator Terminal voltage, that is, the voltage of the non-inverting input terminal, Vcint is the voltage on the integrating capacitor Cint, Vs0 is the voltage on the control terminal of the reset switch S0 of the first integration node, OUT0, OUT1 and OUT2 are the three output terminals of the 3-bit counter respectively. The signal output by the output line.

Detailed ways

The technical solutions of the present invention will be described in detail below with reference to the accompanying drawings and embodiments.

The first pulse frequency modulation type image sensor circuit of the present invention includes a power input terminal, a photodetector, an integrating node capacitor, a comparator, a reset switch of the first integrating node, a counter, a circuit output terminal, a ground wire, an external control A signal input terminal, a set of gating control switches, a logic module and a set of fixed reference voltage input terminals, the positive pole of the photodetector is connected to the ground wire, and its negative pole is connected to the power input terminal through the first integration node reset switch, and the integration node capacitance One end is connected to the ground wire, and the other end is connected to the negative electrode of the photodetector; among a set of gating control switches and a set of fixed reference voltage terminals, each gating control switch corresponds to each fixed reference voltage input terminal one-to-one, and the comparator The negative phase input terminal of the comparator is connected with the negative pole of the photodetector, its positive phase input terminal is respectively connected with the corresponding fixed reference voltage input terminal through each gating control switch, and the output terminal of the comparator is connected with the counting input terminal of the counter; The reset terminal is connected to the input terminal of the external control signal, the reset control terminal of the integration node is connected to the control terminal of the reset switch of the first integration node, the output terminal is used as the output terminal of the circuit, and is connected to the input terminal of the logic module. The output terminals are in one-to-one correspondence with each gating control switch, and each output terminal is respectively connected with the control terminal of the corresponding gating control switch; here, in a group of fixed reference voltage terminals, the fixed reference voltage input by each fixed reference voltage terminal is Different from other fixed reference voltage input with fixed reference voltage; in the counter, every time N pulses are input to the counting input terminal of the counting input terminal, the reset control terminal of the integration node triggers a pulse to turn on the reset switch of the first integration node. , where N is a positive integer greater than or equal to 2; each gating control switch is controlled by the logic module, only one gating control switch is turned on at the same time, and the rest are turned off; when the external control signal input terminal inputs the reset control signal to make When the counter is reset, the reset control terminal of the integration node of the counter triggers a pulse to turn on the reset switch of the first integration node, and at the same time, the output terminal of the counter outputs the initial reset signal; When the count value output by the output terminal adds L, the next gating control switch is selected to be turned on in sequence. If there is no next gating control switch, it will return to the first gating control switch for cyclic conduction. When the output count value is mN or the initial reset signal, the logic module directly returns to the first gating control switch for cyclic conduction, where L is a positive integer greater than or equal to 1, and m is a positive integer greater than or equal to 1.

The second pulse frequency modulation type image sensor circuit of the present invention includes a power input terminal, a photodetector, an integrating node capacitor, a comparator, a reset switch for the first integrating node, a counter, a circuit output terminal, a ground wire, an external control A signal input terminal, a set of gating control switches, a logic module and a set of fixed reference voltage input terminals, the positive pole of the photodetector is connected to the ground wire, and its negative pole is connected to the power input terminal through the first integration node reset switch, and the integration node capacitance One end is connected to the ground wire, and the other end is connected to the negative electrode of the photodetector; among a set of gating control switches and a set of fixed reference voltage terminals, each gating control switch corresponds to each fixed reference voltage input terminal one-to-one, and the comparator The negative phase input terminal of the comparator is connected with the negative pole of the photodetector, its positive phase input terminal is respectively connected with the corresponding fixed reference voltage input terminal through each gating control switch, and the output terminal of the comparator is connected with the counting input terminal of the counter; The reset terminal is connected to the input terminal of the external control signal, the reset control terminal of the integration node is connected to the control terminal of the reset switch of the first integration node, the output terminal is used as the output terminal of the circuit, and is connected to the input terminal of the logic module. The output terminals are in one-to-one correspondence with each gating control switch, each output terminal is respectively connected with the control terminal of the corresponding gating control switch, and the external control signal input terminal is connected with the reset input terminal of the logic module; here, a set of fixed reference voltage terminals In the counter, the fixed reference voltage input by each fixed reference voltage terminal is different from the fixed reference voltage input by other fixed reference voltages; in the counter, every time N pulses are input to the counting input terminal, the reset control terminal of the integral node triggers a pulse, Turn on the reset switch of the first integration node, where N is a positive integer greater than or equal to 2; each gating control switch is controlled by the logic module, only one gating control switch is turned on at the same time, and the rest are turned off; when the external When the reset control signal is input to the control signal input terminal to reset the counter, the reset control terminal of the integration node of the counter triggers a pulse to turn on the reset switch of the first integration node; the logic module sorts the gate control switches, and when the output of the counter is detected When the count value output by the terminal adds L, the next gate control switch is sequentially selected to be turned on. If there is no next gate control switch, it will return to the first gate control switch for cyclic conduction. When the output terminal of the counter outputs When the count value is mN or the reset input terminal receives the reset control signal to reset the counter, the logic module directly returns to the first gating control switch for cyclic conduction, where L is a positive integer greater than or equal to 1, m is a positive integer greater than or equal to 1.

The third pulse frequency modulation image sensor circuit of the present invention includes a power input terminal, a photodetector, an integrating node capacitor, a comparator, a reset switch for the first integrating node, a counter, a circuit output terminal, a ground wire, an external control The signal input terminal, the second integration node reset switch, a set of gating control switches, a logic module and a set of fixed reference voltage input terminals, the positive pole of the photodetector is connected to the ground wire, and its negative pole is respectively passed through the first integration node reset switch and The second integrating node reset switch is connected to the power input terminal, one end of the integrating node capacitor is connected to the ground wire, and the other end is connected to the negative electrode of the photodetector; among the set of gating control switches and a set of fixed reference voltage terminals, each The gating control switch is in one-to-one correspondence with each fixed reference voltage input terminal, the negative phase input terminal of the comparator is connected to the negative pole of the photodetector, and its positive phase input terminal is respectively connected to the corresponding fixed reference voltage input through each gating control switch. The output end of the comparator is connected with the counting input end of the counter; the reset end of the counter is connected with the input end of the external control signal, the reset control end of the integration node is connected with the control end of the reset switch of the first integration node, and the output end is used as the control end of the reset switch of the first integration node. The output end of the circuit is connected to the input end of the logic module, the control end of the second integration node reset switch is connected to the input end of the external control signal, each output end of the logic module is in one-to-one correspondence with each gating control switch, and each output end The terminals are respectively connected with the control terminal of the corresponding gating control switch; here, in a group of fixed reference voltage terminals, the fixed reference voltage input by each fixed reference voltage terminal is different from the fixed reference voltage input by other fixed reference voltages; in the counter , every time N pulses are input to the counting input terminal, the reset control terminal of the integration node triggers a pulse to turn on the reset switch of the first integration node; each gating control switch is controlled by the logic module, and there is only one gating at the same time. The control switch is turned on, and the rest are turned off; when the reset control signal is input to the external control signal input terminal to reset the counter, the reset switch of the second integration node can be turned on, and the output terminal of the counter outputs the initial reset signal; the logic module is for each selection Sort through the control switch. When the count value output by the output terminal of the detection counter increases by L, the next gate control switch is selected to be turned on in sequence. If there is no next gate control switch, it will return to the first gate control switch. Circular conduction is performed. When the count value output by the output terminal of the counter is mN or the initial reset signal, the logic module directly returns to the first gating control switch for cyclic conduction, where L is a positive integer greater than or equal to 1 , m is a positive integer greater than or equal to 1.

The fourth pulse frequency modulation type image sensor circuit of the present invention includes a power input terminal, a photodetector, an integrating node capacitor, a comparator, a reset switch for the first integrating node, a counter, a circuit output terminal, a ground wire, an external control The signal input terminal, the second integration node reset switch, a set of gating control switches, a logic module and a set of fixed reference voltage input terminals, the positive pole of the photodetector is connected to the ground wire, and its negative pole is respectively passed through the first integration node reset switch and The second integrating node reset switch is connected to the power input terminal, one end of the integrating node capacitor is connected to the ground wire, and the other end is connected to the negative electrode of the photodetector; among a set of gating control switches and a set of fixed reference voltage terminals, each gating The control switch is in one-to-one correspondence with each fixed reference voltage input terminal, the negative phase input terminal of the comparator is connected to the negative pole of the photodetector, and its positive phase input terminal is respectively connected to the corresponding fixed reference voltage input terminal through each gating control switch. , the output end of the comparator is connected with the counting input end of the counter; the reset end of the counter is connected with the input end of the external control signal, the reset control end of the integration node is connected with the control end of the reset switch of the first integration node, and the output end is used as the circuit output The control terminal of the second integration node reset switch is connected to the input terminal of the external control signal, and each output terminal of the logic module corresponds to each gating control switch one by one, and each output terminal is respectively It is connected with the control terminal of the corresponding gating control switch, and the external control signal input terminal is connected with the reset input terminal of the logic module; here, in a set of fixed reference voltage terminals, the fixed reference voltage input by each fixed reference voltage terminal is the same as that of other fixed reference voltage terminals. The fixed reference voltage of the fixed reference voltage input is different; in the counter, every time N pulses are input to the counting input terminal of the counter, the reset control terminal of the integration node triggers a pulse to turn on the reset switch of the first integration node; In the control of the logic module, only one gate control switch is turned on at the same time, and the rest are turned off; when the external control signal input terminal inputs the reset control signal to reset the counter, the reset switch of the second integration node can be turned on; the logic module is: Each gate control switch is sorted. When the count value output by the output terminal of the detection counter is added L, the next gate control switch is selected to be turned on in sequence. If there is no next gate control switch, it will return to the first gate. The control switch is cyclically turned on. When the count value output by the output terminal of the counter is mN or the reset input terminal receives a reset control signal that resets the counter, the logic module directly returns to the first gating control switch for cyclic conduction. , where L is a positive integer greater than or equal to 1, and m is a positive integer greater than or equal to 1.

Example

The first pulse frequency modulation type image sensor circuit in the embodiment of the present invention is shown in FIG. 5 for a schematic structural diagram, including a power input terminal VCC, a photodetector Det1, an integrating node capacitor Cint, a comparator, and a first integrating node reset switch S0 , counter, circuit output terminal, ground wire, external control signal input terminal, a group of gate control switches (including the first gate control switch Sc1, the second gate control switch Sc2, ..., the Nth gate control switch ScN ), a logic module and a set of fixed reference voltage input terminals, the positive pole of the photodetector Det1 is connected to the ground wire, its negative pole is connected to the power input terminal VCC through the first integration node reset switch S0, and one end of the integration node capacitor Cint is connected to the ground wire The other end is connected to the negative pole of the photodetector Det1; among a set of gating control switches and a set of fixed reference voltage terminals, each gating control switch corresponds to each fixed reference voltage input terminal one-to-one, and the negative phase input of the comparator The terminal is connected to the negative pole of the photodetector Det1, its positive phase input terminal is respectively connected to the corresponding fixed reference voltage input terminal through each gating control switch, and the output terminal of the comparator is connected to the counting input terminal of the counter; the reset terminal of the counter It is connected with the input end of the external control signal, the reset control end of the integration node is connected with the control end of the reset switch S0 of the first integration node, the output end is used as the output end of the circuit, and is connected with the input end of the logic module. One-to-one correspondence with each gating control switch, and each output terminal is respectively connected with the control terminal of the corresponding gating control switch; here, in a group of fixed reference voltage terminals, the fixed reference voltage input by each fixed reference voltage terminal is the same as that of other fixed reference voltage terminals. The fixed reference voltages of the fixed reference voltage input are different, that is, the first fixed reference voltage Vc1, the second fixed reference voltage Vc2, ... and the Nth fixed reference voltage VcN are respectively different; The reset control terminal of the integration node triggers a pulse to turn on the reset switch S0 of the first integration node, where N is a positive integer greater than or equal to 2; each gating control switch is controlled by the logic module, and there is only one selection at the same time. The ON control switch is turned on, and the rest are turned off; when the external control signal input terminal inputs the reset control signal Reset to reset the counter, the reset control terminal of the integration node of the counter triggers a pulse to turn on the reset switch S0 of the first integration node, and at the same time the counter The output terminal outputs the initial reset signal; the logic module sorts the gating control switches. When the count value output by the output terminal of the detection counter adds L, the next gating control switch is sequentially selected to be turned on. If there is no next gating control switch control switch, then go back to the first gating control switch for cyclic conduction, when the count value output by the output terminal of the counter is mN or the initial reset signal, the logic module directly returns to the first gating control switch to cycle On, where L is a positive integer greater than or equal to 1, and m is a positive integer greater than or equal to 1.

The second pulse frequency modulation type image sensor circuit in the embodiment of the present invention is shown in FIG. 6 for a schematic structural diagram, including a power input terminal VCC, a photodetector Det1, an integrating node capacitor Cint, a comparator, and a first integrating node reset switch S0 , counter, circuit output terminal, ground wire, external control signal input terminal, a group of gate control switches (including the first gate control switch Sc1, the second gate control switch Sc2, ..., the Nth gate control switch ScN ), a logic module and a set of fixed reference voltage input terminals (including a first fixed reference voltage Vc1, a second fixed reference voltage Vc2, ..., the Nth fixed reference voltage VcN), the positive electrode of the photodetector Det1 is connected to the ground wire, Its negative pole is connected to the power input terminal VCC through the first integration node reset switch S0, one end of the integration node capacitor Cint is connected to the ground wire, and the other end is connected to the negative pole of the photodetector Det1; a set of gating control switches and a set of fixed reference In the voltage terminal, each gating control switch corresponds to each fixed reference voltage input terminal one-to-one, the negative phase input terminal of the comparator is connected to the negative pole of the photodetector Det1, and its positive phase input terminal is connected to each gating control switch through each gating control switch respectively. The corresponding fixed reference voltage input terminal is connected, and the output terminal of the comparator is connected to the counting input terminal of the counter; the reset terminal of the counter is connected to the input terminal of the external control signal, and the reset control terminal of the integration node is controlled by the reset switch S0 of the first integration node. The output terminal is used as the circuit output terminal, and is connected with the input terminal of the logic module. Each output terminal of the logic module is in one-to-one correspondence with each gating control switch, and each output terminal is respectively connected with the control terminal of the corresponding gating control switch. connection, the external control signal input terminal is connected to the reset input terminal of the logic module; here, in a group of fixed reference voltage terminals, the fixed reference voltage input by each fixed reference voltage terminal is different from the fixed reference voltage input by other fixed reference voltage terminals; In the counter, each time N pulses are input to the counting input terminal, the reset control terminal of the integration node triggers a pulse to turn on the reset switch S0 of the first integration node, where N is a positive integer greater than or equal to 2; The switch is controlled by the logic module, only one gating control switch is turned on at the same time, and the rest are turned off; when the external control signal input terminal inputs the reset control signal Reset to reset the counter, the reset control terminal of the integral node of the counter triggers a pulse, The first integration node reset switch S0 is turned on; the logic module sorts the gate control switches, and when the count value output by the output end of the detection counter adds L, the next gate control switch is sequentially selected to be turned on. A gating control switch will return to the first gating control switch for cyclic conduction. When the count value output by the output terminal of the counter is mN or the reset input terminal receives the reset control signal Reset that resets the counter, the logic The module directly returns to the first gating control switch for cyclic conduction, where L is a positive integer greater than or equal to 1, and m is a positive integer greater than or equal to 1.

The third pulse frequency modulation type image sensor circuit in the embodiment of the present invention is shown in FIG. 7 for a schematic structural diagram, including a power input terminal VCC, a photodetector Det1, an integrating node capacitor Cint, a comparator, and a first integrating node reset switch S0 , counter, circuit output terminal, ground wire, external control signal input terminal, second integration node reset switch Sr, a group of gate control switches (including the first gate control switch Sc1, the second gate control switch Sc2, ... , Nth gate control switch ScN), logic module and a set of fixed reference voltage input terminals (including the first fixed reference voltage Vc1, the second fixed reference voltage Vc2, ..., the Nth fixed reference voltage VcN), photodetector The positive pole of Det1 is connected to the ground wire, and its negative pole is connected to the power input terminal VCC through the first integration node reset switch S0 and the second integration node reset switch Sr respectively, one end of the integration node capacitor Cint is connected to the ground wire, and the other end is connected to the photodetector In the group of gating control switches and a group of fixed reference voltage terminals, each gating control switch corresponds to each fixed reference voltage input terminal one-to-one, and the negative phase input terminal of the comparator is connected to the photodetector The negative pole of Det1 is connected, its non-inverting input terminal is connected to the corresponding fixed reference voltage input terminal through each gating control switch respectively, the output terminal of the comparator is connected to the counting input terminal of the counter; the reset terminal of the counter is connected to the external control signal input The reset control terminal of the integration node is connected to the control terminal of the first integration node reset switch S0, and its output terminal is used as the circuit output terminal and is connected to the input terminal of the logic module. The control terminal of the second integration node reset switch Sr The terminal is connected with the input terminal of the external control signal, each output terminal of the logic module is in one-to-one correspondence with each gating control switch, and each output terminal is respectively connected with the control terminal of the corresponding gating control switch; here, in a set of fixed reference voltage terminals , the fixed reference voltage input by each fixed reference voltage terminal is different from the fixed reference voltage input by other fixed reference voltage terminals; in the counter, every N pulses are input to the counting input terminal of the counter, the reset control terminal of the integration node will trigger a pulse, so that The first integration node reset switch S0 is turned on; each gate control switch is controlled by the logic module, only one gate control switch is turned on at the same time, and the rest are turned off; when the external control signal input terminal inputs the reset control signal Reset to make the counter When reset, the second integration node reset switch Sr can be turned on, and the output terminal of the counter outputs an initial reset signal; the logic module sorts the gate control switches, when the count value output by the output terminal of the detection counter adds L, Select the next gating control switch to be turned on in sequence. If there is no next gating control switch, it will return to the first gating control switch for cyclic conduction. When the count value output by the output terminal of the counter is mN or the initial reset signal When , the logic module directly returns to the first gating control switch for cyclic conduction, where L is a positive integer greater than or equal to 1, and m is a positive integer greater than or equal to 1.

The fourth pulse frequency modulation type image sensor circuit in the embodiment of the present invention is shown in FIG. 8 for a schematic structural diagram, including a power input terminal VCC, a photodetector Det1, an integrating node capacitor Cint, a comparator, and a first integrating node reset switch S0 , counter, circuit output terminal, ground wire, external control signal input terminal, second integration node reset switch Sr, a group of gate control switches (including the first gate control switch Sc1, the second gate control switch Sc2, ... , Nth gate control switch ScN), logic module and a set of fixed reference voltage input terminals (including the first fixed reference voltage Vc1, the second fixed reference voltage Vc2, ..., the Nth fixed reference voltage VcN), photodetector The positive pole of Det1 is connected to the ground wire, and its negative pole is connected to the power input terminal VCC through the first integration node reset switch S0 and the second integration node reset switch Sr respectively, one end of the integration node capacitor Cint is connected to the ground wire, and the other end is connected to the photodetector The negative pole of the comparator Det1 is connected; in a set of gating control switches and a set of fixed reference voltage terminals, each gating control switch is in one-to-one correspondence with each fixed reference voltage input terminal, and the negative phase input terminal of the comparator is connected to the photodetector Det1. The negative pole is connected, and its non-inverting input terminal is connected to the corresponding fixed reference voltage input terminal through each gating control switch respectively. The output terminal of the comparator is connected to the counting input terminal of the counter; the reset terminal of the counter is connected to the external control signal input terminal. , its integration node reset control terminal is connected to the control terminal of the first integration node reset switch S0, its output terminal is used as a circuit output terminal, and is connected to the input terminal of the logic module, and the control terminal of the second integration node reset switch Sr is connected to The external control signal input terminal is connected, each output terminal of the logic module is in one-to-one correspondence with each gating control switch, each output terminal is respectively connected with the control terminal of the corresponding gating control switch, and the external control signal input terminal is connected with the reset input of the logic module. terminal connection; here, in a set of fixed reference voltage terminals, the fixed reference voltage input by each fixed reference voltage terminal is different from the fixed reference voltage input by other fixed reference voltage terminals; in the counter, the counting input terminal of each input N pulses, The reset control terminal of the integration node triggers a pulse to turn on the reset switch S0 of the first integration node; each gating control switch is controlled by the logic module, only one gating control switch is turned on at the same time, and the rest are turned off; When the reset control signal Reset is input to the external control signal input terminal to reset the counter, the reset switch Sr of the second integration node can be turned on; the logic module sorts the gate control switches, when the count value output by the output terminal of the detection counter is added L When there is no next strobe control switch, it will return to the first strobe control switch for cyclic conduction. When the count value output by the output terminal of the counter is mN or reset When the input terminal receives the reset control signal Reset that resets the counter, it directly returns to the first gate control switch for cyclic conduction, where L is a positive integer greater than or equal to 1, and m is a positive integer greater than or equal to 1 number

In the above four pulse frequency modulation type image sensor circuits, the comparators can be two-stage comparators or OTA-based symmetric comparators or dynamic latch comparators or controllable Schmitt triggers, etc.; and the first integral The node reset switch S0 and/or the second integration node reset switch Sr may be a PMOS switch, an NMOS switch, a CMOS switch, a bootstrap switch, or the like.

The value of the fixed reference voltage input by each fixed reference voltage terminal is between the reset voltage of the integration node and the lowest input voltage of the non-inverting input terminal of the comparator. The amount of change increases or decreases sequentially.

In a set of fixed reference voltage terminals, the number of fixed reference voltage terminals is preferably greater than or equal to N, and it is optimal to be equal to N.

According to the above four pulse frequency modulation type image sensor circuits, it can be seen that the difference lies in whether there is a second integration node reset switch Sr and whether the reset input terminal of the logic module is connected to the external control signal input terminal, when there is a second integration node reset switch Sr When Sr is used, the reset control signal Reset can be directly reacted to the integration node capacitor Cint, so that the system responds faster, without waiting for the reset control terminal of the counter integration node to trigger the pulse, and when the reset input terminal of the logic module and the external control signal input terminal When connected, it can make the reset control signal Reset directly react to the logic module, and it can also make the system react faster, and it is not necessary for the counter to output the initial reset signal during reset.

In addition, in the logic module and the counter, it can also have various connection methods to realize the judgment when the count value of the counter output is mN. The integration node reset control terminal is connected, or a second reset input terminal is directly set on the logic module, and it is connected to the integration node reset control terminal of the counter. In this way, the counter can be used to pass the integration node when its output count value is mN To reset the logic module by resetting the pulse output from the control terminal, the logic module does not need to judge the output count value of the counter. Of course, the logic module can also directly detect and judge the output count value of the counter.

It can be seen that the above four pulse frequency modulation type image sensor circuits are essentially the same, and the only difference lies in the response speed to the reset control signal Reset input from the external control signal input terminal.

When in use, connect the output end of the counter to the output bus, and the specific processing steps are as follows:

Step 1. Input the reset control signal Reset to the input terminal of the external control signal, the integrating node capacitor Cint is reset to the reset level, the counter is reset according to the input reset control signal Reset, the logic module is reset, and the first gating control switch is controlled to be turned on , the rest are closed;

Step 2. The input reset control signal Reset disconnects the integrating node capacitor Cint from the power input terminal VCC, and starts counting;

Step 3. Under the action of the photodetector Det1, the voltage on the integrating node capacitor Cint changes. When the voltage is equal to the currently turned on fixed reference voltage, the output voltage of the comparator is reversed, and the process goes to step 4;

Step 4. Add L to the output count value of the counter, the logic module controls the current gating control switch to turn off, and turns on the next gating control switch at the same time, and returns to step 3;

Step 5. When the count value of the counter is mN, the reset control terminal of the integration node of the counter outputs a pulse to turn on the reset switch S0 of the first integration node, reset the capacitor Cint of the integration node, and reset the logic module to control the first integration node. One gating control switch is turned on, the rest are turned off, and the process returns to step 3.

In this example, the third pulse frequency modulation type image sensor circuit is taken as an example, and the value of N is limited to 3, L is 1, all control switches (gating control switch, first integration node reset switch S0 and second integration The node reset switches (Sr) are all PMOS switches, the counter is a 3-bit counter, and a group of gate control switches includes a first gate control switch Sc1, a second gate control switch Sc2 and a third gate control switch Sc3, with which The corresponding fixed reference voltages are the first fixed reference voltage Vc1 , the second fixed reference voltage Vc2 and the third fixed reference voltage Vc3 respectively, and a schematic diagram of the structure is shown in FIG. 9 .

Referring to FIG. 10, it is the working sequence and output result diagram of the pulse frequency modulation type image sensor circuit in the above-mentioned FIG. 9, wherein Vs0 refers to the voltage on the control terminal of the reset switch S0 of the first integration node, 1 represents step A, and 2 represents step A Steps B and 3 represent step C. Here, to explain, the output of the 3-bit counter generally includes three output lines. In Figure 10, the signals output by the three output lines are marked with OUT0, OUT1 and OUT2, respectively. The specific processing steps as follows:

Step A (corresponding to Step 1): external reset. At this stage, the reset control signal Reset is at a low level, the integration node capacitor Cint is reset to a high level through the second integration node reset switch Sr, and the counter completes the initial reset process of the counter under the action of the reset control signal Reset. According to the initial reset signal of the counter, the logic module outputs a corresponding control signal to turn on the first gating control switch Sc1, and turn off the remaining gating control switches Sc2-ScN.

Step B (corresponding to steps 2 to 4): counting and quantification. At this stage, the reset control signal Reset is at a high level. Under the action of the photodetector Det1, the stored charges on the integrating node capacitor Cint are discharged by the photodetector Det1 at a certain speed. When the voltage value Vcint on the integration node capacitor Cint is slightly lower than the reference voltage value Vvref at this time, the output voltage of the comparator is reversed, the count value of the counter is increased by one, and then the logic control module adjusts the next gate switch to be turned on. Go to the next count.

Step C (corresponding to Step 5): Internal reset. When the count value of the counter increases by N each time, the integration node reset control terminal of the counter outputs a low-level pulse signal to turn on the first integration node reset switch S0 to reset the integration node capacitor Cint. At this time, the logic module learns that the count value of the current counter is mN, and turns on the first gating control switch Sc1, and then enters the next cycle of counting quantization and internal reset.

Claims (9)

1. A pulse frequency modulation type image sensor circuit, including a power input end, a photodetector, an integrating node capacitor, a comparator, a first integrating node reset switch, a counter, a circuit output end and a ground wire, and it is characterized in that it also includes an external control A signal input terminal, a set of gating control switches, a logic module and a set of fixed reference voltage input terminals, the anode of the photodetector is connected to the ground wire, and the cathode of the photodetector is connected to the power input terminal through the reset switch of the first integration node, and the integration One end of the node capacitor is connected to the ground wire, and the other end is connected to the negative electrode of the photodetector; among the set of gating control switches and a set of fixed reference voltage terminals, each gating control switch and each fixed reference voltage input terminal one by one Correspondingly, the negative phase input terminal of the comparator is connected to the negative pole of the photodetector, its positive phase input terminal is respectively connected to the corresponding fixed reference voltage input terminal through each gating control switch, and the output terminal of the comparator is connected to the counting input of the counter. The reset terminal of the counter is connected to the input terminal of the external control signal, the reset control terminal of the integration node is connected to the control terminal of the reset switch of the first integration node, and the output terminal is used as the output terminal of the circuit, and is connected with the input terminal of the logic module. connection, each output end of the logic module is in one-to-one correspondence with each gating control switch, and each output end is respectively connected with the control end of the corresponding gating control switch; In the set of fixed reference voltage terminals, the fixed reference voltage input by each fixed reference voltage terminal is different from the fixed reference voltage input by other fixed reference voltage terminals; In the counter, every time N pulses are input to the counting input terminal, the reset control terminal of the integration node triggers a pulse to turn on the reset switch of the first integration node, wherein N is a positive integer greater than or equal to 2; Each of the gating control switches is controlled by the logic module, and only one gating control switch is turned on at the same time, and the rest are turned off; When the reset control signal is input to the external control signal input terminal to reset the counter, the reset control terminal of the integration node of the counter triggers a pulse to turn on the reset switch of the first integration node, and at the same time, the output terminal of the counter outputs the initial reset signal; The logic module sorts each gating control switch, and when the count value output by the output end of the detection counter adds L, the next gating control switch is selected to be turned on in sequence, and if there is no next gating control switch, it returns to The first gating control switch is cyclically turned on. When the count value output by the output terminal of the counter is mN or the initial reset signal, the logic module directly returns to the first gating control switch for cyclic conduction, where L is a positive integer greater than or equal to 1, and m is a positive integer greater than or equal to 1. 2. The pulse frequency modulation type image sensor circuit according to claim 1, wherein the comparator is a two-stage comparator or an OTA-based symmetric comparator or a dynamic latch comparator or a controllable Schmitt comparator trigger; The first integration node reset switch is a PMOS switch or an NMOS switch or a CMOS switch or a bootstrap switch; The values of the fixed reference voltages input by the fixed reference voltage terminals are all between the reset voltage of the integration node and the lowest input voltage of the non-inverting input terminal of the comparator. The fixed amount of change increases or decreases sequentially; In the set of fixed reference voltage terminals, the number of fixed reference voltage terminals is greater than or equal to N. 3. A pulse frequency modulation type image sensor circuit, including a power input end, a photodetector, an integrating node capacitor, a comparator, a first integrating node reset switch, a counter, a circuit output end and a ground wire, and it is characterized in that it also includes an external control A signal input terminal, a set of gating control switches, a logic module and a set of fixed reference voltage input terminals, the anode of the photodetector is connected to the ground wire, and the cathode of the photodetector is connected to the power input terminal through the reset switch of the first integration node, and the integration One end of the node capacitor is connected to the ground wire, and the other end is connected to the negative electrode of the photodetector; among the set of gating control switches and a set of fixed reference voltage terminals, each gating control switch and each fixed reference voltage input terminal one by one Correspondingly, the negative phase input terminal of the comparator is connected to the negative pole of the photodetector, its positive phase input terminal is respectively connected to the corresponding fixed reference voltage input terminal through each gating control switch, and the output terminal of the comparator is connected to the counting input of the counter. The reset terminal of the counter is connected to the input terminal of the external control signal, the reset control terminal of the integration node is connected to the control terminal of the reset switch of the first integration node, and the output terminal is used as the output terminal of the circuit, and is connected with the input terminal of the logic module. connection, each output end of the logic module is in one-to-one correspondence with each gating control switch, each output end is respectively connected with the control end of the corresponding gating control switch, and the external control signal input end is connected with the reset input end of the logic module; In the set of fixed reference voltage terminals, the fixed reference voltage input by each fixed reference voltage terminal is different from the fixed reference voltage input by other fixed reference voltage terminals; In the counter, every time N pulses are input to the counting input terminal, the reset control terminal of the integration node triggers a pulse to turn on the reset switch of the first integration node, wherein N is a positive integer greater than or equal to 2; Each of the gating control switches is controlled by the logic module, and only one gating control switch is turned on at the same time, and the rest are turned off; When the reset control signal is input to the external control signal input terminal to reset the counter, the reset control terminal of the integration node of the counter triggers a pulse to turn on the reset switch of the first integration node; The logic module sorts each gating control switch, and when the count value output by the output end of the detection counter adds L, the next gating control switch is selected to be turned on in sequence, and if there is no next gating control switch, it returns to The first gating control switch is cyclically turned on. When the count value output by the output terminal of the counter is mN or the reset input terminal receives the reset control signal to reset the counter, the logic module directly returns to the first gating control The switch is cyclically turned on, wherein L is a positive integer greater than or equal to 1, and m is a positive integer greater than or equal to 1. 4. The pulse frequency modulation type image sensor circuit according to claim 3, wherein the comparator is a two-stage comparator or an OTA-based symmetric comparator or a dynamic latch comparator or a controllable Schmitt comparator trigger; The first integration node reset switch is a PMOS switch or an NMOS switch or a CMOS switch or a bootstrap switch; The values of the fixed reference voltages input by the fixed reference voltage terminals are all between the reset voltage of the integration node and the lowest input voltage of the non-inverting input terminal of the comparator. The fixed amount of change increases or decreases sequentially; In the set of fixed reference voltage terminals, the number of fixed reference voltage terminals is greater than or equal to N. 5. A pulse frequency modulation type image sensor circuit, including a power input terminal, a photodetector, an integrating node capacitor, a comparator, a first integrating node reset switch, a counter, a circuit output terminal and a ground wire, and it is characterized in that it also includes an external control a signal input terminal, a second integration node reset switch, a set of gating control switches, a logic module and a set of fixed reference voltage input terminals, the positive pole of the photodetector is connected to the ground wire, and its negative pole is reset through the first integration node respectively The switch and the second integrating node reset switch are connected to the power input terminal, one end of the integrating node capacitor is connected to the ground wire, and the other end is connected to the negative electrode of the photodetector; among the set of gating control switches and a set of fixed reference voltage terminals , each gating control switch is in one-to-one correspondence with each fixed reference voltage input terminal, the negative phase input terminal of the comparator is connected to the negative pole of the photodetector, and its positive phase input terminal is connected to the corresponding fixed reference voltage through each gating control switch respectively The voltage input end is connected, the output end of the comparator is connected with the counting input end of the counter; the reset end of the counter is connected with the input end of the external control signal, and the reset control end of the integration node is connected with the control end of the reset switch of the first integration node, Its output end is used as the circuit output end, and is connected with the input end of the logic module, the control end of the second integration node reset switch is connected with the input end of the external control signal, and each output end of the logic module is connected with each gating control switch one by one. Correspondingly, each output terminal is respectively connected with the control terminal of the corresponding gating control switch; In the set of fixed reference voltage terminals, the fixed reference voltage input by each fixed reference voltage terminal is different from the fixed reference voltage input by other fixed reference voltage terminals; In the counter, every time N pulses are input to the counting input terminal, the reset control terminal of the integration node triggers a pulse to turn on the reset switch of the first integration node; Each of the gating control switches is controlled by the logic module, and only one gating control switch is turned on at the same time, and the rest are turned off; When the reset control signal is input to the external control signal input terminal to reset the counter, the reset switch of the second integration node can be turned on, and the output terminal of the counter outputs the initial reset signal; The logic module sorts each gating control switch, and when the count value output by the output end of the detection counter adds L, the next gating control switch is selected to be turned on in sequence, and if there is no next gating control switch, it returns to The first gating control switch is cyclically turned on. When the count value output by the output terminal of the counter is mN or the initial reset signal, the logic module directly returns to the first gating control switch for cyclic conduction, where L is a positive integer greater than or equal to 1, and m is a positive integer greater than or equal to 1. 6 . The pulse frequency modulation type image sensor circuit according to claim 5 , wherein the comparator is a two-stage comparator or an OTA-based symmetric comparator or a dynamic latch comparator or a controllable Schmitt comparator. 7 . trigger; The first integration node reset switch and/or the second integration node reset switch is a PMOS switch or an NMOS switch or a CMOS switch or a bootstrap switch; The values of the fixed reference voltages input by the fixed reference voltage terminals are all between the reset voltage of the integration node and the lowest input voltage of the non-inverting input terminal of the comparator. The fixed amount of change increases or decreases sequentially; In the set of fixed reference voltage terminals, the number of fixed reference voltage terminals is greater than or equal to N. 7. A pulse frequency modulation type image sensor circuit, including a power input terminal, a photodetector, an integrating node capacitor, a comparator, a first integrating node reset switch, a counter, a circuit output end and a ground wire, and it is characterized in that it also includes an external control a signal input terminal, a second integration node reset switch, a set of gating control switches, a logic module and a set of fixed reference voltage input terminals, the positive pole of the photodetector is connected to the ground wire, and its negative pole is reset through the first integration node respectively The switch and the second integrating node reset switch are connected to the power input terminal, one end of the integrating node capacitor is connected to the ground wire, and the other end is connected to the negative electrode of the photodetector; among the set of gating control switches and a set of fixed reference voltage terminals , each gating control switch is in one-to-one correspondence with each fixed reference voltage input terminal, the negative phase input terminal of the comparator is connected to the negative pole of the photodetector, and its positive phase input terminal is connected to the corresponding fixed reference voltage through each gating control switch respectively The voltage input end is connected, the output end of the comparator is connected with the counting input end of the counter; the reset end of the counter is connected with the input end of the external control signal, and the reset control end of the integration node is connected with the control end of the reset switch of the first integration node, Its output end is used as the circuit output end, and is connected with the input end of the logic module, the control end of the second integration node reset switch is connected with the input end of the external control signal, and each output end of the logic module is connected with each gating control switch one by one. Correspondingly, each output terminal is respectively connected with the control terminal of the corresponding gating control switch, and the external control signal input terminal is connected with the reset input terminal of the logic module; In the set of fixed reference voltage terminals, the fixed reference voltage input by each fixed reference voltage terminal is different from the fixed reference voltage input by other fixed reference voltage terminals; In the counter, every time N pulses are input to the counting input terminal, the reset control terminal of the integration node triggers a pulse to turn on the reset switch of the first integration node; Each of the gating control switches is controlled by the logic module, and only one gating control switch is turned on at the same time, and the rest are turned off; When the reset control signal is input to the external control signal input terminal to reset the counter, the reset switch of the second integration node can be turned on; The logic module sorts each gating control switch, and when the count value output by the output end of the detection counter adds L, the next gating control switch is selected to be turned on in sequence, and if there is no next gating control switch, it returns to The first gating control switch is cyclically turned on. When the count value output by the output terminal of the counter is mN or the reset input terminal receives the reset control signal to reset the counter, the logic module directly returns to the first gating control The switch is cyclically turned on, wherein L is a positive integer greater than or equal to 1, and m is a positive integer greater than or equal to 1. 8. The pulse frequency modulated image sensor circuit according to claim 7, wherein the comparator is a two-stage comparator or an OTA-based symmetric comparator or a dynamic latch comparator or a controllable Schmitt comparator trigger; The first integration node reset switch and/or the second integration node reset switch is a PMOS switch or an NMOS switch or a CMOS switch or a bootstrap switch; The values of the fixed reference voltages input by the fixed reference voltage terminals are all between the reset voltage of the integration node and the lowest input voltage of the non-inverting input terminal of the comparator. The fixed amount of change increases or decreases sequentially; In the set of fixed reference voltage terminals, the number of fixed reference voltage terminals is greater than or equal to N. 9. A processing method for a pulse frequency modulation type image sensor circuit, applied to the pulse frequency modulation type image sensor circuit according to claim 1 or 2 or 3 or 4 or 5 or 6 or 7 or 8, characterized in that it comprises the following step: Step 1. Input the reset control signal to the input terminal of the external control signal, reset the capacitor of the integration node to the reset level, reset the counter according to the input reset control signal, reset the logic module, control the first gating control switch to be turned on, and the rest are turned off ; Step 2. The input reset control signal disconnects the integrating node capacitor from the power input terminal and starts counting; Step 3. Under the action of the photodetector, the voltage on the capacitor of the integrating node changes. When the voltage is equal to the current conduction fixed reference voltage, the output voltage of the comparator is reversed, and the process goes to step 4; Step 4. Add L to the output count value of the counter, the logic module controls the current gating control switch to turn off, and turns on the next gating control switch at the same time, and returns to step 3; Step 5. When the count value of the counter is mN, the reset control terminal of the integration node of the counter outputs a pulse to turn on the reset switch of the first integration node, reset the capacitance of the integration node, and reset the logic module to control the first selection. The pass control switch is turned on, the rest are turned off, and go back to step 3.

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