CN107329119B - Radar waveform generation module and radar waveform generation method thereof - Google Patents
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01S—RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES
- G01S7/00—Details of systems according to groups G01S13/00, G01S15/00, G01S17/00
- G01S7/02—Details of systems according to groups G01S13/00, G01S15/00, G01S17/00 of systems according to group G01S13/00
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01S—RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES
- G01S7/00—Details of systems according to groups G01S13/00, G01S15/00, G01S17/00
- G01S7/02—Details of systems according to groups G01S13/00, G01S15/00, G01S17/00 of systems according to group G01S13/00
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Abstract
The invention belongs to the technical field of radars, and particularly relates to a radar waveform generation module and a radar waveform generation method thereof. The invention comprises a signal input/output module, an FPGA control module, a DDS waveform generation module, a balun conversion module, an amplifying and filtering module, a storage module and a programming port, wherein the signal input/output module is used for receiving and driving frequency parameters and waveform trigger signals, the frequency parameters and the waveform trigger signals after driving are sent to the input end of the FPGA control module, the radar waveform generation method of the radar waveform generation module can generate a linear frequency modulation signal and a nonlinear frequency modulation signal for normal radar operation, and can generate two test signals for radar self-detection, namely the linear frequency modulation signal and the nonlinear frequency modulation signal, and each type of frequency modulation signal can generate long and short pulse combined frequency modulation signals in one period.
Description
Technical Field
The invention belongs to the technical field of radars, and particularly relates to a radar waveform generation module and a radar waveform generation method thereof.
Background
Along with the development of radar technology, in order to improve the detection performance of radar, pulse compression technology is applied more and more widely, and pulse waveform signals with various forms and certain widths are required to be generated, and meanwhile, in order to improve the working reliability of the radar, radar self-checking signals are required to be generated to realize the real-time state detection of the radar.
The conventional radar waveform generation module generally generates a waveform with a low carrier frequency, a single waveform generation form, a complex structure and high price.
Disclosure of Invention
In order to overcome the defects in the prior art, the invention provides a radar waveform generation module which can generate a linear frequency modulation signal and a non-linear frequency modulation signal for normal working of a radar and can generate the linear frequency modulation signal and the non-linear frequency modulation signal during self-checking of the radar.
In order to achieve the above object, the present invention adopts the following technical measures:
the radar waveform generation module comprises a signal input/output module, an FPGA control module, a DDS waveform generation module, a balun conversion module, an amplifying and filtering module, a storage module and a programming port,
the signal input/output module is used for receiving and driving the frequency parameters and the waveform trigger signals, sending the driven frequency parameters and waveform trigger signals to the input end of the FPGA control module, receiving the door pocket signals from the FPGA control module, and driving and outputting the door pocket signals;
the output end of the FPGA control module is connected with the input end of the DDS waveform generation module;
the DDS waveform generation module is used for outputting the modulated differential signals to the input end of the balun conversion module, and the clock input end of the DDS waveform generation module is connected with an external clock signal;
the balun conversion module is used for converting the modulated differential signals into analog single-output signals, and the output end of the balun conversion module is connected with the input end of the amplifying and filtering module;
the storage module is used for storing the control program of the FPGA control module and loading the control program into the FPGA control module when the power is on;
and the programming port is used for reading the control program of the FPGA control module and writing the control program into the storage module.
Preferably, the signal input/output module comprises a first bi-directional sixteen-bit transceiver and a second bi-directional sixteen-bit transceiver, wherein,
the first bidirectional sixteen-bit transceiver is used for receiving and driving the frequency parameters and the waveform trigger signals, and sending the driven frequency parameters and waveform trigger signals to the input end of the FPGA control module;
and the second bidirectional sixteen-bit transceiver is used for receiving the door pocket signal from the FPGA control module, driving the door pocket signal and outputting the door pocket signal.
Preferably, the FPGA control module receives an external clock signal, and comprises a waveform form identification and classification conveying frequency parameter unit, a linear frequency register, a non-linear frequency accumulator, a single carrier frequency memory and a control logic parameter output unit,
the waveform form recognition and classification conveying frequency parameter unit is used for receiving the frequency parameters and waveform trigger signals after the first bidirectional sixteen-bit transceiver is driven, generating frequency control words and respectively sending the frequency control words to the input ends of the linear frequency register, the nonlinear frequency accumulator and the single carrier frequency memory;
the control logic parameter output unit is used for reading the frequency control words stored in the linear frequency register, the nonlinear frequency accumulator and the single carrier frequency memory and sending the frequency control words to the input end of the DDS waveform generation module, and the output end of the control logic parameter output unit is connected with the input end of the second bidirectional sixteen-bit transceiver;
the pins TCK, TMS, TDI and TDO of the programming port are respectively connected with the pins TCK, TMS, TDI and TDO of the FPGA control module; the pins TCK, TMS, TDI and TDO of the memory module are respectively connected with the pins TCK, TMS, TDI and TDO of the FPGA control module.
Preferably, the amplifying and filtering module comprises a first filter, an amplifier and a second filter, wherein the input end of the first filter is connected with the output end of the balun converting module, the output end of the first filter is connected with the input end of the amplifier, the output end of the amplifier is connected with the input end of the second filter, and the output end of the second filter outputs radar waveforms.
Further, the chip types of the first bidirectional sixteen-bit transceiver and the second bidirectional sixteen-bit transceiver are 74FCT163245CPV chips manufactured by IDT company of America.
Further, the chip model of the FPGA control module is an EP20K200EFI484-2X chip manufactured by ALTERA company of America.
Further, the chip model of the DDS waveform generation module is an AD9854ASQ chip manufactured by Analog Devices, inc. of America; the balun conversion module comprises a balun converter, and the chip model of the balun converter is an ADTT1-1 chip manufactured by Mini-Circuits company of America.
Further, the first filter is a low-pass filter, and the second filter is a band-pass filter; the model of the amplifier is ERA-5 monolithic radio frequency amplifier manufactured by Mini-Circuits company of America.
Still further, the memory module includes two EPC2LI20 chips connected in parallel.
The invention also provides a radar waveform generating method of the radar waveform generating module, which comprises the following steps:
s1, the first bidirectional sixteen-bit transceiver receives and drives frequency parameters and waveform trigger signals sent from the outside, and sends the driven frequency parameters into a waveform form recognition and classification conveying frequency parameter unit; the waveform form recognition and classification conveying frequency parameter unit converts the frequency parameters after driving into frequency control words, and sends the frequency control words into a linear frequency register, a non-linear frequency accumulator and a single carrier frequency memory for storage; the first bidirectional sixteen-bit transceiver receives and drives a waveform trigger signal sent from the outside, the driven waveform trigger signal is sent to a waveform form recognition and classification conveying frequency parameter unit, the waveform form recognition and classification conveying frequency parameter unit recognizes the waveform form according to the level of the waveform trigger signal, generates a linear waveform parameter and sends the linear waveform parameter to a linear frequency register for storage, and generates a nonlinear waveform parameter and sends the nonlinear waveform parameter to a nonlinear frequency accumulator for storage;
s2, the control logic parameter output unit respectively reads the linear waveform parameters and the nonlinear waveform parameters in the linear frequency register and the nonlinear frequency accumulator, and the control logic parameter output unit generates a gate sleeve signal and drives and outputs the gate sleeve signal through a second bidirectional sixteen-bit transceiver;
s3, the control logic parameter output unit reads the frequency control words in the linear frequency register, the nonlinear frequency accumulator and the single carrier frequency memory, and sends the frequency control words to the input end of the DDS waveform generation module, and the DDS waveform generation module receives an external clock signal and generates a modulated differential signal;
s4, the DDS waveform generation module outputs a modulated differential signal to the input end of the balun conversion module, the balun conversion module converts the modulated differential signal into an analog single output signal, and the analog single output signal is sent to the input end of the amplifying and filtering module;
s5, the amplification filtering module outputs radar waveforms after amplifying and filtering the analog single-input signals.
The invention has the beneficial effects that:
1) The invention comprises a signal input/output module, an FPGA control module, a DDS waveform generation module, a balun conversion module, an amplifying and filtering module, a storage module and a programming port, wherein the radar waveform generation method of the radar waveform generation module can generate a linear frequency modulation signal and a non-linear frequency modulation signal for normal working of a radar, and can also generate two test signals, namely the linear frequency modulation signal and the non-linear frequency modulation signal, during self-checking of the radar, and each type of frequency modulation signal can generate a long and short pulse combined frequency modulation signal in one period.
2) The waveform and parameters of the radar waveform generation module can be changed timely through program loading according to different use environment requirements, and the radar waveform generation module is easy to maintain and simple to upgrade.
3) The chip model of the FPGA control module is an EP20K200EFI484-2X chip manufactured by ALTERA corporation in America, which is provided with 526000 logic units, 106496-bit RAM and 376I/O ports, the resource is rich, the price is lower, and the design cost of the invention is greatly saved.
Drawings
FIG. 1 is a block diagram of the circuit components of the present invention;
FIG. 2 is a circuit diagram of the parallel use of EPC2LI20 chips according to the present invention;
fig. 3 is an application control timing diagram of an embodiment of the present invention.
The reference numerals in the figures have the following meanings:
10-signal input output module 11-first bidirectional sixteen-bit transceiver
12-second bidirectional sixteen-bit transceiver 20-FPGA control module
21-waveform form identification and classification conveying frequency parameter unit
22-chirp frequency register 23-non-chirp frequency accumulator
24-single carrier frequency memory 25-control logic parameter output unit
30-DDS waveform generation module 40-balun conversion module
50-amplification filter module 51-first filter
52-amplifier 53-second filter
60-memory module 70-programming port
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
As shown in fig. 1, a radar waveform generating module includes a signal input/output module 10, an FPGA control module 20, a DDS waveform generating module 30, a balun converting module 40, an amplifying and filtering module 50, a storage module 60 and a programming port 70, where the signal input/output module 10 is configured to receive and drive frequency parameters and waveform trigger signals, send the driven frequency parameters and waveform trigger signals to an input end of the FPGA control module 20, and the signal input/output module 10 receives a door pocket signal from the FPGA control module 20, and drives and outputs the door pocket signal; the output end of the FPGA control module 20 is connected with the input end of the DDS waveform generation module 30; the clock signal input end of the DDS waveform generation module 30 is connected with an external clock signal of 240 MHz; the DDS waveform generation module 30 receives control parameters sent by the FPGA control module 20 under the control of an external clock signal of 240MHz, the DDS waveform generation module 30 outputs a modulated differential signal to the input end of the balun conversion module 40, the balun conversion module 40 is used for converting the modulated differential signal into an analog single output signal, and the output end of the balun conversion module 40 is connected with the input end of the amplifying and filtering module 50; the storage module 60 is used for storing a control program of the FPGA control module 20, and loading the control program into the FPGA control module 20 when power is on; the programming port 70 is used to read the control program of the FPGA control module 20 and write the control program to the memory module 60.
The programming port 70 is a JTAG programming port, and is a dual in-line pin, which can read and write programs to the FPGA control module 20 and write programs to the memory module 60.
The signal input/output module 10 includes a first bidirectional sixteen-bit transceiver 11 and a second bidirectional sixteen-bit transceiver 12, where the first bidirectional sixteen-bit transceiver 11 is configured to receive and drive a frequency parameter and a waveform trigger signal, and send the driven frequency parameter and waveform trigger signal to an input end of the FPGA control module 20; the second bidirectional sixteen-bit transceiver 12 is configured to receive a door pocket signal from the FPGA control module 20, drive the door pocket signal, and output the door pocket signal, where the door pocket signal is composed of a set of square wave pulse signals, and is used as a control signal of the transmit switch.
The FPGA control module 20 is a control core of the radar waveform generation module, the FPGA control module 20 receives an external clock signal of 80MHz, the FPGA control module 20 classifies the interior of the radar waveform generation module into a waveform form identification and classification conveying frequency parameter unit 21, a chirp frequency register 22, a non-chirp frequency accumulator 23, a single carrier frequency memory 24 and a control logic parameter output unit 25 according to the written program, the waveform form identification and classification conveying frequency parameter unit 21 is used for receiving the frequency parameters and waveform trigger signals after the first bi-directional sixteen-bit transceiver 11 is driven, frequency control words are generated and sent to the input ends of the chirp frequency register 22, the non-chirp frequency accumulator 23 and the single carrier frequency memory 24 respectively, and the output end of the waveform form identification and classification conveying frequency parameter unit 21 is connected with the input end of the second bi-directional sixteen-bit transceiver 12; the control logic parameter output unit 25 is configured to read the frequency control words stored in the chirped frequency register 22, the non-chirped frequency accumulator 23, and the single carrier frequency memory 24, and send the frequency control words to the input end of the DDS waveform generation module 30, where the output end of the control logic parameter output unit 25 is connected to the input end of the second bidirectional sixteen-bit transceiver 12; the pins TCK, TMS, TDI, TDO of the programming port 70 are respectively connected with the pins TCK, TMS, TDI, TDO of the FPGA control module 20; pin TCK, pin TMS, pin TDI, pin TDO of memory module 60 are connected to pin TCK, pin TMS, pin TDI, pin TDO, respectively, of FPGA control module 20.
The amplifying and filtering module 50 comprises a first filter 51, an amplifier 52 and a second filter 53, wherein the input end of the first filter 51 is connected with the output end of the balun converting module 40, the output end of the first filter 51 is connected with the input end of the amplifier 52, the output end of the amplifier 52 is connected with the input end of the second filter 53, and the output end of the second filter 53 outputs radar waveforms.
Specifically, the first filter 51 is a low-pass filter, and is configured to filter out the high-frequency signal output by the DDS waveform generating module 30; the second filter 53 is a band-pass filter for filtering harmonic signals output from the amplifier 52.
The chip types of the first bidirectional sixteen-bit transceiver 11 and the second bidirectional sixteen-bit transceiver 12 are 74FCT163245CPV chips manufactured by IDT company of America; the chip model of the FPGA control module 20 is an EP20K200EFI484-2X chip manufactured by ALTERA corporation of America. The device has 526000 logic units, 106496-bit RAM, 376I/O ports, low resource enrichment price and high cost performance.
The chip model of the DDS waveform generation module 30 is an AD9854ASQ chip manufactured by Analog Devices of America, the chip model is provided with a 300MHz internal clock, the frequency of an output signal is allowed to be 150MHz, the digital frequency modulation output frequency can reach 100MHz, the DDS core has 48-bit frequency resolution, and output 17-bit phase truncation ensures a good spurious-free dynamic range and 8-bit programmable parallel port control. In the invention, a 240MHz clock signal is externally provided, and a pulse modulation signal with carrier frequency of 10MHz is output by the DDS waveform generation module 30.
The balun conversion module 40 comprises a balun converter, wherein the chip model of the balun converter is an ADTT1-1 chip manufactured by Mini-Circuits corporation of America, and the balun converter is used for converting differential signals output by an AD9854ASQ chip into analog single output signals.
The amplifier 52 is an ERA-5 monolithic radio frequency amplifier manufactured by Mini-Circuits, inc. In the united states of america, and is used to amplify the generated radar waveform to a desired amplitude.
As shown in fig. 2, the storage module 60 includes two EPC2LI20 chips connected in parallel, and is configured to store a control program of the FPGA control module 20, and load the control program into the FPGA control module 20 when the power is on; two or more EPC2LI20 may be used in parallel due to insufficient memory space of one EPC2LI20 chip.
The invention also provides a radar waveform generating method of the radar waveform generating module, which comprises the following steps:
the frequency parameters include a preamble trigger, a transmit trigger, and a test trigger, and the timing relationships of the preamble trigger, the transmit trigger, and the test trigger during the radar operation period are shown in fig. 3. The radar waveform generation module firstly receives the pulse falling edge of the position of leading trigger-2τ (τ is 1 mu S) as a starting reference of each period, and the radar waveform generation module receives the pulse falling edge of the position of 0 τ of the transmitting trigger after 2 τ time, delays the time by 1 τ, and generates a first modulated short pulse signal (the nonlinear frequency modulation is 2 mu S and the linear frequency modulation is 5 mu S) of the transmitting excitation signal; receiving the pulse falling edge of 105 tau position of the transmission trigger by the 105 tau time waveform generating module, delaying by 1 tau time, and generating a second modulated long pulse signal (the nonlinear frequency modulation is 100 mu S, and the linear frequency modulation is 100 mu S) of the transmission excitation signal; after the radar receiving time, the waveform generating module receives the falling edge of the test trigger position of the test trigger signal and generates a modulated long pulse signal (the nonlinear frequency modulation is 100 mu S, and the linear frequency modulation is 100 mu S) of the test signal; if the radar is not in operation, the waveform generation module receives the falling edge of the mode position of the working area triggered by the test, delays for 1 mu S time, and generates a mode modulation long pulse signal (the nonlinear frequency modulation is 100 mu S and the linear frequency modulation is 100 mu S) of the test signal.
S1, the first bidirectional sixteen-bit transceiver 11 receives and drives externally transmitted frequency parameters and waveform trigger signals, and the driven frequency parameters are sent to a waveform form recognition and classification conveying frequency parameter unit 21; the waveform form recognition and classification conveying frequency parameter unit 21 converts the frequency parameters after driving into frequency control words, and sends the frequency control words into the linear frequency register 22, the non-linear frequency accumulator 23 and the single carrier frequency memory 24 for storage; the first bi-directional sixteen-bit transceiver 11 receives and drives the externally sent waveform trigger signal, and sends the driven waveform trigger signal to the waveform form recognition and classification conveying frequency parameter unit 21, the waveform form recognition and classification conveying frequency parameter unit 21 performs waveform form recognition according to the level of the waveform trigger signal, a non-linear frequency modulation signal is generated by agreeing to a high level, a low level is linear frequency modulation, and linear waveform parameters are generated and sent to the linear frequency register 22 to be stored, and the generated non-linear waveform parameters are sent to the non-linear frequency accumulator 23 to be stored;
s2, the control logic parameter output unit 25 reads the linear waveform parameter and the nonlinear waveform parameter in the linear frequency register 22 and the nonlinear frequency accumulator 23 respectively, and the control logic parameter output unit 25 generates a gate sleeve signal and drives and outputs the gate sleeve signal through the second bidirectional sixteen-bit transceiver 12;
s3, the control logic parameter output unit 25 reads the frequency control words in the linear frequency register 22, the non-linear frequency accumulator 23 and the single carrier frequency memory 24, and sends the frequency control words to the input end of the DDS waveform generation module 30, and the DDS waveform generation module 30 generates a modulated differential signal after receiving an external 240MHz clock signal;
s4, the DDS waveform generation module 30 outputs a modulated differential signal to the input end of the balun conversion module 40, and the balun conversion module 40 converts the modulated differential signal into an analog single output signal and sends the analog single output signal to the input end of the amplifying and filtering module 50;
s5, the amplification and filtering module 50 outputs radar waveforms after amplifying and filtering the analog single input signals.
The radar waveform generation method of the radar waveform generation module can generate a linear frequency modulation signal and a non-linear frequency modulation signal for normal working of the radar, and can also generate two test signals for self-checking of the radar, namely the linear frequency modulation signal and the non-linear frequency modulation signal, so that the method can be widely applied to the fields of pulse Doppler radar, pulse compression radar, moving target display radar and the like.
Claims (9)
1. A radar waveform generation module, characterized by: comprises a signal input/output module (10), an FPGA control module (20), a DDS waveform generation module (30), a balun conversion module (40), an amplifying and filtering module (50), a storage module (60) and a programming port (70),
the signal input/output module (10) is used for receiving and driving the frequency parameter and the waveform trigger signal, sending the driven frequency parameter and waveform trigger signal to the input end of the FPGA control module (20), receiving a door pocket signal from the FPGA control module (20) by the signal input/output module (10), and driving the door pocket signal and outputting the door pocket signal;
the output end of the FPGA control module (20) is connected with the input end of the DDS waveform generation module (30);
the DDS waveform generation module (30) is used for outputting the modulated differential signal to the input end of the balun conversion module (40), and the clock input end of the DDS waveform generation module (30) is connected with an external clock signal;
the balun conversion module (40) is used for converting the modulated differential signal into an analog single output signal, and the output end of the balun conversion module (40) is connected with the input end of the amplifying and filtering module (50);
the storage module (60) is used for storing a control program of the FPGA control module (20), and loading the control program into the FPGA control module (20) when the power is on;
a programming port (70) for reading a control program of the FPGA control module (20) and writing the control program to the memory module (60);
the FPGA control module (20) receives an external clock signal, and the FPGA control module (20)
Comprises a waveform form identification and classification conveying frequency parameter unit (21), a linear frequency register (22), a non-linear frequency accumulator (23), a single carrier frequency memory (24) and a control logic parameter output unit (25), wherein,
the waveform form recognition and classification conveying frequency parameter unit (21) is used for receiving the frequency parameters and waveform trigger signals after the first bidirectional sixteen-bit transceiver (11) is driven, generating frequency control words and respectively sending the frequency control words to the input ends of the linear frequency register (22), the nonlinear frequency accumulator (23) and the single carrier frequency memory (24);
the control logic parameter output unit (25) is used for reading frequency control words stored in the linear frequency register (22), the non-linear frequency accumulator (23) and the single carrier frequency memory (24) and sending the frequency control words to the input end of the DDS waveform generation module (30), and the output end of the control logic parameter output unit (25) is connected with the input end of the second bidirectional sixteen-bit transceiver (12);
the pins TCK, TMS, TDI and TDO of the programming port (70) are respectively connected with the pins TCK, TMS, TDI and TDO of the FPGA control module (20); pin TCK, pin TMS, pin TDI, pin TDO of the memory module (60) are connected with pin TCK, pin TMS, pin TDI, pin TDO of the FPGA control module (20), respectively.
2. The radar waveform generation module of claim 1, wherein: the signal input/output module (10) comprises a first bidirectional sixteen-bit transceiver (11) and a second bidirectional sixteen-bit transceiver (12), wherein,
the first bidirectional sixteen-bit transceiver (11) is used for receiving and driving the frequency parameters and the waveform trigger signals, and sending the driven frequency parameters and waveform trigger signals to the input end of the FPGA control module (20);
and the second bidirectional sixteen-bit transceiver (12) is used for receiving the door pocket signal from the FPGA control module (20), driving the door pocket signal and outputting the door pocket signal.
3. A radar waveform generation module according to claim 2, wherein: the amplifying and filtering module (50) comprises a first filter (51), an amplifier (52) and a second filter (53), wherein the input end of the first filter (51) is connected with the output end of the balun converting module (40), the output end of the first filter (51) is connected with the input end of the amplifier (52), the output end of the amplifier (52) is connected with the input end of the second filter (53), and the output end of the second filter (53) outputs radar waveforms.
4. A radar waveform generating module according to claim 3, wherein: the chip types of the first bidirectional sixteen-bit transceiver (11) and the second bidirectional sixteen-bit transceiver (12) are 74FCT163245CPV chips manufactured by IDT company of America.
5. The radar waveform generation module of claim 4, wherein: the chip model of the FPGA control module (20) is an EP20K200EFI484-2X chip manufactured by ALTERA company of America.
6. The radar waveform generation module of claim 4, wherein: the chip model of the DDS waveform generation module (30) is an AD9854ASQ chip manufactured by Analog Devices of America; the balun module (40) comprises a balun transformer, and the chip type of the balun transformer is ADTT1-1 chip manufactured by Mini-Circuits company of America.
7. The radar waveform generation module of claim 4, wherein: the first filter (51) is a low-pass filter, and the second filter (53) is a band-pass filter; the amplifier (52) is an ERA-5 monolithic radio frequency amplifier manufactured by Mini-Circuits, inc. of America.
8. A radar waveform generating module according to claim 3, wherein: the memory module (60) comprises two EPC2LI20 chips connected in parallel.
9. A radar waveform generating method of a radar waveform generating module according to any one of claims 4 to 8, comprising the steps of:
s1, the first bidirectional sixteen-bit transceiver (11) receives and drives frequency parameters and waveform trigger signals sent from the outside, and sends the driven frequency parameters into a waveform form recognition and classification conveying frequency parameter unit (21); the waveform form recognition and classification conveying frequency parameter unit (21) converts the frequency parameters after driving into frequency control words, and sends the frequency control words into a linear frequency register (22), a non-linear frequency accumulator (23) and a single carrier frequency memory (24) for storage; the first bidirectional sixteen-bit transceiver (11) receives and drives a waveform trigger signal sent from the outside, the waveform trigger signal after driving is sent to the waveform form identification and classification conveying frequency parameter unit (21), the waveform form identification and classification conveying frequency parameter unit (21) carries out waveform form identification according to the level of the waveform trigger signal, generates linear waveform parameters, sends the linear waveform parameters to the linear frequency register (22) for storage, and generates nonlinear waveform parameters, and sends the nonlinear waveform parameters to the nonlinear frequency accumulator (23) for storage;
s2, the control logic parameter output unit (25) respectively reads linear waveform parameters and nonlinear waveform parameters in the linear frequency register (22) and the nonlinear frequency accumulator (23), and the control logic parameter output unit (25) generates a gate sleeve signal and drives and outputs the gate sleeve signal through the second bidirectional sixteen-bit transceiver (12);
s3, the control logic parameter output unit (25) reads frequency control words in the linear frequency register (22), the nonlinear frequency accumulator (23) and the single carrier frequency memory (24) and sends the frequency control words to the input end of the DDS waveform generation module (30), and the DDS waveform generation module (30) receives an external clock signal and generates a modulated differential signal;
s4, the DDS waveform generation module (30) outputs a modulated differential signal to the input end of the balun conversion module (40), the balun conversion module (40) converts the modulated differential signal into an analog single output signal, and the analog single output signal is sent to the input end of the amplifying and filtering module (50);
s5, the amplifying and filtering module (50) outputs radar waveforms after amplifying and filtering the analog single input signals.
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| CN111090093A (en) * | 2019-12-11 | 2020-05-01 | 成都汇蓉国科微系统技术有限公司 | PD radar emission waveform configuration method and device based on FPGA |
| CN112327256A (en) * | 2020-09-11 | 2021-02-05 | 北京无线电测量研究所 | Method and system for generating difference pulse waveform |
| CN113030872B (en) * | 2021-03-18 | 2023-05-16 | 中国电子科技集团公司第三十八研究所 | High-low frequency excitation waveform alternate generation method suitable for Mars subsurface detection radar |
| CN113721206A (en) * | 2021-08-27 | 2021-11-30 | 四创电子股份有限公司 | Radar signal-based waveform generation device |
| CN114063027A (en) * | 2021-09-30 | 2022-02-18 | 北京无线电计量测试研究所 | Multi-radiation source radar sequence generation method and device |
| CN114488022B (en) * | 2022-01-26 | 2024-11-22 | 中国科学院空天信息创新研究院 | Linear frequency modulation signal generation method and transceiver system based on scalable processing platform |
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| EP2357487A2 (en) * | 2009-05-05 | 2011-08-17 | Uniwersytet Technologiczni-Przyrodniczy Im. Jana I Jedrzeja Sniadeckich W Bydgoszcz | Method and system for detecting short locating signals |
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