CN107316819A - Chip package and chip packaging process - Google Patents

Abstract

The invention provides a chip packaging body and a chip packaging process, which comprises the following steps: the circuit board comprises a circuit carrier plate with a conductive column, a chip, a packaging colloid, a conductive layer and a plurality of external terminals. The packaging colloid is arranged on the circuit carrier plate and covers the chip and the conductive columns. The top surfaces of the conductive posts are exposed outside the packaging adhesive and are arranged on the circuit carrier plate. The chip is disposed on the circuit carrier, and the circuit carrier is electrically connected to the chip through at least one bonding wire. The external terminal is located on the circuit carrier plate, is located on the different side of the circuit carrier plate with the chip, and is electrically connected with the chip through the circuit carrier plate. The packaging colloid is provided with a conductive layer, and the conductive layer is connected with the top surface of the conductive column, so that the conductive layer is electrically connected with the circuit carrier plate and the chip through the conductive column. In summary, the technical solution of the present invention can improve the packaging yield of the chip packaging process.

Description

Chip package and chip packaging process

technical field

The present invention relates to a chip package and a chip package process, and in particular to a chip package with conductive pillars and a chip package process.

Background technique

In the semiconductor industry, the production of integrated circuits (Integrated Circuits, IC) is mainly divided into three stages: the manufacture of wafers, the manufacture of integrated circuits, and the packaging of chips. Among them, the chip is completed through the steps of wafer fabrication, circuit design, photomask fabrication, circuit fabrication, and wafer cutting. After the electrical connection, the chip can be covered with encapsulation colloid material. The purpose of the encapsulation is to prevent the chip from being affected by moisture, heat, and noise, and to provide a medium for electrical connection between the chip and the external circuit, thus completing the integrated circuit. Production of body circuits.

In the manufacturing process of communication components, after the communication chip is coated with encapsulant, the external antenna must be further fabricated. The production of the external antenna includes forming the external antenna itself and the contact conductor connected between the external antenna and the communication chip. Generally speaking, the above-mentioned contact conductor is usually fabricated by laser drilling and filling of conductive material after the encapsulant is fabricated.

However, since the encapsulant is too thick and the energy of the laser is difficult to control, forming contact openings in the encapsulant by laser drilling faces the problem of insufficient process window. Therefore, problems such as open circuits or poor electrical characteristics may occur in the electrical connection between the external antenna and the communication chip, which leads to the failure to effectively improve the packaging yield of the communication components. Therefore, how to further improve the packaging yield of communication components has become an urgent problem to be solved.

Contents of the invention

The invention provides various chip packaging bodies and various chip packaging processes.

The invention provides a chip packaging process, which includes the following steps. A circuit carrier is provided with conductive posts. The chip is placed on the circuit carrier, wherein the chip is electrically connected to the circuit carrier through at least one bonding wire. An encapsulant is formed on the circuit carrier to cover the chip and the conductive column. Part of the encapsulant is removed to expose the top surface of the conductive pillar. A conductive layer connected to the top surface of the conductive column is formed on the encapsulant, and the conductive layer is electrically connected to the chip through the circuit carrier. A plurality of external terminals are formed on the circuit carrier, the external terminals and the chip are on different sides of the circuit carrier, and the external terminals are electrically connected to the chip through the circuit carrier.

The invention provides a chip packaging body, which includes a circuit carrier, a chip, packaging glue, a conductive layer and a plurality of external terminals. The circuit carrier has conductive pillars. The chip is arranged on the circuit carrier and is electrically connected with the circuit carrier through at least one bonding wire. The packaging colloid is arranged on the circuit carrier, wherein the packaging colloid covers the chip and the conductive column, and the top surface of the conductive column is exposed outside the packaging colloid. The conductive layer is disposed on the encapsulant to be connected to the top surface of the conductive pillar, wherein the conductive layer is electrically connected to the chip through the circuit carrier. The external terminals and the chip are located on different sides of the circuit carrier, and the external terminals are electrically connected to the chip through the circuit carrier.

In an embodiment of the invention, the method for removing part of the encapsulant includes grinding.

In an embodiment of the invention, the method for forming the conductive layer includes electroplating.

In an embodiment of the present invention, the conductive pillar and the chip are located on the same side of the circuit carrier, and the height of the conductive pillar is greater than the thickness of the chip.

The present invention provides another chip packaging process, which includes the following steps. A circuit carrier is provided with conductive posts. The chip is placed on the circuit carrier, wherein the chip is electrically connected to the circuit carrier through at least one bonding wire. An encapsulant is formed on the circuit carrier to cover the chip and the conductive column. Part of the encapsulant is removed to form an opening in the encapsulant, and the opening exposes the top surface of the conductive pillar. Fill the opening with a contact conductor. A conductive layer connected to the top surface of the contact conductor is formed on the encapsulant, and the conductive layer is electrically connected to the chip through the contact conductor and the circuit carrier.

The invention provides another chip package, which includes a circuit carrier, a contact conductor, a chip, an encapsulant, a conductive layer and a plurality of external terminals. The circuit carrier has conductive pillars. The contact conductor is arranged on the conductive column. The chip is configured on the circuit carrier and electrically connected with the circuit carrier. The packaging colloid is arranged on the circuit carrier, wherein the packaging colloid covers the chip, the conductive column and the contact conductor, and the top surface of the contact conductor is exposed outside the packaging colloid. The conductive layer is disposed on the encapsulant to be connected to the top surface of the contact conductor, wherein the conductive layer is electrically connected to the chip through the contact conductor and the circuit carrier. The external terminals and the chip are located on different sides of the circuit carrier, and the external terminals are electrically connected to the chip through the circuit carrier.

In another embodiment of the present invention, the method for removing part of the encapsulant to form an opening in the encapsulant includes laser drilling.

In another embodiment of the present invention, the method of forming the conductive layer includes electroplating.

In another embodiment of the present invention, a plurality of external terminals are formed on the circuit carrier, wherein the external terminals and the chip are located on different sides of the circuit carrier, and the external terminals are electrically connected to the chip through the circuit carrier.

In another embodiment of the present invention, the conductive post, the contact conductor and the chip are located on the same side of the circuit carrier.

Based on the above, the above embodiments of the present invention form the conductive pillars on the circuit carrier before forming the encapsulant. This process sequence can improve the encapsulation yield of the chip encapsulation process. In addition, since the fabrication of the conductive pillars is earlier than the formation of the encapsulant, the thickness of the encapsulant will not affect the yield of the conductive pillars.

In order to make the above-mentioned features and advantages of the present invention more comprehensible, the following specific embodiments are described in detail with reference to the accompanying drawings.

Description of drawings

1A to 1D are schematic diagrams of the manufacturing process of a chip package according to the first embodiment of the present invention;

1D is a schematic cross-sectional view of a chip package according to the first embodiment of the present invention;

2A to 2D are schematic diagrams of the manufacturing process of a chip package according to the second embodiment of the present invention;

2D is a schematic cross-sectional view of a chip package according to a second embodiment of the present invention.

Explanation of reference signs:

200, 200': chip package;

210: circuit carrier board;

210a: first surface;

210b: second surface;

S1, S2: surface;

212a: first pad;

212b: second pad;

214a: the first solder mask layer;

214b: the second solder mask layer;

C: conductor;

216: external terminal;

220, 220': conductive column;

H, H': height;

220a: top surface;

230: chip;

240: welding wire;

250, 250', 251: encapsulation colloid;

252: contact opening;

T1, T2, T3: thickness;

260: contact conductor;

260a: top surface;

270: Conductive layer.

detailed description

1A to 1D are schematic diagrams of a manufacturing process of a chip package according to a first embodiment of the present invention. First, please refer to FIG. 1A , there is provided a circuit carrier 210 formed with conductive pillars 220, wherein the circuit carrier 210 has a first surface 210a and a second surface 210b, and the conductive pillars 220 are located on the first surface 210a of the circuit carrier 210. superior. Specifically, the circuit carrier 210 includes a core layer 212, a conductor C, a first pad 212a, a second pad 212b, a first solder resist layer 214a and a second solder resist layer 214b, wherein the core layer 212 is hard or Flexible dielectric material, the first pad 212a and the second pad 212b are respectively located on two opposite surfaces S1, S2 of the core layer 212, and the first pad 212a is respectively connected to the conductor embedded in the core layer 212 C is electrically connected to the corresponding second pad 212b. The first solder mask layer 214a and the second solder mask layer 214b respectively cover two opposite surfaces S1 and S2 of the core layer 212 and expose the first pad 212a and the second pad 212b. In one embodiment, the conductive column 220 is located on the surface S1 of the core layer 212 of the circuit carrier 210 , and the conductive column 220 is embedded in the first solder resist layer 214 a, for example. However, the present invention does not limit that the conductive pillar 220 must be embedded in the first solder resist layer 214a. In other words, in other embodiments, the conductive pillar 220 may be disposed on the first surface 210a of the circuit carrier 210 (ie, the first solder resist layer 214a). Alternatively, in addition to being embedded in the first solder resist layer 214a, the conductive pillar 220 can be further embedded or extended into the core layer 212 .

In this embodiment, the circuit carrier 210 is, for example, a printed circuit board with single-layer circuits or a printed circuit board with multi-layer circuits. The aforementioned circuit carrier 210 can be a rigid circuit carrier or a flexible circuit carrier. The material of the first pad 212a and the second pad 212b is, for example, copper, nickel, gold, tin or a combination thereof, and the material of the first solder resist layer 214a and the second solder resist layer 214b is, for example, epoxy resin or other The solder resist material, and the material of the conductive pillar 220 is, for example, copper or copper alloy.

Next, please refer to FIG. 1B, the chip 230 is placed on the first surface 210a of the circuit carrier 210, so that the chip 230 and the conductive column 220 are located on the same side of the circuit carrier 210, and then, the chip is connected by at least one bonding wire 240. 230 is electrically connected to the first pad 212 a on the circuit carrier 210 .

As shown in FIG. 1B , the aforementioned conductive pillars 220 , chips 230 and bonding wires 240 are all located on the same side of the circuit carrier 210 . In one embodiment, the chip 230 is disposed on the surface of the solder resist layer 214a. After the chip 230 is bonded to the circuit carrier 210 , the chip 230 is electrically connected to the conductive column 220 through the conductor C in the circuit carrier 210 .

After the bonding of the chip 230 and the circuit carrier 210 is completed, then, an encapsulant 250 is formed on the circuit carrier 210 to cover the conductive pillar 220 and the chip 230 . Specifically, in addition to covering the conductive pillars 220 and the chip 230 , the aforementioned encapsulant 250 may further cover the bonding wires 240 and the first pads 212 a exposed by the solder resist layer 214 a. In this embodiment, the chip 230 is such as a communication chip, the bonding wire 240 is such as a gold wire, and the encapsulant 250 is made by injection molding (mold injection), and the thickness of the chip 230 and the arc height of the bonding wire 240 determine the The thickness T1 of the encapsulant 250 to be formed. Here, the thickness T1 of the encapsulant 250 is sufficient to cover the top surface 220 a of the conductive pillar 220 .

After the encapsulant 250 is manufactured, in this embodiment, the external terminal 216 can be formed on the second surface 210b of the circuit carrier 210, wherein the external terminal 216 is electrically connected to the second pad 212b exposed by the solder resist layer 214b. connect. For example, the external terminals 216 can be solder balls, bumps, etc., and the chip 230 can be electrically connected to external components through the bonding wires 240 , the first pads 212 a , the conductor C, the second pads 212 b and the external terminals 216 .

Then, referring to FIG. 1C , part of the encapsulant 250 is removed until the top surface 220 a of the conductive pillar 220 is exposed. In this embodiment, the encapsulant 250 can be thinned by grinding process, etching process or other processes to form the encapsulant 250'. It should be noted that when the encapsulant 250 with the thickness T1 is thinned to become the encapsulant 250', the thickness of the encapsulant 250' is T2. .

Please refer to FIG. 1D, after forming the encapsulant 250', a conductive layer 270 is then formed on the encapsulant 250', the conductive layer 270 is connected to the top surface 220a of the conductive pillar 220, so that the conductive layer 270 passes through the conductive pillar 220, the circuit The carrier board 210 is electrically connected to the chip 230 . In addition, in this embodiment, the method of forming the conductive layer 270 is, for example, electroplating, sputtering or other suitable film-forming processes, and the material of the conductive layer 270 is, for example, metal. In this embodiment, the conductive layer 270 may serve as an antenna layer.

In this embodiment, as shown in FIG. 1C and FIG. 1D , since the conductive pillar 220 can be prefabricated and arranged on the circuit carrier 210 , the flatness of the top surface 220 a of the conductive pillar 220 can be accurately controlled in this embodiment. , so that the top surface 220a is aligned (substantially coplanar) with the top surface of the thinned encapsulant 250 ′, so that the subsequently formed conductive layer 270 can be electrically connected to the top surface 220a of the conductive pillar 220 smoothly. When the flatness of the top surface 220a of the conductive pillar 220 is well controlled, the conductive layer 270 and the top surface 220a of the conductive pillar 220 will form a good ohmic contact, so that the overall packaging reliability is improved.

After the above process, the fabrication of the chip package 200 of this embodiment can be substantially completed. The aforementioned chip package 200 includes a circuit carrier 210 , conductive pillars 220 , chips 230 , bonding wires 240 , encapsulant 250 ′, conductive layer 270 and external terminals 216 . The circuit carrier 210 has a first surface 210a and a second surface 210b, and the conductive column 220, the chip 230, the bonding wire 240, the encapsulant 250' and the conductive layer 270 are located on the first surface 210a of the circuit carrier 210, and the external terminal 216 Located on the second surface 210b of the circuit carrier 210 . In one embodiment, the circuit carrier 210 includes a core layer 212, a conductor C, a first pad 212a, a second pad 212b, a first solder resist layer 214a and a second solder resist layer 214b, the first pad 212a and the second solder resist layer 214b. The second pads 212b are respectively located on two opposite surfaces S1 , S2 of the core layer 212 , and the first pads 212a are respectively electrically connected to the corresponding second pads 212b through the conductor C embedded in the core layer 212 . The chip 230 is electrically connected to the first pad 212a exposed by the solder resist layer 214a through at least one bonding wire 240 . The external terminal 216 is electrically connected to the second pad 212b exposed by the solder mask layer 214b. Therefore, the chip 230 is electrically connected to external components through at least one bonding wire 240 , the first pad 212 a , the conductor C, the second pad 212 b and the external terminal 216 . The encapsulant 250' is disposed on the circuit carrier. In addition to covering the chip 230 and the conductive column 220, it can further cover the bonding wire 240 and the first pad 212a exposed by the solder mask layer 214a, and expose the conductive column 220. The top surface 220 a of the conductive pillar 220 . The conductive layer 270 is disposed on the encapsulant 250', so that the conductive layer 270 contacts the top surface 220a of the conductive pillar 220, and is electrically connected to the chip 230 through the conductive pillar 220 and the circuit carrier 210.

The manufacturing process of the chip package will be described below with different embodiments. It must be noted here that the following embodiments continue to use the component numbers and part of the content of the previous embodiments, wherein the same numbers are used to denote the same or similar components, and descriptions of the same technical content are omitted. For the description of omitted parts, reference may be made to the aforementioned embodiments, and the following embodiments will not be repeated.

2A to 2D are schematic diagrams of a manufacturing process of a chip package according to a second embodiment of the present invention. First, please refer to FIG. 1A, FIG. 1B, FIG. 2A and FIG. 2B, the circuit carrier 210 with conductive columns 220' in this embodiment is the same as the circuit carrier 210 with conductive columns 220 shown in FIG. 1A and FIG. 1B Similar, the difference between the two is: the conductive pillar 220 ′ formed on the circuit carrier 210 in this embodiment ( FIGS. 2A and 2B ) is shorter than the conductive pillar 220 ( FIGS. 1A and 1B ).

Then, please refer to FIG. 2C , after the encapsulant 251 is fabricated, a contact opening 252 is formed in the encapsulant 251, and the contact opening 252 exposes the top surface 220a of the conductive pillar 220'. Next, a contact conductor 260 is filled in the contact opening 252, where the contact conductor 260 is electrically connected to the conductive column 220'. In this embodiment, the contact opening 252 can be formed in the encapsulant 251 by etching, grinding drilling, laser drilling or other processes. In addition, the material of the contact conductor 260 is, for example, solder paste, silver paste, or other conductive substances whose melting point is lower than the material of the conductive pillar 220'.

In this embodiment, as shown in FIG. 2B and FIG. 2C , since the conductive posts 220 ′ can be prefabricated and arranged on the circuit carrier 210 , when forming the contact opening 252 in the encapsulant 251 in this embodiment, it will be possible to Effectively reducing the aspect ratio of the contact opening 252 in the encapsulant 251 shortens the process time and increases the throughput.

Please refer to FIG. 2D , after filling the contact conductor 260 , a conductive layer 270 is then formed on the encapsulant 251 , so that the conductive layer 270 is electrically connected to the chip 230 through the contact conductor 260 , the conductive pillar 220 and the circuit carrier 210 .

In this embodiment, as shown in FIG. 2C and FIG. 2D, after the aforementioned contact conductor 260 is filled into the opening, the contact conductor 260 will have a top surface 260a, wherein the top surface 260a will not be covered by the encapsulant 251, and then This enables the subsequently formed conductive layer 270 to be electrically connected to the top surface 260 a of the contact conductor 260 smoothly.

After the above-mentioned manufacturing process, the fabrication of the chip package 200' of this embodiment can be substantially completed. The above-mentioned chip package 200′ includes a circuit carrier 210, a conductive column 220, a chip 230, a bonding wire 240, an encapsulant 251, a contact conductor 260, a conductive layer 270 and an external terminal 216. The circuit carrier 210 has a first surface 210a and a second surface 210b, and the conductive pillar 220, the chip 230, the bonding wire 240, the encapsulant 251, the contact conductor 260 and the conductive layer 270 are located on the first surface 210a of the circuit carrier 210, The external terminals 216 are located on the second surface 210 b of the circuit carrier 210 . In one embodiment, the circuit carrier 210 includes a core layer 212, a conductor C, a first pad 212a, a second pad 212b, a first solder resist layer 214a and a second solder resist layer 214b, the first pad 212a and the second solder resist layer 214b. The second pads 212b are respectively located on two opposite surfaces S1 , S2 of the core layer 212 , and the first pads 212a are respectively electrically connected to the corresponding second pads 212b through the conductor C embedded in the core layer 212 . The chip 230 is electrically connected to the first pad 212a exposed by the solder resist layer 214a through at least one bonding wire 240 . The external terminal 216 is electrically connected to the second pad 212b exposed by the solder mask layer 214b. Therefore, the chip 230 is electrically connected to external components through at least one bonding wire 240 , the first pad 212 a , the conductor C, the second pad 212 b and the external terminal 216 . The encapsulant 251 is disposed on the circuit carrier 210. In addition to covering the chip 230, the contact conductor 260 and the conductive column 220, it can further cover the bonding wire 240 and the first pad 212a exposed by the solder mask layer 214a, and make the contact The conductor 260 exposes a top surface 260a that contacts the conductor 260 . The conductive layer 270 is disposed on the encapsulant 251 , so that the conductive layer 270 contacts the conductor 260 , and is electrically connected to the chip 230 through the conductive pillar 220 and the circuit carrier 210 .

To sum up, in the above embodiments of the present invention, the conductive pillars are formed on the circuit carrier before forming the encapsulant. This process sequence can improve the encapsulation yield of the chip encapsulation process. In addition, since the fabrication of the conductive pillars is earlier than the formation of the encapsulant, the thickness of the encapsulant will not affect the yield of the conductive pillars.

Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present invention, rather than limiting them; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that: It is still possible to modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements for some or all of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the technical solutions of the various embodiments of the present invention. scope.

Claims (11)

1. a kind of chip encapsulating manufacturing procedure, including：

There is provided has conductive pole on line carrier plate, the line carrier plate；

Chip is placed in line carrier plate, and the chip is passed through an at least bonding wire and line carrier plate electricity Property connection；

Packing colloid is formed on the line carrier plate to coat the chip and the conductive pole；

The packing colloid of part is removed to expose the top surface of the conductive pole；And

The conductive layer being connected with the top surface of the conductive pole, wherein institute are formed on the packing colloid Conductive layer is stated to be electrically connected with by the line carrier plate and the chip；

Multiple outside terminals are formed on the line carrier plate, wherein the multiple outside terminal and the core Piece is located at the not homonymy of the line carrier plate, and the multiple outside terminal passes through the line carrier plate and institute State chip electric connection.

2. chip encapsulating manufacturing procedure according to claim 1, wherein removing the packing colloid of part Method include grinding.

3. chip encapsulating manufacturing procedure according to claim 1, wherein forming the method bag of the conductive layer Include plating.

4. a kind of chip packing-body, including：

Line carrier plate, the line carrier plate has conductive pole；

Chip, is configured on the line carrier plate, and passes through an at least bonding wire and line carrier plate electricity Property connection；

Packing colloid, is configured on the line carrier plate, wherein the packing colloid coat the chip and The conductive pole, and the conductive pole top surface outside the packing colloid；

Conductive layer, configuration is connected on the packing colloid with the top surface with the conductive pole, wherein The conductive layer is electrically connected with by the line carrier plate and the chip；And

Multiple outside terminals, wherein the multiple outside terminal is located at the line carrier plate with the chip Not homonymy, and the multiple outside terminal passes through the line carrier plate and chip electric connection.

5. chip packing-body according to claim 4, wherein the conductive pole is located at the chip The homonymy of the line carrier plate, and thickness of the height more than the chip of the conductive pole.

6. a kind of chip encapsulating manufacturing procedure, including：

There is provided has conductive pole on line carrier plate, the line carrier plate；

Chip is placed in line carrier plate, and the chip is passed through an at least bonding wire and line carrier plate electricity Property connection；

Packing colloid is formed on the line carrier plate to coat the chip and the conductive pole；

The packing colloid of part is removed with forming opening in the packing colloid, wherein the opening Expose the top surface of the conductive pole；

Contact conductor is inserted in said opening；And

The conductive layer with the top surface connection for contacting conductor is formed on the packing colloid, wherein described Conductive layer is electrically connected with by the contact conductor and the line carrier plate with the chip.

7. chip encapsulating manufacturing procedure according to claim 6, wherein removing the packing colloid of part Include laser drill in the method that the opening is formed in the packing colloid.

8. chip encapsulating manufacturing procedure according to claim 6, wherein forming the method bag of the conductive layer Include plating.

9. chip encapsulating manufacturing procedure according to claim 6, is additionally included on the line carrier plate and is formed Multiple outside terminals, wherein the multiple outside terminal is located at the difference of the line carrier plate with the chip Side, and the multiple outside terminal passes through the line carrier plate and chip electric connection.

10. a kind of chip packing-body, including：

Line carrier plate, the line carrier plate has conductive pole；

Conductor is contacted, is configured on the conductive pole；

Chip, is configured on the line carrier plate, and is electrically connected with the line carrier plate；

Packing colloid, is configured on the line carrier plate, wherein the packing colloid cladding chip, The conductive pole and the contact conductor, and the top surface for contacting conductor is outside packing colloid；

Conductive layer, is configured to be connected with the top surface for contacting conductor on the packing colloid, its Described in conductive layer pass through the contact conductor and the line carrier plate and the chip are electrically connected with；And

Multiple outside terminals, wherein the multiple outside terminal is located at the line carrier plate with the chip Not homonymy, and the multiple outside terminal passes through the line carrier plate and chip electric connection.

11. chip packing-body according to claim 10, wherein the conductive pole, the contact are led Body is located at the homonymy of the line carrier plate with the chip.