CN106970317A - A kind of degradation failure detection sensor based on protection band - Google Patents

Abstract

The invention discloses an aging fault detection sensor based on a guard band, which includes a delay unit, a stability detector, an output latch and a first inverter, the delay unit is used to control the switch of the aging fault detection sensor, and the time delay is The delayed clock signal GB is generated when the unit is turned on, and the aging fault detection sensor is in the anti-aging state when the delay unit is turned off; the stability detector receives the delayed clock signal GB, the reverse signal nclk of the original clock signal and the CL signal of the combinational logic circuit, The delayed clock signal GB and the reverse signal nclk of the original clock signal form a guard band time, and detect whether the combinational logic circuit signal CL jumps during the guard band time, and output a jump signal to the output latch; the output latch is used for Latch the received transition signal and issue an alarm signal. The invention has the advantages of simple structure, low power consumption, self-aging resistance and high reliability, can predict the natural aging fault of the circuit, and can meet the requirement of low power consumption of the chip.

Description

An Aging Fault Detection Sensor Based on Guard Band

technical field

The invention belongs to the field of integrated circuit fault detection, in particular to an aging fault detection sensor based on a protective band.

Background technique

With the rapid development of semiconductor technology, the feature size of the circuit is getting smaller and smaller, the integration level is getting higher and higher, and the chip area is getting smaller and smaller. This is an inevitable direction for the development of integrated circuits, that is, towards high integration. It will The performance of the circuit is improved, and the production cost is also reduced. Another direction of the development of integrated circuits is to develop towards high reliability. The development of semiconductor technology has made the gate dielectric thinner and the channel shorter. These changes have also brought about circuit reliability problems. In some fields with relatively high reliability requirements, such as aerospace, reliability is even as important as technical performance, or even the dominant factor.

Aging is a natural phenomenon of everything, and integrated circuits are no exception. The rapidly shrinking feature size leads to a series of negative mechanisms that accelerate circuit aging. According to the different physical mechanisms of their generation, they are divided into: negative bias temperature instability, hot carrier injection, time-dependent dielectric breakdown, and electromigration. These aging effects negatively affect the delay of the circuit, causing it to increase with the passage of time, resulting in timing violations in the circuit path, errors in the circuit function, and ultimately affecting the life of the circuit, resulting in a continuous decrease in the performance and operating frequency of the chip. , the chip malfunctions. How to design anti-aging circuits and prolong the service life of chips has become a hot issue in integrated circuit design. How to accurately monitor the aging situation and obtain aging data to measure the degree of aging is a prerequisite for anti-aging circuit design.

Chinese patent application CN102435931A, online circuit aging prediction method based on measurement of leakage changes By measuring leakage changes to predict the aging of the circuit due to negative bias temperature instability NBTI effect, it can avoid the real-time noise generated when the circuit performs functional operations on the measurement accuracy Impact. However, its scope of use is small, and the detection circuit is always in working condition, which will increase the power consumption of the circuit, and at the same time, it does not have anti-aging ability.

Chinese patent application CN106291322A is a CMOS circuit aging sensor adopting a delay amplification structure, including a reference delay circuit, a delay detection circuit, a delay amplifier, a digital quantization circuit, an SR latch, a first two-input AND gate and a first inverter phase device, the reference delay circuit is connected to the delay detection circuit, the clock output terminal of the reference delay circuit is connected to the third input terminal of the delay detection circuit, and the second output terminal of the reference delay circuit is connected to the first two inputs and the first two inputs and the delay detection circuit respectively. The first input end of the gate is connected to the first input end of the delay amplifier, the output end of the delay detection circuit is connected to the first input end of the SR latch, and the output end of the SR latch is connected to the second input end of the delay amplifier. The input end is connected, the delay amplifier is connected to the first inverter, the output end of the first inverter is connected to the second input end of the first two-input AND gate, the output end of the first two-input AND gate is connected to a digital quantization circuit input connection. The structure of the sensor is complex, which leads to a large power consumption to the original circuit during actual use, which cannot meet the current requirements for low power consumption of the chip.

Contents of the invention

The purpose of the present invention is to overcome the shortcomings of the existing circuit aging sensor, such as complex structure, high power consumption, and inability to resist aging, and provide an aging fault detection sensor based on a guard band. The sensor has a simple structure, low power consumption, self-aging resistance, and reliability High predictability of natural aging failures.

The realization scheme of the present invention is as follows: a kind of aging fault detection sensor based on guard band, comprises delay unit, stable detector, output latch and first inverter, and delay unit is used for controlling the switch of aging fault detection sensor , the delayed clock signal GB is generated when the delay unit is turned on, and the aging fault detection sensor is in an anti-aging state when the delay unit is turned off; the stability detector receives the delayed clock signal GB, the reverse signal nclk of the original clock signal and the combination logic circuit The CL signal, the delayed clock signal GB and the reverse signal nclk of the original clock signal form a guard band time (that is, the time window Tg), and detect whether the combinational logic circuit signal CL jumps during the guard band time, and output to the output latch Transition signal; the output latch is used to latch the received transition signal and issue an alarm signal.

The delay unit has a clock input terminal, a monitoring signal input terminal (Monitor) and an output terminal, the stability detector has a first input terminal, a second input terminal, a third input terminal and an output terminal, and the output latch has a first The input terminal, the second input terminal and the output terminal, the output terminal of the delay unit is connected with the first input terminal of the stable detector, the second input terminal of the stable detector is connected with the combinational logic circuit, and the input terminal of the first inverter is connected The output terminal of the clock is connected to the third input terminal of the stability detector, the output terminal of the stability detector is connected to the first input terminal of the output latch, and the second input terminal of the output latch is connected to the reset signal reset.

The delay unit includes a two-input AND gate T1, a two-input AND gate T2, an inverter S1, an inverter S2, an inverter S3... an inverter Sn, a two-input NOR gate D1, an inverter The input terminal of S1 is connected to the monitoring signal Monitor, the output terminal of the inverter S1 is connected to the first input terminal of the two-input NOR gate D1, and the clk clock signal is connected to the second input terminal of the two-input NOR gate D1, and the two-input OR The output terminal of the NOT gate D1 is connected to the input terminal of the inverter S2, the output terminal of the inverter S2 is connected to the first input terminal of the two-input AND gate T1, and the monitoring signal Monitor is connected to the second input terminal of the two-input AND gate T1 , the output of the two-input AND gate T1 is connected to the input of the inverter S3, and the output of the inverter S3 is connected to the input of the next series inverter, and the number of series inverters is adjusted according to the delay requirement , the output terminal of the last stage inverter Sn is connected to the first input terminal of the two-input AND gate T2, the monitoring signal Monitor is connected to the second input terminal of the two-input AND gate T2, and the output of the two-input AND gate T2 is the delayed The output GB of time unit.

The stable detector includes basic RS flip-flop H1, basic RS flip-flop H2, AND gate T3, AND gate T4, inverter S4, inverter S5, inverter S6, inverter S7, or NOT gate D2 . The signal CL from the combinational logic is connected to the first input terminal of the AND gate T3 after passing through the NOT gate S9, the GB signal from the delay unit is connected to the second input terminal of the AND gate T3, and the output terminal of the AND gate T3 is connected to the basic RS The first input terminal of the flip-flop H1, the nclk signal is connected to the second input terminal of the RS flip-flop H1 through the NOT gate S7, the CL signal is connected to the first input terminal of the AND gate T4 at the same time, and the GB signal is connected to the first input terminal of the AND gate T4 Two input terminals, the output terminal of the AND gate T4 is connected to the first input terminal of the basic RS flip-flop H2, the nclk signal is connected to the second input terminal of the basic RS flip-flop H2 through the inverter S4, and the output of the basic RS flip-flop H1 The terminal is output to the first input terminal of the NOR gate D2 through the inverter S5, the output terminal of the basic RS flip-flop H2 is output to the second input terminal of the NOR gate D2 through the inverter S6, and the output of the NOR gate D2 is is the output of the stability detection unit.

The output latch includes an inverter S8, and a basic RS flip-flop H3 composed of a NOR gate T5 and a NOR gate T6. The signal OUT_SC from the stability detection unit is connected to the first input terminal of the basic RS flip-flop H3, the reset signal reset is output to the second input terminal of the basic RS flip-flop H3 after passing through the inverter S8, and the output of the basic RS flip-flop H3 is the output of the aging prediction sensor.

The protection band-based aging fault detection sensor of the invention can be inserted into several critical timing paths in the circuit to monitor their time delay changes online to predict the aging of the circuit. The sensor circuit is embedded in the flip-flop and can receive the output signal from the combinatorial logic just like the flip-flop. The clock signal is delayed for a certain time by the delay unit, and then sent to the stability detector together with the reverse signal of the original clock signal to form a desired protection interval (GuardbandInterval), that is, the time window Tg, in which the key of the monitoring system is The signal jump at the end of the combinational logic on the path (the size of Tg is very close to a delay fault), so as to know the aging of the circuit and realize the prediction of aging. If the aging of the circuit does not exceed the prescribed threshold, the signal output from the end of the combinatorial logic does not jump within the protection interval Tg. However, if the sensor detects that the signal output from the end of the combinatorial logic jumps within the range of Tg, it indicates that the aging of the combinatorial logic exceeds a specified threshold. The sensor will output a jump signal to the output latch for latching, thus sending an alarm signal to the user. The present invention has a simple structure and a reasonable design. Compared with the existing aging detection sensor, the present invention adopts its own anti-aging design, and can issue an early warning before the delay causes circuit failure, and the power consumption of the sensor is also low.

Description of drawings

Fig. 1 is a connection diagram of an aging fault detection sensor based on a guard band in the present invention.

Fig. 2 is a structural diagram of the delay unit of the present invention.

Fig. 3 is a structural diagram of a stability detector in the present invention.

FIG. 4 is a structural diagram of an output latch in the present invention.

Fig. 5 is a structure diagram of the protection band-based aging fault detection sensor of the present invention.

Fig. 6 is a schematic diagram of the working principle of the protection band-based aging fault detection sensor of the present invention.

detailed description

The present invention will be further described through the embodiments below in conjunction with the accompanying drawings.

In actual use, the designed natural aging sensor circuit can be inserted into several critical timing paths in the circuit to monitor their time delay changes online to predict the aging of the circuit. The aging sensor circuit is embedded in the flip-flop and can receive the output signal from the combinational logic just like the flip-flop.

The aging sensor mainly includes three parts: a delay unit 1, a stable detector 2 for detecting aging, and an output latch 3. The data path diagram of each component is shown in Figure 1. The delay unit 1 has a clock input terminal, a monitoring signal input terminal (Monitor) and an output terminal, the stability detector 2 has a first input terminal, a second input terminal, a third input terminal and an output terminal, and the output latch 3 has a first input terminal and an output terminal. An input terminal, a second input terminal and an output terminal, the output terminal of the delay unit 1 is connected to the first input terminal of the stable detector 2, the second input terminal of the stable detector 2 is connected to the combinational logic circuit, and the first inverter The input terminal of 4 is connected to the clock, the output terminal of the first inverter 4 is connected to the third input terminal of the stable detector 2, the output terminal of the stable detector 2 is connected to the first input terminal of the output latch 3, and the output latch The second input end of the device 3 is connected to the reset signal reset.

As shown in Figure 2, the delay unit 1 of the aging fault detection sensor based on the protection band of the present invention includes a two-input AND gate T1, a two-input AND gate T2, an inverter S1, an inverter S2, an inverter S3.. .Sn, the two-input NOR gate D1, the input terminal of the inverter S1 is connected to the monitoring signal Monitor, the output terminal of the inverter S1 is connected to the first input terminal of the two-input NOR gate D1, and the clock signal clk is connected to the two-input NOR gate D1 The second input end of the NOR gate D1, the output of the two-input NOR gate D1 is connected to the input end of the inverter S2, and the output end of the inverter S2 is connected to the first input end of the E two-input AND gate T1, and the monitoring signal The Monitor is connected to the second input terminal of the two-input AND gate T1, the output terminal of the two-input AND gate T1 is connected to the input terminal of the inverter S3, and the output terminal of the inverter S3 is connected to the input terminal of the next inverter, and the inverter The number of phasers is adjusted according to the delay time. The output terminal of the last stage inverter Sn is connected to the first input terminal of the two-input AND gate T2, and the monitoring signal Monitor is connected to the second input of the two-input AND gate T2. The output of the two-input AND gate T2 is the output GB of the delay unit 1. MONITOR is the overall control signal of the aging fault detection sensor, it is a slow clock signal, and controls the switch of the entire aging fault detection sensor. When the aging detection is to be started, the MONITOR signal is turned on, and it can be turned off when the detection is not needed. Monitor=1, the delay unit is turned on. At this time, the NOR gate D1 is equivalent to an inverter. After the clock CLK passes through the NOR gate D1, the inversion signal of CLK is obtained, and then several stages of inverters can realize the delay of the signal. Function, the tail of the delay unit uses an AND gate T2 to realize the control of the switch of the delay unit by the Monitor, and the output signal is the delayed GB signal. Similarly, when Monitor=0, the delay unit is turned off, and the unit is in an anti-aging state. Since the aging of functional circuits is a gradual process, there is no need for the aging prediction unit to keep working forever, so the actual working time is very small, and the delay unit can be considered as not aging.

As shown in Figure 3, the stability detector 2 of the aging fault detection sensor based on the guard band in the present invention mainly includes a basic RS flip-flop H1, a basic RS flip-flop H2, an AND gate T3, an AND gate T4, an inverter S4, an inverter Inverter S5, inverter S6, inverter S7, NOR gate D2. The signal CL from the combinational logic is connected to the first input terminal of the AND gate T3 after passing through the NOT gate S9, the GB signal from the delay unit is connected to the second input terminal of the AND gate T3, and the output terminal of the AND gate T3 is connected to the basic RS The first input terminal of the flip-flop H1, the nclk signal is connected to the second input terminal of the basic RS flip-flop H1 through the NOT gate S7, the CL signal is connected to the first input terminal of the AND gate T4 at the same time, and the GB signal is connected to the AND gate T4 The second input terminal, the output terminal of the AND gate T4 is connected to the first input terminal of the basic RS flip-flop H2, the nclk signal is connected to the second input terminal of the basic RS flip-flop H2 through the inverter S4, and the basic RS flip-flop H1 The output terminal is output to the first input terminal of the NOR gate D2 through the inverter S5, and the output terminal of the basic RS flip-flop H2 is output to the second input terminal of the NOR gate D2 through the inverter S6, or the output of the NOR gate D2 is the output of the stability detection unit. The stability detector 2 is also the core unit of this design, the delay unit 1 delays the clock signal, the delayed clock signal GB and the reverse signal nclk of the original clock signal are sent to the stability detector 2 and the signal becomes 1, and then After the basic RS flip-flop H1 and a non-gate S5, the signal remains at 1, so that the final flag signal is 0; and when nclk and GB are 1 at the same time, these two signals will together construct the guard band time, and at the same time from The CL signal of the combinational logic circuit is also sent to the stability detector 2. If the signal CL of the combinational logic circuit jumps within this time range, no matter from 0-1 or 1-0, the basic combination of two NOR gates The outputs of RS flip-flops H1 and H2 are always 1. After passing through the NOR gate D2, the final flag signal is set to 1, which means that the circuit is aging to a certain threshold and an error is about to occur.

As shown in FIG. 4 , the output latch 3 of the guard band-based aging fault detection sensor of the present invention mainly includes an inverter S8, and a basic RS flip-flop H3 composed of a NOR gate T5 and a NOR gate T6. The signal OUT_SC from the stability detection unit is connected to the first input terminal of the basic RS flip-flop H3, the reset signal reset is output to the second input terminal of the basic RS flip-flop H3 after passing through the inverter S8, and the output of the basic RS flip-flop H3 is the output of the aging prediction sensor. Reset in Figure 4 is a reset signal. When reset is 0, it will be 1 after passing through the inverter S8, and the result will be 0 after passing through the basic RS flip-flop H3. At this time, the circuit is in a non-detection state; when reset is 1, After the non-gate S8 is 0, when OUT_SC is 0, the result can be latched. When OUT_SC jumps to 1, the output can be set to 1, and an alarm signal can be sent to notify the peripheral circuit or the user to adjust the circuit in time. In the detection circuit Reset can be set to 0 when it is not working, and reset to 1 when it needs to be detected, which can reduce the working time of the latch, and the latch unit can be considered as not aging.

Fig. 5 is the structural diagram of the aging fault detection sensor based on the guard band of the present invention, the aging fault detection sensor delay unit receives the clock signal, is used to generate the delayed clock signal GB, then the reverse signal nclk and the combination of the GB signal and the original clock signal The CL signal of the logic circuit is sent to the stability detection unit together, the delayed clock signal GB and the reverse signal nclk of the original clock signal form a guard band time (that is, the time window Tg), and the combined logic circuit signal CL is detected within the guard band time Whether there is a jump, and the detection result is output to the output latch, and the output latch is used to latch the received jump signal and send an alarm signal. What is marked in Figure 6 is that the CL signal jumps in the protection zone, indicating that the circuit has aged to a certain threshold.

The invention has simple structure, reasonable design, low actual working power consumption, adopts self-aging anti-aging design, realizes on-line aging prediction, and can successfully predict the occurrence of aging faults.

Claims (4)

1. A kind of aging fault detection sensor based on guard band, it is characterized in that described sensor comprises time-delay unit, stable detector, output latch and the first inverter, and time-delay unit is used for controlling the aging fault detection sensor The switch generates a delayed clock signal GB when the delay unit is turned on, and the aging fault detection sensor is in an anti-aging state when the delay unit is turned off; the stability detector receives the delayed clock signal GB, the reverse signal nclk of the original clock signal, and a combinational logic circuit The CL signal, the delayed clock signal GB and the reverse signal nclk of the original clock signal form a guard band time, and detect whether the combinational logic circuit signal CL jumps during the guard band time, and output a jump signal to the output latch; output The latch is used to latch the received jump signal and send an alarm signal; the delay unit has a clock input end, a monitoring signal input end and an output end, and the stability detector has a first input end, a second input end, a second input end, and a second input end. Three input terminals and output terminals, the output latch has a first input terminal, a second input terminal and an output terminal, the output terminal of the delay unit is connected with the first input terminal of the stable detector, and the second input terminal of the stable detector The combinational logic circuit is connected, the input end of the first inverter is connected to the clock, the output end is connected to the third input end of the stable detector, the output end of the stable detector is connected to the first input end of the output latch, and the output latch The second input end of the second input terminal is connected to the reset signal reset. 2. The aging fault detection sensor based on guard band according to claim 1, characterized in that said delay unit comprises two-input AND gate T1, two-input AND gate T2, inverter S1, inverter S2, inverter Phase S3... Inverter Sn, a two-input NOR gate D1, the input end of the inverter S1 is connected to the monitoring signal Monitor, and the output end of the inverter S1 is connected to the first input end of the two-input NOR gate D1, The clk clock signal is connected to the second input end of the two-input NOR gate D1, the output end of the two-input NOR gate D1 is connected to the input end of the inverter S2, and the output end of the inverter S2 is connected to the two-input AND gate T1 The first input terminal of the monitor signal Monitor is connected to the second input terminal of the two-input AND gate T1, the output terminal of the two-input AND gate T1 is connected to the input terminal of the inverter S3, and the output of the inverter S3 is connected to the next series The input terminal of the inverter, the number of serial inverters is adjusted according to the delay time, the output terminal of the last stage inverter Sn is connected to the first input terminal of the two-input AND gate T2, and the monitoring signal Monitor is connected to The second input terminal of the two-input AND gate T2, the output of the two-input AND gate T2 is the output GB of the delay unit. 3. The aging fault detection sensor based on guard band according to claim 1, characterized in that said stable detector comprises basic RS flip-flop H1, basic RS flip-flop H2, AND gate T3, AND gate T4, inverter S4, inverter S5, inverter S6, inverter S7, and NOR gate D2; the signal CL from the combinational logic is connected to the first input terminal of the AND gate T3 after passing through the NOR gate S9, and the GB from the delay unit The signal is connected to the second input terminal of the AND gate T3, and the output terminal of the AND gate T3 is connected to the first input terminal of the basic RS flip-flop H1, and the nclk signal is connected to the second input terminal of the RS flip-flop H1 through the NOT gate S7, CL The signal is connected to the first input terminal of the AND gate T4 at the same time, the GB signal is connected to the second input terminal of the AND gate T4, the output terminal of the AND gate T4 is connected to the first input terminal of the basic RS flip-flop H2, and the nclk signal is inverted The switch S4 is connected to the second input terminal of the basic RS flip-flop H2, the output terminal of the basic RS flip-flop H1 is output to the first input terminal of the NOR gate D2 through the inverter S5, and the output terminal of the basic RS flip-flop H2 is inverted The output of the phase switch S6 is to the second input end of the NOR gate D2, and the output of the NOR gate D2 is the output of the stability detection unit. 4. The aging fault detection sensor based on guard band according to claim 1, characterized in that said output latch comprises an inverter S8, and a basic RS flip-flop composed of a NOR gate T5 and a NOR gate T6 H3; the signal OUT_SC from the stability detection unit is connected to the first input terminal of the basic RS flip-flop H3, the reset signal reset is output to the second input terminal of the basic RS flip-flop H3 after passing through the inverter S8, and the basic RS flip-flop H3 The output of is the output of the aging prediction sensor.