CN106711187A - High K power device with high withstand voltage and low specific on-resistance - Google Patents
High K power device with high withstand voltage and low specific on-resistance Download PDFInfo
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- 239000004065 semiconductor Substances 0.000 abstract description 5
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- H—ELECTRICITY
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- H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
- H10D62/103—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices
- H10D62/105—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE]
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- H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
- H10D62/103—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices
- H10D62/105—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE]
- H10D62/106—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE] having supplementary regions doped oppositely to or in rectifying contact with regions of the semiconductor bodies, e.g. guard rings with PN or Schottky junctions
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Abstract
本发明涉及的高耐压低比导的高K功率器件属于功率半导体器件技术领域。本发明在漂移区引入高K介质槽以辅助耗尽漂移区降低器件的导通电阻，还可以调制器件的体内电场分布来提高器件的击穿电压。在高K介质槽下界面引入的高浓度N型条，开态时，提供低阻通道，降低器件的导通电阻。同时利用高K介质槽的辅助耗尽作用提高N型条和漂移区的浓度进一步降低器件的导通电阻；关态时，缩短电离积分路径，可以提高体内电场，提高器件击穿电压。并且浅而宽的高K介质槽结构，在工艺填充时更容易实现。采用本发明可获得各种性能优良的横向低比导高耐压高K半导体功率器件。
The high-K power device with high withstand voltage and low specific conductance involved in the invention belongs to the technical field of power semiconductor devices. The invention introduces a high-K dielectric groove in the drift region to assist the depletion of the drift region to reduce the on-resistance of the device, and can also modulate the internal electric field distribution of the device to increase the breakdown voltage of the device. The high-concentration N-type strips introduced at the lower interface of the high-K dielectric groove provide a low-resistance channel and reduce the on-resistance of the device when it is in the on state. At the same time, using the auxiliary depletion effect of the high-K dielectric groove to increase the concentration of N-type strips and drift regions further reduces the on-resistance of the device; in the off state, shortening the ionization integration path can increase the electric field in the body and increase the breakdown voltage of the device. And the shallow and wide high-K dielectric groove structure is easier to realize during process filling. By adopting the invention, various lateral low-specific conduction, high-voltage-resistant, and high-K semiconductor power devices with excellent performance can be obtained.
Description
技术领域technical field
本发明涉及的高耐压低比导的高K功率器件属于功率半导体器件技术领域。The high-K power device with high withstand voltage and low specific conductance involved in the invention belongs to the technical field of power semiconductor devices.
背景技术Background technique
功率半导体器件，由P=IV可知，就是一类可以在高压、大电流下工作的微电子器件。并沿着提高功率和频率的方向发展。基于以上的要求，功率器件的设计要求具有高的击穿电压BV，低的比导通电阻Ron,sp和实现开态和关态之间的快速转换。对于现阶段通常研究的硅材料器件，比导通电阻Ron,sp与击穿电压BV成指数增长的关系——即“硅极限”，比导通电阻增加会使器件的导通损耗增加，降低器件的性能。实现器件比导通电阻Ron,sp和耐压BV之间的折中，是设计功率器件的主要研究工作。Power semiconductor devices, known from P=IV, are a type of microelectronic devices that can work under high voltage and high current. And develop along the direction of increasing power and frequency. Based on the above requirements, the design of power devices requires high breakdown voltage BV, low specific on-resistance Ron,sp and fast switching between on-state and off-state. For silicon material devices that are usually studied at this stage, the relationship between the specific on-resistance Ron,sp and the breakdown voltage BV increases exponentially—that is, the "silicon limit". The increase in the specific on-resistance will increase the conduction loss of the device and reduce the device performance. Achieving a compromise between device specific on-resistance Ron,sp and withstand voltage BV is the main research work in designing power devices.
随着半导体工艺技术的不断发展，器件的栅极尺寸由.5um减小到.18um，器件越来越小，集成度越来越高，功耗越来越低。所以在保持器件高的击穿电压的同时减小器件的表面积也就是漂移区的长度，成为设计功率器件的又一考虑因素。槽型功率器件是将介质槽深入漂移区内，使漂移区向下弯曲，缩小横向漂移区长度，使得器件的表面积大大减小，减小生产成本。并且槽栅结构可以将横向沟道转变成纵向沟道。开态时，在槽栅的边缘有电子的积累，形成沟道，使器件内部电流分布更加均匀；关态时，槽栅结构可以优化纵向电场，和纵向介质槽承担部分漏极电压，使器件耐压得到提高。With the continuous development of semiconductor process technology, the gate size of the device is reduced from .5um to .18um, the device is getting smaller, the integration level is getting higher, and the power consumption is getting lower and lower. Therefore, reducing the surface area of the device, that is, the length of the drift region while maintaining a high breakdown voltage of the device, has become another consideration for designing power devices. The trench type power device is to deepen the dielectric trench into the drift region, so that the drift region is bent downward, and the length of the lateral drift region is reduced, so that the surface area of the device is greatly reduced, and the production cost is reduced. And the trench gate structure can transform the lateral channel into a vertical channel. In the on state, electrons accumulate on the edge of the trench gate to form a channel, which makes the current distribution in the device more uniform; in the off state, the trench gate structure can optimize the vertical electric field, and the vertical dielectric groove bears part of the drain voltage, making the device Pressure resistance is improved.
为了进一步优化比导通电阻和器件耐压的关系，陈星弼院士提出了超结功率器件，但是超结功率器件存在衬底辅助耗尽效应，使得N条和P条电荷不平衡，进而大大影响器件的耐压特性。而在器件的漂移区中引入高K介质槽结构，由于硅材料的介电系数（εs=11.9）远小于高K材料的介电系数（高K材料介电系数可达几百甚至上千），硅材料的电导率大于高K材料的电导率。在开态时，硅材料的电流密度远大于高K材料的电流密度，器件呈现低阻通道现象；在关态时，由于高K材料的介电系数远高于硅材料的介电系数，因此绝大部分的电力线经过高K介质终止于源端，因此硅层内及表面电场较低，避免出现提前击穿，提高器件的耐压。高K介质槽可以辅助耗尽漂移区，提高器件的耐压和降低器件的比导通电阻的作用。相对于低K介质槽结构，高K介质槽在工艺上具有更大的优势：（1）击穿电压随漂移区浓度范围变化不是很明显，工艺容差较大；（2）由于高K介质槽设计成浅而宽的槽型结构，在工艺填充时更容易实现，所以高K介质槽具备更好的应用前景。In order to further optimize the relationship between the specific on-resistance and the withstand voltage of the device, academician Chen Xingbi proposed a super-junction power device, but the super-junction power device has a substrate-assisted depletion effect, which makes the charges of the N and P bars unbalanced, which greatly affects the device. pressure characteristics. However, when a high-K dielectric trench structure is introduced into the drift region of the device, since the dielectric coefficient of the silicon material (ε s = 11.9) is much smaller than that of the high-K material (the dielectric coefficient of the high-K material can reach hundreds or even thousands ), the conductivity of the silicon material is greater than that of the high-K material. In the on state, the current density of the silicon material Far greater than the current density of high-K materials, the device presents a low-resistance channel phenomenon; in the off state, since the dielectric coefficient of high-K materials is much higher than that of silicon materials, most of the power lines are terminated by high-K dielectrics At the source end, the electric field inside and on the surface of the silicon layer is low, which avoids premature breakdown and improves the withstand voltage of the device. The high-K dielectric groove can help deplete the drift region, improve the withstand voltage of the device and reduce the specific on-resistance of the device. Compared with the low-K dielectric tank structure, the high-K dielectric tank has greater advantages in technology: (1) The breakdown voltage does not change significantly with the concentration range of the drift region, and the process tolerance is large; (2) Due to the high-K dielectric The groove is designed as a shallow and wide groove structure, which is easier to realize during process filling, so the high-K dielectric groove has better application prospects.
发明内容Contents of the invention
本发明申请的目的在于通过在器件漂移区中引入高K介质槽辅助耗尽漂移区，提高器件的击穿电压，降低器件的比导通电阻，缓解器件的“硅极限”问题。通过在高K介质槽的下界面引入高浓度的N+条，提供低阻通道，进一步降低器件的导通电阻，进而降低器件的比导通电阻。在器件的左边引入深槽栅结构，在开态时，在栅氧化层处积累电子，提供低阻通道，降低器件比导通电阻。三者共同作用，进一步扩展了低比导高压功率器件的应用范围。The purpose of the application of the present invention is to improve the breakdown voltage of the device, reduce the specific on-resistance of the device, and alleviate the "silicon limit" problem of the device by introducing a high-K dielectric groove into the drift region of the device to assist the depletion of the drift region. By introducing high-concentration N + strips at the lower interface of the high-K dielectric groove, a low-resistance channel is provided, and the on-resistance of the device is further reduced, thereby reducing the specific on-resistance of the device. A deep trench gate structure is introduced on the left side of the device. In the on state, electrons are accumulated at the gate oxide layer to provide a low-resistance channel and reduce the specific on-resistance of the device. The three work together to further expand the application range of low specific conductance high voltage power devices.
为解决上述问题，本发明实施例提供了如下技术方案：In order to solve the above problems, the embodiments of the present invention provide the following technical solutions:
一种高耐压低比导的高K功率器件，其元胞结构包括P型衬底11、氧化层32，N型漂移区21，其特征在于：所述N型漂移区21包括P型阱区13，高K介质槽41；多晶硅栅电极54。A high-K power device with high withstand voltage and low specific conductance, its cellular structure includes a P-type substrate 11, an oxide layer 32, and an N-type drift region 21, and is characterized in that: the N-type drift region 21 includes a P-type well Region 13, high-K dielectric trench 41; polysilicon gate electrode 54.
具体的，specific,
所述P型阱区13包括P型重掺杂区12和N型重掺杂区23，其上端是源端电极52，左端是栅氧化槽32。The P-type well region 13 includes a P-type heavily doped region 12 and an N-type heavily doped region 23 , the upper end of which is a source terminal electrode 52 , and the left end is a gate oxide groove 32 .
具体的，specific,
所述源端电极52和栅电极51通过钝化层33隔离。The source electrode 52 and the gate electrode 51 are separated by the passivation layer 33 .
具体的，specific,
所述多晶硅栅电极54设置在N漂移区21的左端。The polysilicon gate electrode 54 is disposed at the left end of the N drift region 21 .
具体的，specific,
所述多晶硅栅电极54延伸到漂移区里面与氧化层31相连。The polysilicon gate electrode 54 extends into the drift region and is connected to the oxide layer 31 .
具体的，specific,
所述高K介质槽结构设置在N型漂移区21中与P型阱区13和N型重掺杂区24相连接。The high-K dielectric trench structure is arranged in the N-type drift region 21 and connected with the P-type well region 13 and the N-type heavily doped region 24 .
具体的，specific,
所述N型重掺杂区24上端设置有漏端电极53。A drain terminal electrode 53 is disposed on the upper end of the N-type heavily doped region 24 .
具体的，specific,
所述漏端电极53和源端电极52通过钝化层34隔离。The drain terminal electrode 53 and the source terminal electrode 52 are separated by the passivation layer 34 .
具体的，specific,
所述高浓度N型条22设置在N型漂移区21中并且设计在高K介质槽41的下边，与高K介质槽41相连接。The high-concentration N-type strips 22 are arranged in the N-type drift region 21 and designed under the high-K dielectric groove 41 to connect with the high-K dielectric groove 41 .
具体的，specific,
所述衬底电极55设置在P型衬底11的下表面。The substrate electrode 55 is disposed on the lower surface of the P-type substrate 11 .
与现有技术相比，上述技术方案具有以下优点：Compared with the prior art, the above-mentioned technical solution has the following advantages:
本发明提供的一种高耐压低比导的高K功率器件，在漂移区21内引入了高K介质槽41，在高K介质槽41的下侧引入了高浓度N型条22。本发明与传统技术相比，即在器件的漂移区中引入高K介质槽相当于两个场板结构，辅助耗尽漂移区，提高器件耐压，提高漂移区浓度，降低器件的比导通电阻。在高K界面处引入高浓度N型条可以使器件在开态的时候提供低阻通道，进一步降低器件的比导通电阻，在关态时，减小了电离积分路径，提高器件的击穿电压，实现耐压和比导的折中，获得更高的功率优值FOM。使用深槽栅结构，在开态时积累电子，降低器件的比导通电阻。相对与低K介质槽结构，高K介质槽在工艺上具有更大的优势：（1）击穿电压随漂移区浓度范围变化不是很明显，工艺容差较大；（2）由于高K介质槽设计成浅而宽的槽型结构，在工艺填充时更容易实现。In the high-K power device with high withstand voltage and low specific conductance provided by the present invention, a high-K dielectric groove 41 is introduced into the drift region 21 , and a high-concentration N-type strip 22 is introduced under the high-K dielectric groove 41 . Compared with the traditional technology, the present invention introduces a high-K dielectric groove into the drift region of the device, which is equivalent to two field plate structures, assists in depleting the drift region, improves the withstand voltage of the device, increases the concentration of the drift region, and reduces the specific conduction of the device resistance. Introducing high-concentration N-type strips at the high-K interface can provide a low-resistance channel in the on-state of the device, further reducing the specific on-resistance of the device, and reducing the ionization integration path in the off-state, improving the breakdown of the device Voltage, achieve a compromise between withstand voltage and specific conductance, and obtain a higher power figure of merit FOM. Using a deep trench gate structure, electrons are accumulated in the on-state to reduce the specific on-resistance of the device. Compared with the low-K dielectric tank structure, the high-K dielectric tank has greater advantages in technology: (1) The breakdown voltage does not change significantly with the concentration range of the drift region, and the process tolerance is large; (2) Due to the high-K dielectric The groove is designed as a shallow and wide groove structure, which is easier to realize during process filling.
附图说明Description of drawings
图1 是常规横向高压功率器件结构剖面示意图；Figure 1 is a schematic cross-sectional view of a conventional lateral high-voltage power device structure;
图2 是本发明的高K介质槽低比导通电阻的横向高压器件结构剖面图；Fig. 2 is a cross-sectional view of the lateral high-voltage device structure of the high-K dielectric groove of the present invention with low specific on-resistance;
图3 是本发明的高K介质槽低比导通电阻的横向高压器件的关态原理示意图；Fig. 3 is a schematic diagram of the off-state principle of the lateral high-voltage device of the high-K dielectric groove and low specific on-resistance of the present invention;
图4 是本发明的高K介质槽低比导通电阻的横向高压器件的开态原理示意图；Fig. 4 is the schematic diagram of the on-state principle of the lateral high-voltage device with high-K dielectric groove and low specific on-resistance of the present invention;
图5 是本发明的高K介质槽低比导通电阻的横向高压器件和常规结构的横向电场对比图；Fig. 5 is a lateral electric field comparison diagram of a lateral high-voltage device with a high-K dielectric groove and a low specific on-resistance of the present invention and a conventional structure;
图6 是本发明的高K介质槽低比导通电阻的横向高压器件和常规结构的纵向电场对比图；Fig. 6 is a comparison diagram of the longitudinal electric field between the lateral high-voltage device of the present invention and the conventional structure of the high-K dielectric groove with low specific on-resistance;
图7 是本发明的高K介质槽低比导通电阻的横向高压器件和常规结构击穿时的等势线分布图；Fig. 7 is the distribution diagram of equipotential lines during the breakdown of the lateral high voltage device of the present invention with high K dielectric groove and low specific on-resistance and conventional structure;
图8 是本发明的浅槽栅结构的高K介质槽低比导通电阻的横向高压器件的结构图；Fig. 8 is a structural diagram of a lateral high-voltage device with a high-K dielectric trough and a low specific on-resistance of the shallow trench gate structure of the present invention;
图9 是本发明的中等槽栅结构的高K介质槽低比导通电阻的横向高压器件的结构图；Fig. 9 is a structural diagram of a lateral high-voltage device with a high-K dielectric groove and a low specific on-resistance of a medium groove gate structure of the present invention;
图10 是本发明的深槽栅结构的高K介质槽低比导通电阻的横向高压器件的结构图；Fig. 10 is a structural diagram of a lateral high-voltage device with a high-K dielectric trench and a low specific on-resistance of the deep trench gate structure of the present invention;
图11 是本发明的高K介质槽低比导通电阻的横向高压器件剖面图，其中第2条高浓度N型条25位于介质槽的右侧；Fig. 11 is a cross-sectional view of a lateral high-voltage device with a high-K dielectric groove and low specific on-resistance of the present invention, wherein the second high-concentration N-type strip 25 is located on the right side of the dielectric groove;
图12 是本发明的高K介质槽低比导通电阻的横向高压器件剖面图，在图2的基础上设计两个栅电极；Fig. 12 is a cross-sectional view of a lateral high-voltage device with a high-K dielectric groove and low specific on-resistance of the present invention, and two gate electrodes are designed on the basis of Fig. 2;
图13 是本发明的深槽栅结构的高K介质槽低比导通电阻的横向高压器件结图，埋氧层31设置为阶梯形状；FIG. 13 is a junction diagram of a lateral high-voltage device with a high-K dielectric trench and low specific on-resistance in a deep trench gate structure of the present invention, and the buried oxide layer 31 is set in a stepped shape;
图14 是本发明的深槽栅结构的高K介质槽低比导通电阻的横向高压器件结图，埋氧层31设置为双面阶梯形状；FIG. 14 is a junction diagram of a lateral high-voltage device with a high-K dielectric trench and low specific on-resistance in the deep trench gate structure of the present invention, and the buried oxide layer 31 is set in a double-sided ladder shape;
图15 是本发明的深槽栅结构的高K介质槽低比导通电阻的横向高压器件结图，埋氧层31设置为部分埋氧层结构；FIG. 15 is a junction diagram of a lateral high-voltage device with a high-K dielectric trench and low specific on-resistance in the deep trench gate structure of the present invention, and the buried oxide layer 31 is set as a partially buried oxide layer structure;
图16 是本发明的深槽栅结构的高K介质槽低比导通电阻的横向高压器件结图，埋氧层31设置为高K埋氧层，即42为高K材料；Fig. 16 is a junction diagram of a lateral high-voltage device with a high-K dielectric trench and low specific on-resistance of the deep trench gate structure of the present invention, and the buried oxide layer 31 is set as a high-K buried oxide layer, that is, 42 is a high-K material;
图17 是本发明的高K介质槽低比导通电阻的横向高压器件结构图，其栅电极槽栅结构，栅极在器件左边，并且栅氧物为高K材料，即42为高K材料；Figure 17 is a structural diagram of a lateral high-voltage device with a high-K dielectric groove and low specific on-resistance according to the present invention. Its gate electrode has a groove-gate structure, the gate is on the left side of the device, and the gate oxide is a high-K material, that is, 42 is a high-K material ;
图18 是本发明的高K介质槽低比导通电阻的横向高压器件结构图，其栅电极槽栅结构，栅极在器件中间，并且栅氧化物为高K材料，即42为高K材料；Figure 18 is a structural diagram of a lateral high-voltage device with a high-K dielectric groove and low specific on-resistance according to the present invention. Its gate electrode has a groove-gate structure, the gate is in the middle of the device, and the gate oxide is a high-K material, that is, 42 is a high-K material ;
图19 是本发明的高K介质槽低比导通电阻的横向高压器件应用到体硅器件中，其衬底材料P型体硅；Figure 19 shows the application of the high-K dielectric groove and low specific on-resistance lateral high-voltage device of the present invention to a bulk silicon device, and the substrate material is P-type bulk silicon;
图20 是本发明的高K介质槽低比导通电阻的横向高压器件应用到体硅器件中，其衬底材料P型体硅，槽栅延伸到P型衬底里面；Figure 20 shows the application of the high-K dielectric groove and low specific on-resistance lateral high-voltage device of the present invention to a bulk silicon device, the substrate material is P-type bulk silicon, and the groove gate extends into the P-type substrate;
图21 是本发明的高K介质槽低比导通电阻的横向高压器件应用到PMOS器件中，其N型漂移区21变为P型漂移区12；Figure 21 shows the application of the lateral high-voltage device with high-K dielectric groove and low specific on-resistance of the present invention to a PMOS device, and its N-type drift region 21 becomes a P-type drift region 12;
图22 是本发明的高K介质槽低比导通电阻的横向高压器件应用到LIGBT中，14为P型重掺杂,25为高浓度的N-Buffer区。Figure 22 shows the application of the lateral high-voltage device with high-K dielectric groove and low specific on-resistance of the present invention to LIGBT, 14 is P-type heavily doped, and 25 is a high-concentration N-Buffer region.
图23 是本发明的高K介质槽低比导通电阻的横向高压器件结构剖面图。Fig. 23 is a cross-sectional view of the structure of a lateral high-voltage device with a high-K dielectric trench and low specific on-resistance according to the present invention.
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