CN106684126A - Trench type transistor device structure and making method - Google Patents

Abstract

The present invention provides a device structure and manufacturing method of a trench type transistor. The structure includes a source region, a body region, a drift region and a drain region arranged in sequence from top to bottom, and perpendicular to the source region, body region, drift region and The trench-type gate region of the region and the drain region; wherein, the trench-type gate region includes polysilicon filled in the trench, a gate dielectric layer located between the inner wall of the trench and the polysilicon, and inserting the Conductive layer of metal inside polysilicon. The trench transistor device structure of the present invention forms a "sandwich" structure of oxide layer/polysilicon/metal conductive layer in the gate trench, and a metal with low resistivity replaces a part of polysilicon with relatively high resistivity, so that the gate resistance of the device Effectively reduce, thereby increasing the switching speed of the device.

Description

Structure and manufacturing method of a trench transistor device

technical field

The invention relates to the technical field of integrated circuits, in particular to a trench type transistor device structure and manufacturing method.

Background technique

For trench devices, gate resistance is an important parameter. During the switching process of the device, the transmission speed of the electrical signal is affected by the gate resistance. The greater the gate resistance, the greater the switching loss of the device and the slower the switching speed. At present, the gate of the traditional trench MOSFET transmits the electrical signal to the cell gate inside the chip through the metal connection trench polysilicon channel on the periphery of the chip. Due to the long transmission line and the high resistivity of the polysilicon channel, so The gate resistance of the trench type device is relatively large, and the switching speed of the device is relatively low. Trench MOSFET devices are often used in higher frequency applications, so people have made a lot of efforts to reduce gate resistance. Patents CN2035317U, CN101826551A, and CN103928512A change the device structure design, but the gates are all made of polysilicon with relatively high resistance, so there is a certain limit in the reduction of gate resistance.

Therefore, it is really necessary to provide a new structure and process to effectively reduce the gate resistance, thereby increasing the switching speed of the device.

Contents of the invention

In view of the prior art described above, the purpose of the present invention is to provide a structure and manufacturing method of a trench transistor device, which is used to solve the problem that the gate resistance of the trench transistor device in the prior art is relatively large and the device switching speed is relatively slow. low problem.

In order to achieve the above object and other related objects, the present invention provides a trench transistor device structure, including:

A source region, a body region, a drift region and a drain region arranged in sequence from top to bottom, and a trench gate region perpendicular to the source region, body region, drift region and drain region;

Wherein, the trench-type gate region includes polysilicon filled in the trench, a gate dielectric layer located between the inner wall of the trench and the polysilicon, and a metal conductive layer inserted into the polysilicon.

Optionally, the material of the metal conductive layer is a high melting point metal.

Optionally, the material of the metal conductive layer is tungsten, aluminum, aluminum silicon copper, aluminum copper, copper, or an alloy containing tungsten, aluminum, aluminum silicon copper, aluminum copper or copper.

Optionally, the trench-type transistor device structure includes a plurality of trench-type gate regions.

Optionally, the trench-type gate region is inserted vertically through the source region and the body region.

Optionally, the drain region is a heavily doped semiconductor layer of the first conductivity type, and the drift region is a lightly doped semiconductor layer of the first conductivity type epitaxially grown on the drain region.

Optionally, the source region is an ion-implanted heavily doped semiconductor layer of the first conductivity type, and the body region is an ion-implanted semiconductor layer of the second conductivity type.

Optionally, the device structure of the trench type transistor further includes a source electrode, a drain electrode and a gate electrode respectively connected to the source region, the drain region and the trench gate region, and the gate electrode is connected to the The metal conductive layer of the trench gate area is connected.

To achieve the above object and other related objects, the present invention also provides a method for manufacturing a trench type semiconductor device structure, comprising the following steps:

S1 providing a heavily doped semiconductor substrate of the first conductivity type, and growing an epitaxial layer of the lightly doped first conductivity type on the surface of the semiconductor substrate;

S2 forming an oxide layer on the epitaxial layer, and etching a trench;

S3 removing the oxide layer, and forming a gate dielectric layer on the inner wall of the trench;

S4 filling polysilicon in the trench;

S5 ion implantation and high temperature annealing to form the body region;

S6 ion implantation forms the source region;

S7 defines a contact hole above the trench by photolithography, performs polysilicon etching, and then fills a metal conductive material to form a metal conductive layer inserted into the polysilicon.

Optionally, in step S3, a sacrificial layer is formed first, and then the oxide layer and the sacrificial layer are removed by wet etching.

Optionally, in step S3, a gate oxide layer is formed by high temperature oxidation growth as the gate dielectric layer.

Further optionally, the gate oxide layer also covers the surface of the source region.

Optionally, in step S4, after filling the trench with polysilicon, dry etching is used to remove excess polysilicon material outside the trench.

Optionally, the manufacturing method further includes: forming a passivation layer covering the surface of the polysilicon and the source.

Optionally, the manufacturing method further includes: forming a source electrode, a drain electrode and a gate electrode electrically connected to the source region, the drain region and the metal conductive layer in the trench, respectively.

As mentioned above, the trench transistor device structure and manufacturing method of the present invention have the following beneficial effects:

The trench type transistor device structure and manufacturing method of the present invention, by adding a contact hole photolithography process, form a contact hole above the polysilicon gate, fill the metal conductive layer after etching the polysilicon, and form an oxide layer in the gate trench. Layer/polysilicon/metal conductive layer "sandwich" structure, the metal with low resistivity replaces a part of polysilicon with relatively high resistivity, which can effectively reduce the gate resistance of the device, thereby increasing the switching speed of the device.

Description of drawings

Fig. 1 shows a schematic diagram of the structure of a trench transistor device provided by the present invention.

FIG. 2 shows a schematic diagram of a fabrication method for the trench transistor device structure provided by the present invention.

3a-3h are schematic diagrams showing the fabrication process of the trench transistor device structure provided by the embodiment of the present invention.

Component designation description

100 drain area

100’ semiconductor substrate

200 Drift Zone

200’ epitaxial layer

201 oxide layer

300 trench gate

301 gate dielectric layer

301’ gate oxide

302 polysilicon

303 metal conductive layer

304 grid electrode

400 body area

500 source area

501 Source electrode

600 passivation layer

S1～S7 steps

detailed description

Embodiments of the present invention are described below through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific implementation modes, and various modifications or changes can be made to the details in this specification based on different viewpoints and applications without departing from the spirit of the present invention. It should be noted that, in the case of no conflict, the following embodiments and features in the embodiments can be combined with each other.

It should be noted that the diagrams provided in the following embodiments are only schematically illustrating the basic ideas of the present invention, and only the components related to the present invention are shown in the diagrams rather than the number, shape and shape of the components in actual implementation. Dimensional drawing, the type, quantity and proportion of each component can be changed arbitrarily during actual implementation, and the component layout type may also be more complicated.

Referring to Fig. 1, the present invention provides a trench type transistor device structure, including:

The source region 500, the body region 400, the drift region 200 and the drain region 100 arranged in order from top to bottom, and the trench type gate region perpendicular to the source region 500, the body region 400, the drift region 200 and the drain region 100 300;

Wherein, the trench gate region 300 includes polysilicon 302 filled in the trench, a gate dielectric layer 301 located between the inner wall of the trench and the polysilicon 302, and a metal conductive layer inserted inside the polysilicon 302 303.

Specifically, the material of the metal conductive layer 303 can be selected from high melting point metals, such as tungsten, aluminum, aluminum silicon copper, aluminum copper, copper and other metals and alloys containing these components. The resistivity of the metal conductive layer 303 may be 1.75E-6-5.5E-6 ohm·cm. The metal conductive layer 303 is inserted into the polysilicon 302 to a depth of 0.5-2 microns.

In some embodiments of the present invention, the trench transistor device structure may include a plurality of trench gate regions 300 , and a plurality of source regions 500 and body regions corresponding to the plurality of trench gate regions 300 District 400.

In some embodiments of the present invention, the trench gate region 300 is inserted vertically through the source region 500 and the body region 400 . The bottom of the trench gate region 300 may be in contact with the drift region 200 .

In some embodiments of the present invention, the drain region 100 may be a heavily doped semiconductor layer of the first conductivity type, such as n+ type; the drift region 200 may be a lightly doped semiconductor layer epitaxially grown on the drain region 100 heterogeneous semiconductor layer of the first conductivity type, such as n-type.

In some embodiments of the present invention, the source region 500 may be an ion-implanted heavily doped semiconductor layer of the first conductivity type, such as n+ type; the body region 400 may be an ion-implanted semiconductor layer of the second conductivity type , such as the p-type body region.

The structure, material, manufacturing process, principle, etc. of the source region, drain region, body region, and drift region of the trench transistor device are known to those skilled in the art, so they will not be repeated here. The source in the device structure of the present invention The regions, drain regions, body regions, and drift regions may adopt any suitable structures, materials, and fabrication techniques, which are not limited in the present invention.

In some embodiments of the present invention, the device structure of the trench type transistor may further include a source electrode 501 and a drain electrode respectively connected to the source region 500, the drain region 100 and the trench type gate region 300 (the accompanying drawings not shown) and the gate electrode 304. The gate electrode 304 may be connected to the metal conductive layer 303 inserted inside the polysilicon 302 .

The present invention changes the traditional gate oxide layer/polysilicon gate structure in the trench into a "sandwich" structure of oxide layer/polysilicon/metal conductive layer, because a part of polysilicon with relatively high resistivity is replaced by a metal with low resistivity, which can The gate resistance of the device is effectively reduced, thereby increasing the switching speed of the device.

Please refer to FIG. 2, the present invention also provides a method for manufacturing the above-mentioned trench transistor device structure, including the following steps:

S1 providing a heavily doped semiconductor substrate of the first conductivity type, and growing an epitaxial layer of the lightly doped first conductivity type on the surface of the semiconductor substrate;

S2 forming an oxide layer on the epitaxial layer, and etching a trench;

S3 removing the oxide layer, and forming a gate dielectric layer on the inner wall of the trench;

S4 filling polysilicon in the trench;

S5 ion implantation and high temperature annealing to form the body region;

S6 ion implantation forms the source region;

S7 defines a contact hole above the trench by photolithography, performs polysilicon etching, and then fills a metal conductive material to form a metal conductive layer inserted into the polysilicon.

The above manufacturing method will be described in detail below through specific examples.

First, as shown in FIG. 3a, a heavily doped semiconductor substrate 100' of the first conductivity type is provided as a drain region, and an epitaxial layer 200' of the lightly doped first conductivity type is grown on the surface of the semiconductor substrate 100', The lower half of the epitaxial layer 200' will serve as a drift region.

Then, as shown in FIG. 3b, an oxide layer 201 with a thickness of about 2000-10000 angstroms is formed on the epitaxial layer 200' by chemical vapor deposition or similar methods, and then the trench photolithography plate defines the trench positions, The device trenches are then formed by dry etching. The width of the trenches may be 0.2-2 microns.

Subsequently, the oxide layer 201 is removed, and a gate dielectric layer is formed on the inner wall of the trench. Preferably, a sacrificial layer of 500-1250 Angstroms may be formed first, and the sacrificial layer is used to remove damage on the silicon surface during trench etching. The oxide layer 201 and the sacrificial layer are removed by wet etching, and then a gate oxide layer 301' of 150-1000 Angstroms is formed as the gate dielectric layer by high temperature oxidation growth. The gate oxide layer 301' also covers the surface of the epitaxial layer 200' which will serve as the source region.

Next, as shown in FIG. 3 c , polysilicon 302 is filled in the trench by chemical vapor deposition or similar methods. The thickness of the filled polysilicon 302 may be 0.5-2 microns. In specific operation, after filling the trench with polysilicon material, dry etching can be used to remove excess polysilicon material outside the trench, and the etching will stop on the surface of the gate oxide layer 301'.

Then, as shown in FIG. 3d, the body region 400 of the device is formed by high temperature annealing after ion implantation.

After the body region 400 is formed, as shown in FIG. 3 e , ion implantation is performed to form the source region 500 . Specifically, a source region implantation photolithography plate can be used to define and implant the source of the device in the cell region of the device to form a heavily doped (eg, n+) device source region 500 .

Next, as shown in FIG. 3f, a contact hole is defined above the trench by photolithography and polysilicon etching is performed, and then a metal conductive material is filled to form a metal conductive layer 303 inserted into the polysilicon 302, thereby forming an oxide layer. /polysilicon/metal conductive layer "sandwich" structure. Wherein, the material of the metal conductive layer 303 can be selected from high melting point metals, such as tungsten, aluminum, aluminum silicon copper, aluminum copper, copper and other metals and alloys containing these components. The depth at which the metal conductive layer 303 is inserted into the polysilicon 302 , that is, the etched depth of the polysilicon 302 may be 0.5-2 microns, and the diameter of the defined contact hole may be 0.2-2 microns.

Afterwards, a passivation layer 600 covering the surface of the polysilicon 302 and the surface of the source region 500 may also be formed by chemical vapor deposition or similar methods. The passivation layer 600 may have a thickness of 0.2-1 micron. Then, as shown in Figure 3g, the source contact hole of the device is defined using a contact hole photolithography plate.

Finally, a source electrode 501 , a drain electrode (not shown in the drawings) and a gate electrode 304 electrically connected to the source region 500 , the drain region 100 and the metal conductive layer 303 in the trench are formed. Specifically, physical vapor deposition or a similar method can be used to form a 0.8-2 micron thick conductive material, and the front and back sides of the silicon wafer will be deposited. Then, the gate electrode and source electrode of the device are defined by using a metal photolithography plate, such as Figure 3h.

In summary, the device structure and manufacturing method of the trench type transistor of the present invention, by adding a contact hole photolithography process, a contact hole is formed above the polysilicon gate, and the metal conductive layer is filled after the polysilicon is etched, and the gate The "sandwich" structure of oxide layer/polysilicon/metal conductive layer is formed in the trench. Since the polysilicon in the trench can be etched very deep, and then filled with a highly conductive metal conductive layer, the gate resistance is greatly reduced and the gate resistance is improved. The switching speed of the trench device is improved, making the device more suitable for high-frequency working environment. Therefore, the present invention effectively overcomes various shortcomings in the prior art and has high industrial application value.

The above-mentioned embodiments only illustrate the principles and effects of the present invention, but are not intended to limit the present invention. Anyone skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or changes made by those skilled in the art without departing from the spirit and technical ideas disclosed in the present invention should still be covered by the claims of the present invention.

Claims (15)

1. A trench transistor device structure, characterized in that, comprising: A source region, a body region, a drift region and a drain region arranged in sequence from top to bottom, and a trench gate region perpendicular to the source region, body region, drift region and drain region; Wherein, the trench-type gate region includes polysilicon filled in the trench, a gate dielectric layer located between the inner wall of the trench and the polysilicon, and a metal conductive layer inserted into the polysilicon. 2. The trench transistor device structure according to claim 1, characterized in that: the material of the metal conductive layer is a high melting point metal. 3. The trench transistor device structure according to claim 1, characterized in that: the material of the metal conductive layer is tungsten, aluminum, aluminum-silicon-copper, aluminum-copper, copper, or contains tungsten, aluminum, aluminum-silicon-copper , aluminum copper or copper alloys. 4 . The trench transistor device structure according to claim 1 , wherein the trench transistor device structure comprises a plurality of trench gate regions. 5 . The trench transistor device structure according to claim 1 , wherein the trench gate region is inserted vertically through the source region and the body region. 6. The trench transistor device structure according to claim 1, wherein the drain region is a heavily doped semiconductor layer of the first conductivity type, and the drift region is epitaxially grown on the drain region Lightly doping the first conductivity type semiconductor layer. 7. The trench transistor device structure according to claim 1, wherein the source region is an ion-implanted heavily doped semiconductor layer of the first conductivity type, and the body region is an ion-implanted second conductivity type semiconductor layer. type semiconductor layer. 8. The trench type transistor device structure according to claim 1, characterized in that: the trench type transistor device structure further comprises source electrodes respectively connected to the source region, the drain region and the trench type gate region, A drain electrode and a gate electrode, the gate electrode is connected to the metal conductive layer of the trench gate region. 9. A method for manufacturing a trench type transistor device structure, characterized in that the method comprises the following steps: S1 providing a heavily doped semiconductor substrate of the first conductivity type, and growing an epitaxial layer of the lightly doped first conductivity type on the surface of the semiconductor substrate; S2 forming an oxide layer on the epitaxial layer, and etching a trench; S3 removing the oxide layer, and forming a gate dielectric layer on the inner wall of the trench; S4 filling polysilicon in the trench; S5 ion implantation and high temperature annealing to form the body region; S6 ion implantation forms the source region; S7 defines a contact hole above the trench by photolithography, performs polysilicon etching, and then fills a metal conductive material to form a metal conductive layer inserted into the polysilicon. 10 . The manufacturing method of the trench transistor device structure according to claim 9 , wherein in step S3 , a sacrificial layer is formed first, and then the oxide layer and the sacrificial layer are removed by wet etching. 11 . 11. The manufacturing method of the trench transistor device structure according to claim 9, characterized in that in step S3, a gate oxide layer is formed by high temperature oxidation growth as the gate dielectric layer. 12 . The method for fabricating a trench transistor device structure according to claim 11 , wherein the gate oxide layer also covers the surface of the source region. 13 . 13. The manufacturing method of the trench transistor device structure according to claim 9, characterized in that: in step S4, after filling the trench with polysilicon, dry etching is used to remove excess polysilicon outside the trench Material. 14. The manufacturing method of the trench transistor device structure according to claim 9, characterized in that: the manufacturing method further comprises: forming a passivation layer covering the surface of the polysilicon and the source. 15. The manufacturing method of the trench type transistor device structure according to claim 9, characterized in that: the manufacturing method further comprises: forming a conductive layer electrically connected to the source region, the drain region and the metal conductive layer in the trench respectively. connected source, drain and gate electrodes.