CN106610816A - Avoidance method for conflict between instruction sets in RISC-CPU and avoidance system thereof - Google Patents

Abstract

The invention discloses a method and system for avoiding conflicts between instruction sets in a RISC-CPU, comprising the following steps: Step 1: Determine the type of conflict according to the data dependency between different instruction sets in the RISC-CPU; Step 2: For the current instruction, judge whether it needs to access the "register file" or "memory", if so, proceed to step three, otherwise, continue to analyze the next instruction; Window", look for "related instructions" and judge whether there are "related instructions". If so, go to step 4; The choice of using specific strategies to resolve data conflicts while ensuring pipeline throughput efficiency.

Description

Method and system for avoiding conflicts between instruction sets in a RISC-CPU

technical field

The invention relates to the technical field of computer processing, in particular to a method and system for avoiding conflicts between instruction sets in a RISC-CPU.

Background technique

Because the design of embedded RISC-CPU (from CPU hardware instruction set selection and instruction custom design, to the design of corresponding compiler) is very important.

The relevant technologies are as follows: the application number is CN200810191060, and the applicant is "Shiyifa (Beijing) Semiconductor Research and Development Co., Ltd." for the invention patent application "reducing instruction conflicts in processors". Instruction issue) stage, select two kinds of instructions, and send them to the subsequent parallel functional unit, to see which instruction has no conflict, and then arbitrate one of the instructions. This method is used to select a conflict-free command from a multi-issue command window.

The invention patent application of Intel Corporation with the patent application number CN200710087737 "Technology for Executing Memory Disambiguation" provides a solution for conflict avoidance between adjacent memory access instructions, but does not involve the interior of other related instruction sets Or the definition of coherence windows between instruction sets and the avoidance of conflicts between coherent instructions.

Xidian University's application number is CN201310054280 for an invention patent application "a method for designing an assembler based on a special instruction set processor with super-long instruction words". Write-after-write (W-A-W) conflicts with write-after-read (W-A-R) caused by out-of-order execution.

Intel Corporation's invention patent application "Technology for Performing Memory Disambiguation" with the patent application number "CN200710087737" provides a solution for conflict avoidance between adjacent memory access instructions, but does not involve other related instruction sets The definition of coherent windows between internal or instruction sets and the avoidance of conflicts between coherent instructions are different from the number of pipeline stages of the embedded RISC-CPU involved in this patent, and there is no mention of the instruction-based Set prototype CPU to full instruction set CPU hardware engineering design strategy.

It can be seen that none of the prior art provides a method for solving RAW coherent conflicts from the perspective of the overall instruction system, nor does it propose a CPU hardware design engineering strategy from the CPU prototype of the local minimum instruction set to the entire instruction set.

Contents of the invention

In order to solve the deficiencies in the prior art, the present invention discloses a method and system for avoiding conflicts between instruction sets in RISC-CPU, a mechanism for solving conflicts between instruction sets, and provides a RISC-CPU for reading Intelligent control of hardware devices for write conflict resolution.

To achieve the above object, the specific scheme of the present invention is as follows:

A method for avoiding conflicts between instruction sets in a RISC-CPU, comprising the following steps:

Step 1: Determine the type of conflict according to the data dependencies between different instruction sets in the RISC-CPU;

Step 2: For the current instruction, determine whether it needs to access the "register file" or "memory", if so, proceed to step 3, otherwise, continue to analyze the next instruction;

Step 3: Define the "coherent window" for the current command, search for the "coherent command" in the "coherent window", and judge whether there is a "coherent command", if so, go to step 4, otherwise, judge that there is no read-write conflict ;

Step 4: According to the type of conflict between instruction sets, select a conflict method, and use a specific strategy to resolve data conflicts while ensuring pipeline throughput efficiency.

Further, in step 1, statistically analyze and classify the architecture, instruction set and pipeline segments of RISC-CPU, and divide all instruction sets into data processing instruction set, memory access instruction set, branch instruction set and immediate number instruction set .

Further, in step 1, after obtaining the four instruction sets, statistically analyze the conflicts between the instruction sets, traverse and classify the types of read-write conflicts between various instruction sets, and obtain the existing instruction data dependent on the introduction Conflict: The following "related instructions" read old register data or overwrite new write data that has not been read, that is, the data dependency of the original instruction sequence is destroyed, causing functional errors; and the original instruction pipeline is interrupted, These include reduced instruction throughput due to pipeline freezing or pipeline insertion of NOP instructions.

Further, the classification of conflict types specifically includes: data processing, memory access, and immediate instruction sets within and between them.

Further, in step 3, the definition of "coherent window": For superscalar instruction processing, out-of-order execution of instructions does not need to be considered. For the current instruction, if it needs to write to a certain register, it needs to be in the following In the window: if the current instruction operates on a specific register in the register file or a certain location in the memory; push from the current instruction to the following instruction flow, from fetching the instruction until submitting the instruction sequence involved in the result of the current instruction.

Further, in step 3, the definition of "coherent instruction": based on the already defined "coherent window", regardless of the out-of-order execution of instructions, for the "current instruction", if it requires a certain register or memory To write to a certain offset address, search from the current instruction to the following instruction within the scope of the "coherent window", and also need to write or read one or more instructions to the "current instruction". These exist data Dependent instructions may have data read and write conflicts, causing pipeline interruptions and reducing instruction throughput efficiency.

Further, within the "coherence window", the conflict resolution method includes: (1) directly feed the result of the logical operation before the current command is submitted to the calculation unit of the following coherent command, without waiting until the current command has been submitted , and then feed the final result to the arithmetic unit of the following instruction. (2) A delayed version is performed on the operation result of the coherent instruction following the current instruction, and the output of the delayed version is used as a register backup resource for reading and writing conflict resolution.

Further, in step 4, the conflict method specifically includes:

(1) If the data is before the final calculation result is submitted, the intermediate calculation data is fed forward in advance, and the intermediate calculation data is fed forward in advance, that is, it does not need to go to the final submission stage, and is directly fed to the input terminal of the next instruction;

(2), the delayed version of the data is fed forward before the final calculation result is submitted;

(3), the pipeline delay version of the intermediate operation result coexists with the original operation version. In the pipeline segment of the next coherent instruction, an additional delay version register is added to delay one or several beats, while retaining the registers in the original normal pipeline segment. Version;

(4), the original pipeline does not freeze strategy;

(5), the method of inserting the NOP instruction is not used.

Further, specifically, RAW conflict resolution between the ADD and XOR instructions: feed the operation result of the ADD instruction into the XOR as input in advance, without waiting for the ADD instruction to be submitted before executing;

RAW conflict resolution between STORE and LOAD instructions: The result of STORE is used as the address calculation input of LOAD, and the delayed register is added in front of the LOAD instruction;

RAW conflict resolution between ADD and STORE instructions: the operation result of the ADD instruction is directly fed to the next level as the offset address, and the address address of the STORE command is calculated;

RAW conflict resolution between LOAD and ADD instructions: the result of the LOAD instruction is directly used as the input of ADD, and the intermediate result of ADD is delayed by one beat as the offset address of DMEM access.

Further, in step 1, after classifying all read-write conflicts that may exist, store them in the local file table: conflict retrieval table, including index and conflict type; using superscalar technology, take out multiple Instructions are stored in the instruction cache window, and the "coherent window" definition and the search for "coherent instructions" are performed in advance; by defining the "coherent window" and "coherent instructions", the search for read and write conflicts of the instruction stream is performed. If there are instructions For the coherent conflicts between them, by searching for the conflict types between the instruction sets that have been pre-stored locally, the conflicts can be quickly avoided in advance.

A system for avoiding conflicts between instruction sets in a RISC-CPU, including a conflict resolution control unit, which is applied in a RISC-CPU, and the conflict resolution control unit is used to implement: after classifying all possible read-write conflicts, Stored in the local file table: conflict retrieval table, including index and conflict type; using superscalar technology, multiple instructions are taken out from the instruction memory, stored in the instruction cache window, and the "coherence window" definition and "coherence window" are defined in advance Instructions" search; by defining "coherent window" and "coherent instructions", search for read-write conflicts of instruction streams. Conflict type, to quickly avoid conflicts in advance.

Beneficial effects of the present invention:

For the instruction set of the current RISC-CPU, the present invention performs statistical analysis and classification of the conflicts between the instruction sets in advance for the types of conflicts existing between the instructions, and then controls the "conflicts" based on the result of searching for conflicting "coherent instructions". Find and solve" unit to achieve the purpose of smooth pipeline inside the coherent window.

The present invention provides an effective strategy for solving conflicts between instruction sets in RISC-CPU design; defines the instruction "coherent window" and "coherent instruction" to solve the "coherent instruction" read/write, write/ Read, write/write conflicts. This paper uses RAW conflict resolution as an example to analyze conflicts between several major instruction sets. This engineering method quantifies and resolves instruction conflicts. By adding read and write conflicts to locate and resolve hardware units, it can effectively Avoid instruction conflicts between different instruction sets of RISC-CPU, and at the same time, improve pipeline throughput efficiency.

Description of drawings

Figure 1 is the classification of instruction sets involved in RISC-CPU;

Figure 2 is a schematic diagram of "coherent window" and "coherent instruction";

Fig. 3 is the background and workflow of the present invention;

Fig. 4 is the added hardware unit of conflict location and resolution;

Figure 5 is the RAW conflict resolution of ADD and XOR instructions;

Figure 6 is the RAW conflict resolution of STORE and LOAD instructions;

Figure 7 is the RAW conflict resolution of ADD and STORE instructions;

Figure 8 is the RAW conflict resolution of LOAD and ADD instructions.

detailed description:

The present invention is described in detail below in conjunction with accompanying drawing:

As shown in FIG. 1, the present invention proposes an effective method for resolving CPU instruction conflicts. The present invention divides all instructions in the design into 4 categories (data processing instructions, branch Branch instructions, immediate data instructions, and storage access instructions), extracts representative instruction subsets from each type of instruction, and solves the internal problems of the instruction subsets respectively. Conflicts with RAW (write-after-read) direct data coherence between them. Pre-statistically analyze all potential RAW conflicts, and then locate and resolve conflicts to achieve a smooth pipeline.

The RISC-CPU design proposed by the present invention divides all instruction sets into data processing (Data-Processing), memory access (STORE/LOAD), branch (Branch), and immediate data (Immediate) four instruction types. For each type of instruction (except branch Branch) and between instruction classes, RAW (write-after-read) conflict resolution is used as an example to explain. There are several RAW conflicts (data processing, memory access, immediate instruction set Internal and between them), coherent conflict resolution caused by data dependencies is required.

Definition of "coherent window": For superscalar instruction processing, it is not necessary to consider the out-of-order execution of instructions. For the current instruction, if it needs to write to a certain register, it needs to be within the following window: Operate on a specific register in the register file or a certain location in the memory; push from the current instruction to the instruction flow below, from fetching the instruction until submitting the instruction sequence involved in the result of the current instruction.

Definition of "coherent instruction": Based on the previously defined "coherence window", regardless of the out-of-order execution of instructions, for the "current instruction", if it needs to write to a certain register or a certain offset address of the memory If input is entered, within the scope of the "coherence window", search from the current instruction to the following instructions, and also need to write or read one or more instructions to the "current instruction". These instructions with data dependencies may have data read and write conflicts, causing pipeline interruption and reducing instruction throughput efficiency (CPI).

For each case, "coherence window" and "coherence instruction" are given respectively. Examples of coherent windows are shown in FIG. 2 , such as ADD (thick solid line) and XOR (thin dashed line) instructions. An example of a coherent instruction is shown in FIG. 2 . For example, the coherent instruction of the ADD instruction corresponds to the XOR and STORE instructions. For all similar instruction sets, for example: for the subset of data processing instructions: ADD and XOR instructions, as shown in Tables 1 and 2, RAW conflicts are resolved respectively, as shown in Figure 3. For example: For memory access instructions (LOAD/STORE), as shown in Tables 3, 4, 5, and 6:

Table 1 Instruction format of Data-Processing instruction instruction set

Table 2 Representative of data processing instruction set (ADD addition instruction, XOR exclusive OR instruction)

Table 3, memory-to-register (LOAD) instruction format

Table 4, representatives of the subset of LOAD instruction classes

LDR R _D ←[R _S ] LDR R _D ,[R _S ]

Table 5, Register-to-Memory (STORE) Instruction Format

Table 6, representatives of the subset of STORE instruction classes

STR R _D → [R _S ] STR R _D ,[R _S ]

RAW conflicts are resolved separately, as shown in FIG. 5 .

For all heterogeneous instruction sets, RAW conflicts are resolved respectively, as shown in Figures 6, 7, and 8.

For the rest of the instruction sets, immediate data instructions, branch instructions, RAW conflicts between them are no longer analyzed.

Located in the "coherence window", conflict resolution methods include: (1) Feed the logical operation results before the current command submission stage to the calculation unit of the following coherent command, instead of waiting until the current command has been submitted, and then send The final result is fed to the arithmetic unit of the following instruction. (2) A delayed version is performed on the operation result of the coherent instruction following the current instruction, and the output of the delayed version is used as a register backup resource for reading and writing conflict resolution.

This design only analyzes the RAW conflicts between data processing and memory access instructions. Conflicts and avoidances between other instruction sets and other WAR/WAWs will not be introduced with specific examples.

In conjunction with Fig. 3 and Fig. 4, the instruction conflict resolution of the present invention is described. In RISC-CPU hardware design, there may be data read and write dependencies between adjacent instructions, that is, access to the same register in the register file or the same offset address of the memory has read and write order conflicts, resulting in the pipeline must be stopped , reduce efficiency: RAW/WAR/WAR. For the design of RISC-CPU, the conflict between the instruction sets will cause the interruption of the pipeline and reduce the efficiency of instruction throughput. According to the classic 5-stage pipeline of MIPS: stage 1-fetch, stage 2-decode, stage 3-execute, stage 4-memory access, for internal Memory As far as it is concerned, it includes load/store two categories), phase 5-write back. 5-stage pipeline (Write Back, the operation result is written back to the Register-bank in the RISC-CPU). In the classic MIPS architecture, the longest instruction occupies 5 pipeline segments (such as accessing the memory STORE instruction, and then writing it back to the register file); ordinary non-storage access data operation instructions occupy 4 pipeline segments (such as ADD addition instruction, The result of the final addition is written into a certain register of the register file, the ADD instruction does not go through the memory access stage), and some instructions are executed in the decoding stage (such as the jump JMP instruction); the conditional branch instruction, due to its need Changing the order of the instruction stream causes the non-sequential execution of the instructions; it can be seen that in the design of RISC-CPU, due to the different pipeline segments occupied by different instruction sets, and the randomness of the instruction arrangement is very strong, the same register in the register file Or there may be a data dependency conflict in the read/write of a certain offset address of the memory.

The present invention defines the "coherence window" for the current instruction by analyzing the conflicts caused by the possible register data read and write dependencies between different instruction sets in the classic MIPS architecture, and searches for the "coherence window" for the current instruction from the "coherence window". "Coherent instructions", by analyzing the data dependencies between different instruction sets in the RISC-CPU in advance, determine the conflict type and avoid the pipeline efficiency: (1) The following "related instructions" read old register data or overwrite The newly written data that has not been read, that is, the data dependency of the original instruction sequence is destroyed, causing a functional error; (2) and the original instruction pipeline is interrupted (including due to the pipeline being frozen or the pipeline inserting the NOP instruction) Instruction throughput is reduced), once the pipeline is frozen or blindly delayed as a whole, it will cause the weakening of the advantage of pipeline and reduce the efficiency of instruction throughput.

In the present invention, the analyzed example uses the following strategies to resolve data conflicts while ensuring pipeline throughput efficiency: (1) before the final calculation result is submitted, the intermediate calculation data is fed forward in advance; (2) the data is before the final calculation result is submitted (3), the delay version of the intermediate operation result coexists with the original operation version; (4), the original pipeline does not freeze the strategy; (5), does not use: the method of inserting the NOP instruction. For example: for the (1) method: the intermediate operation data is fed forward in advance (that is, it does not need to go to the final submission stage), and it is directly fed into the input of the next instruction; for the (3) method: in the next coherent In the pipeline section of the instruction, an additional delayed version register (delayed by one or several beats) is added, while the original register version in the normal pipeline section is retained.

For the current RISC-CPU instruction set, for the types of conflicts between the instructions, the statistical analysis and classification of the conflicts between the instruction sets are carried out in advance, and then the results of the search for the conflict "related instructions" are used to control the "conflict search and "Solution" unit to achieve the goal of smooth pipeline inside the coherent window. Figures 4 and 6 are the advance feed-forward mechanism using the intermediate calculation results; Figures 5 and 7 are the delayed version methods using the calculation results. The current existing method is the NOP mechanism, which will delay the pipeline. This method is no longer used in this patent. At the same time, this patent does not use the method of freezing the pipeline, and the delayed version of this patent retains the original At the same time, for the classification results of the pre-known coherent instruction conflicts, the pipeline register backs up the delayed version, so as to solve the local instruction conflicts inside the "coherence window", and at the same time, it will not destroy the original normal version of the pipeline segment data transmission. In this patent, it is necessary to make full use of various methods such as data feedforward and delayed version to reach the inside of the coherent window and the pipeline is smooth. In this patent, the conflict resolution of instructions is systematically managed from statistical classification to positioning resolution. At the same time, the patent conflict resolution framework can also absorb new command resolution technologies to make the entire command conflict resolution system more complete.

Explanation of Figure 1: Figure 1 is the conflict resolution between several instruction sets (data processing, immediate data, branch, storage access).

Explanation of Figure 2: Figure 2 shows the "coherent window" for the current ADD instruction and the current XOR instruction; and for the ADD instruction, it gives the "coherent instructions" with data read and write conflicts: XOR, STORE , both of these instructions are related instructions of the ADD instruction. Explanation of Fig. 3: The overall flow of the method for resolving instruction conflicts based on the "coherent window" and "coherent instruction" of the present invention is given. This method can be added to the hard core of the RISC-CPU as an intelligent positioning and resolution module of instruction read-write conflicts in the RISC-CPU. Of course, after the architecture, number of pipeline segments, instruction set types, and instruction formats of the currently designed RISC-CPU are determined, it is necessary to develop the RISC-CPU hard core. Traditional methods do not quantify and resolve conflicts from a systematic perspective.

This patent first conducts pre-statistical analysis on the read-write conflicts between different types or the same type of instructions, and strictly classifies the conflicts, and stores all possible read-write conflicts in the local file table after classification : conflict retrieval table (index, conflict type); using superscalar technology, take out multiple instructions from the instruction memory, store them in the instruction cache window, and carry out the "coherent window" definition and the search for "coherent instructions" in advance; through Strictly define "coherent window" and "coherent instruction" to search for conflicts between reading and writing of instruction streams. If there are coherent conflicts between instructions, search for conflict types between instruction sets that have been pre-stored locally. Fast early avoidance of conflicts (via added conflict resolution control unit). Tables 1, 2, and 3 in the invention list several instructions. Table 1 is the data format and instruction mnemonic of the data processing instruction. Table 2 and Table 3 are the data format and instruction helper of the memory access LOAD/STORE instruction. mark;

Figures 5 and 7 are feedforward in advance before the result of the preceding instruction is submitted, and Figures 6 and 8 are the output of the delayed version of the intermediate operation results of subsequent coherent instructions. Both methods are to prevent pipeline interruption. The output of different delay beats of coherent instructions needs to use some additional registers. These registers are delayed versions of calculation results, which do not destroy the original pipeline results. For other conflict resolution techniques, this invention can be extended into the technical framework of the present invention.

If the current instruction does not access the register file or memory, the next instruction is analyzed, and the "coherent window" slides down; if there is no "coherent instruction" in the "coherent window", there is no read-write conflict, and the analysis ends.

Explanation of Figure 5: The operation result of the ADD instruction is fed into the XOR as an input in advance, and there is no need to wait for the ADD instruction to be submitted before execution, so as to ensure the smoothness of the pipeline.

Explanation of Figure 6: The result of STORE is used as the input of the address calculation of LOAD. By adding a delayed register in front of the LOAD instruction, the smoothness of the pipeline is ensured.

Explanation of Figure 7: The operation result of the ADD instruction is directly fed to the next stage as the offset address, and the address address of the STORE command is calculated to ensure the smoothness of the pipeline.

Explanation of Figure 8: The storage result of the LOAD instruction is directly sent to the following related instructions: the result of the LOAD instruction is directly used as the input of ADD, and the version of the intermediate result of ADD delayed by one beat is used as the offset address of DMEM access to ensure the smoothness of the pipeline.

The present invention can realize instruction conflict search and instruction avoidance by using "coherent window" and "coherent instruction". It is an effective and simple strategy for resolving conflicts between multiple instruction sets, and is beneficial for common conflict resolution of RISC-CPU hardware instructions.

The unit of intelligent conflict finding and resolution is added in RISC-CPU design, which can be applied to superscalar CPU design. The present invention combines technologies such as data advance, no freezing of pipelines, no insertion of NOP instructions, delayed feedforward or multi-shot delayed versions based on intermediate calculation results, etc. to achieve smooth pipeline technology.

Although the specific implementation of the present invention has been described above in conjunction with the accompanying drawings, it does not limit the protection scope of the present invention. Those skilled in the art should understand that on the basis of the technical solution of the present invention, those skilled in the art do not need to pay creative work Various modifications or variations that can be made are still within the protection scope of the present invention.

Claims (10)

1. a method for avoiding conflict between instruction sets in a RISC-CPU, characterized in that, comprising the following steps: Step 1: Determine the type of conflict according to the data dependencies between different instruction sets in the RISC-CPU; Step 2: For the current instruction, determine whether it needs to access the "register file" or "memory", if so, proceed to step 3, otherwise, continue to analyze the next instruction; Step 3: Define the "coherent window" for the current command, search for the "coherent command" in the "coherent window", and judge whether there is a "coherent command", if so, go to step 4, otherwise, judge that there is no read-write conflict ; Step 4: According to the type of conflict between instruction sets, select a conflict method, and use a specific strategy to resolve data conflicts while ensuring pipeline throughput efficiency. 2. the avoidance method of conflict between instruction sets in a kind of RISC-CPU as claimed in claim 1, it is characterized in that, in step 1, carry out statistical analysis and merge at the structure of RISC-CPU, instruction set and pipeline section Class, all instruction sets are divided into data processing instruction set, memory access instruction set, branch instruction set and immediate number instruction set. 3. the avoidance method of conflict between instruction sets in a kind of RISC-CPU as claimed in claim 2, it is characterized in that, in step 1, after obtaining four kinds of instruction sets, the conflict between statistical analysis instruction sets, Traverse and classify the types of read-write conflicts between various instruction sets, and obtain the conflicts introduced by the existing instruction data dependence: the following "related instructions" read the old register data or overwrite the new write data that has not been read , that is, the data dependency of the original instruction sequence is destroyed, causing a functional error; and the original instruction pipeline is interrupted, including the instruction throughput reduction caused by the pipeline being frozen or the pipeline inserting a NOP instruction. 4. the avoidance method of conflict between instruction sets in a kind of RISC-CPU as claimed in claim 1 or 3, it is characterized in that, the classification of conflict type is specifically: data processing, memory access, immediate data instruction set interior and between them; Preferably, the RAW conflict between ADD and XOR instructions is resolved: the operation result of the ADD instruction is fed into XOR as an input in advance, and it is not necessary to wait until the ADD instruction is submitted before execution; RAW conflict resolution between STORE and LOAD instructions: The result of STORE is used as the address calculation input of LOAD, and the delayed register is added in front of the LOAD instruction; RAW conflict resolution between ADD and STORE instructions: the operation result of the ADD instruction is directly fed to the next level as the offset address, and the address address of the STORE command is calculated; RAW conflict resolution between LOAD and ADD instructions: the result of the LOAD instruction is directly used as the input of ADD, and the version of the intermediate result of ADD delayed by one beat is used as the offset address of DM EM access. 5. the method for avoiding conflicts between instruction sets in a kind of RISC-CPU as claimed in claim 1, it is characterized in that, in step 3, " coherent window " definition: for superscalar instruction processing, need not consider instruction Out-of-order execution, for the current instruction, if it needs to write to a certain register, it needs to be in the following window: if the current instruction operates on a specific register in the register file or a certain location in the memory; from the current The instruction is pushed to the following instruction flow, from fetching the instruction to submitting the instruction sequence involved in the result of the current instruction. 6. The avoidance method of conflict between instruction sets in a kind of RISC-CPU as claimed in claim 5, it is characterized in that, in step 3, " coherent instruction " definition: based on the " coherent window " that has defined, not Considering the out-of-order execution of instructions, for the "current instruction", if it needs to write to a certain register or a certain offset address of the memory, within the scope of the "coherent window", search from the current instruction to the following instruction , It also needs to write or read one or more instructions for the "current instruction". These instructions with data dependencies may have data read and write conflicts, causing pipeline interruption and reducing instruction throughput efficiency. 7. the avoidance method of conflict between instruction sets in a kind of RISC-CPU as claimed in claim 1, it is characterized in that, be positioned at " coherence window ", the method for conflict resolution comprises: (1) present order submission stage The result of the previous logic operation is directly fed into the operation unit of the following related instruction, instead of waiting until the current instruction has been submitted, and then the final result is fed into the operation unit of the following instruction. (2) A delayed version is performed on the operation result of the coherent instruction following the current instruction, and the output of the delayed version is used as a register backup resource for reading and writing conflict resolution. 8. the avoidance method of conflict between instruction sets in a kind of RISC-CPU as claimed in claim 1, it is characterized in that, in step 4, conflict method specifically comprises: (1) If the data is before the final calculation result is submitted, the intermediate calculation data is fed forward in advance, and the intermediate calculation data is fed forward in advance, that is, it does not need to go to the final submission stage, and is directly fed to the input terminal of the next instruction; (2), the delayed version of the data is fed forward before the final calculation result is submitted; (3), the pipeline delay version of the intermediate operation result coexists with the original operation version. In the pipeline segment of the next coherent instruction, an additional delay version register is added to delay one or several beats, while retaining the registers in the original normal pipeline segment. Version; (4), the original pipeline does not freeze strategy; (5), the method of inserting the NOP instruction is not used. 9. the method for avoiding conflicts between instruction sets in a kind of RISC-CPU as claimed in claim 1, it is characterized in that, in step 1, after all read-write conflicts that may exist are classified, be stored in local file table Middle: Conflict retrieval table, including index and conflict type; using superscalar technology, fetch multiple instructions from the instruction memory, store them in the instruction cache window, and define the "coherent window" and search for "coherent instructions" in advance; By defining "coherent window" and "coherent instruction", search for read and write conflicts of instruction streams. If there is a coherent conflict between instructions, search for the conflict type between the instruction sets that have been pre-stored locally. rapid early avoidance. 10. A system for avoiding conflicts between instruction sets in a RISC-CPU, characterized in that it includes a conflict resolution control unit, which is applied in a RISC-CPU, and the conflict resolution control unit is used to realize: all possible reads After write conflicts are classified, they are stored in the local file table: conflict retrieval table, including index and conflict type; using superscalar technology, multiple instructions are taken out from the instruction memory, stored in the instruction cache window, and "coherent" is performed in advance Window” definition and search for “coherent instructions”; by defining “coherent windows” and “coherent instructions”, search for read-write conflicts of instruction streams, if there are coherent conflicts between instructions, it will be pre-stored locally by searching The types of conflicts between different instruction sets are used to quickly avoid conflicts in advance.