CN106601297A - Apparatus and method for improving threshold voltage distribution of non-volatile memory - Google Patents

Abstract

Methods and associated apparatus for controlling voltage threshold distributions corresponding to a non-volatile memory device whose memory cells perform a function are provided. In one embodiment, a method is provided. The method may include providing the non-volatile storage device. The device includes one or more strings, each string including a plurality of memory cells including a first memory cell and a second memory cell. The method also includes performing a function of the non-volatile memory device by applying a first function voltage to the first memory cell and applying a second function voltage to the second memory cell. The first functional voltage is different from the second functional voltage.

Description

Apparatus and method for improving valve voltage distribution of non-volatile memory

technical field

Embodiments of the present invention relate to semiconductor devices, and more particularly, methods for improving programming threshold voltage (Vt) distribution and operations of semiconductor memory devices.

Background technique

Semiconductor devices are typically classified as volatile semiconductor devices (requiring power to maintain storage of data) or non-volatile semiconductor devices (retaining data even when power is removed). Non-volatile semiconductor devices are, for example, flash memory devices, which can generally be classified into NOR or NAND flash memory devices. Such flash memory devices may have memory cells or layers stacked on top of each other in a 3D architecture. When faster programming and erasing speeds are required, 3D NAND flash memory is typically used, partly because its serialized structure allows programming and erasing operations to be performed on the entire string of memory cells . In vertical NAND strings, the layers have different diameters due to non-standard etch angles.

As with 3D NAND flash memory associated with circular memory cells, the diameter difference includes different programming performance, which traditionally results in a wider programming threshold voltage (Vt) distribution. When the diameter of the memory cell is larger, the corresponding programming time is also longer. In this regard, challenges presented by large diameters may, for example, be like insufficient programming efficiency in terms of programming time. In addition, when a string includes memory cells of different diameters, the programming time of the string will be difficult to control. Therefore, how to improve the distribution of the programming valve voltage of the 3D NAND device, thereby improving (for example, reducing) the programming time, is one of the topics that the industry is currently working on.

Contents of the invention

Embodiments of the present invention propose improved semiconductor device operations, in particular, methods for controlling the programming valve voltage distribution corresponding to a non-volatile memory device, such as 3D NAND flash memory.

In one aspect of the present invention, a method for controlling a programming valve voltage distribution corresponding to a non-volatile memory device is provided. In an embodiment, the method includes providing a non-volatile memory device. The non-volatile storage device includes one or more strings, each string includes a plurality of storage units, and the storage units include a first storage unit and a second storage unit. The method further includes performing a function of the nonvolatile memory device by applying a first function voltage to the first memory unit and applying a second function voltage to the second memory unit. The first functional voltage is different from the second functional voltage.

Another aspect of the present invention is to provide a non-volatile memory device with controlled programming valve voltage distribution. The non-volatile memory device includes a plurality of memory cells along a string. The string includes a channel area. Each memory cell includes a word line at the string. The memory cells include a first memory cell with a first word line, and a second memory cell with a second word line. By applying a first function voltage to the first memory cell through the first word line and a second function voltage to the second memory cell through the second word line, the first memory cell and the second memory cell perform a function. on it. The first functional voltage is different from the second functional voltage.

In order to have a better understanding of the above-mentioned and other aspects of the present invention, the preferred embodiments are specifically cited below, together with the accompanying drawings, and are described in detail as follows:

Description of drawings

FIG. 1A is a perspective view of an example string of an example non-volatile memory device according to an embodiment of the present invention.

Figure 1B is a cross-sectional view of the string shown in Figure 1A.

2A and 2B illustrate the operation of a portion of a string conventionally and the resulting wide variation in the valve voltage of the memory cells along the string.

3A and 3B illustrate exemplary operation of a portion of a string, and a corresponding improvement (reduction) in valve voltage variation of memory cells along the string, in accordance with embodiments of the present invention.

4A and 4B illustrate examples of programming algorithms according to different embodiments of the present invention.

FIG. 5 shows an example of an improved programmed valve voltage distribution diagram based on a group according to an embodiment of the present invention.

FIG. 6 is a flowchart illustrating a procedure for controlling voltage distribution according to an embodiment of the present invention.

【Symbol Description】

100, 200: string

10a, 10b, 10c, 10d, WL1~WLN: word lines

θ: exterior angle

R _TOP : Top radius

R _BOT : Bottom Radius

D _A , D _B , D _C , D _D : channel width

50: Passage area

40: tunneling layer

30: capture layer

20: Barrier or dielectric layer

210, 220, 230: storage unit

PV: program verifythreshold (program verification threshold)

EV: erase verifythreshold (erase verification threshold)

V _{WL_l} ～V _{WL_n} : Applied voltage corresponding to WL1～WLN word lines

V _g : programming voltage

ΔV _g : Program voltage change

5, 6: Variation of valve voltage

P: point

400: Procedure

410, 420, 430, 440, 450: steps

detailed description

Herein, some embodiments of the present invention are described in detail with reference to the accompanying drawings, but not all embodiments are shown in the drawings. Indeed, these inventions can use many different variations and are not limited to the examples herein. Rather, the present invention provides these embodiments to meet the statutory requirements of the application. The same reference symbols are used in the drawings to designate the same or similar elements.

Although specific terms are employed herein, they are used in a generic and descriptive sense only and not for purposes of limitation. Unless defined otherwise, all terms used herein including technical and scientific terms have the same meaning as commonly understood by one of ordinary skill in the art of the invention. It will be further understood that terms such as those defined in commonly used dictionaries should be interpreted to have meanings as commonly understood by those of ordinary skill in the art. It will be further understood that terms such as those defined in commonly used dictionaries should be interpreted to have meanings consistent with the relevant art and the context of the present invention. Unless expressly so defined in this disclosure, these generally used terms are not to be interpreted in an idealized or overly formal sense.

The "gate structure" mentioned herein refers to elements in a semiconductor device, such as a memory device. Non-limiting examples of storage devices include flash memory devices (eg, NAND flash memory devices). Erasable Programmable Read-Only Memory (EPROM) and Electrically Erasable Programmable Read-Only Memory (EEPROM) are non-limiting examples of flash memory devices. The gate structure of the present invention may be a collection of gate structures operable in a memory device, or a subset of one or more elements of the gate structure.

A "non-volatile memory device" as used herein refers to a semiconductor device that can store information even after power is removed. Non-volatile memory devices include, but are not limited to, Mask Read-Only Memory, Programmable Read-Only Memory, Erasable Programmable ROM, Electrically Erasable Programmable Read-Only Memory (Electrically Erasable Programmable Read-Only Memory), and flash memory, such as NAND and NOR flash memory.

The "substrate" mentioned herein may include any underlying material on which devices, circuits, epitaxial layers or semiconductors may be formed. In general, a substrate may be used to define layers underlying a semiconductor device, or to form a base layer of a semiconductor device. The substrate may include one or any combination of silicon, doped silicon, germanium, silicon germanium, semiconductor compound, or other semiconductor materials.

The gate structures (eg, nonvolatile memory devices) and methods of the present invention improve the programming threshold voltage distribution of nonvolatile memory devices for random access, such as 3D NAND flash memory. For this reason, the programming speed of the nonvolatile memory device will increase based on the non-uniform programming voltage.

The present invention is concerned with a variety of functions including programming (eg PGM), erasing (eg ERS), reading (eg READ) or any other function that applies a voltage to multiple memory cells on the same string. The present invention can be implemented in different types of devices and/or storage units, including 3D NAND flash memory, other non-volatile storage devices (such as 3D NOR, 3D ROM, 2D NAND or 2D NOR), MOS storage in regular configuration unit or any other device for voltage control in a regular configuration. For illustration purposes, this article provides an example of programming 3D NAND flash memory. Based on the disclosure provided herein, those skilled in the art can understand how to apply the present invention to other functions and other types of devices.

1A and 1B illustrate a part of a non-volatile storage device such as 3D NAND flash memory. FIG. 1B is a cross-sectional view drawn along the line AA” of FIG. 1A as a tangent. The portion of the illustrated nonvolatile memory device includes a vertical string 100 including a plurality of memory cells. The illustrated The string 100 includes four memory cells, but in different embodiments, the string 100 can include more than four or less than four memory cells based on the application. Generally speaking, the string 100 usually includes word lines 10a, 10b , 10c, and 10d (for example, corresponding to the word lines of each memory cell) wrap around the cylindrical portion around it. It should be noted that although the string 100 is generally cylindrical, it is actually slightly conical. Etching the string The process of multiple layers makes this string slightly deviate from the standard. Therefore, the outer angle θ is less than 90 °. This makes the radius R _TOP of the top of the string larger than the radius R _BOT of the bottom of the string. Therefore, the channel width of each memory cell in the string 100 The channel widths of adjacent memory cells are different (eg, D _A >DB > _DC > _{D D )} .

In general, the NAND string 100 includes a tunneling layer 40 surrounding the channel region 50 , a trapping layer 30 and a barrier or dielectric layer 20 . In various embodiments, the tunneling layer 40 may be composed of oxide and have a thickness of about 5 nm. In some embodiments. The blocking or dielectric layer 20 may be composed of oxide and have a thickness of about 7 nm. Channel region 50 may comprise polysilicon material or other suitable materials. Word lines (eg, 10a, 10b, 10c, and 10d) surround barrier or dielectric layer 20 such that there is one word line per memory cell. The word lines (eg, 10a, 10b, 10c, and 10d) may be composed of polysilicon material, metal, or other suitable materials.

2A and 2B illustrate the normal operation of a NAND string 200 with three memory cells 210 , 220 and 230 . In this example, the channel diameter or width W1 of the memory cell 210 is 100 nm, the channel diameter or width W2 of the memory cell 220 is 90 nm, and the channel diameter or width W3 of the memory cell 230 is 80 nm. During the execution of the programming function, a uniform voltage V _g =20V is applied to each memory cell via its respective word line. When the programming function is performed, the programming valve voltage distribution is widened due to the speed difference between the memory cells due to the difference in the channel diameter or width of the memory cells. Therefore, according to this example, when a uniform voltage of 20V is applied, because of the difference in width of the three memory cells 210, 220, 230, it should be noted that although the memory cell string 200 is generally cylindrical, it is actually slightly conical. The process of etching multiple layers of the string causes the string to deviate slightly from standard. Therefore, the external angle α is smaller than 90°. The programming voltage results in a wide programming valve voltage variation over time5. As shown in the figure, when the channel width of a memory cell is larger, the programming time of the memory cell is longer. On the contrary, when the channel width of a memory cell is smaller, the programming time of the memory cell is shorter. As shown in FIG. 2B, at a time of 1×10 ⁻⁵ seconds, the programming valve voltage variation 5 of the three memory cells is about 1˜1.5 V. Due to the difference in channel width among the three memory cells, the variation among the three memory cells is about 20% of the valve voltage of each memory cell.

The present invention proposes a method to reduce the variation of the valve voltage of the memory cells along the string, thereby making the valve voltage distribution tighter. 3A and 3B illustrate an example of this method. 3A shows an example in which string 200 includes memory cells 210, 220, and 230, wherein, in this example, memory cell 210 has a channel diameter or width of 100 nm, memory cell 220 has a channel diameter or width of 90 nm, and memory cell 230 has a channel diameter of 90 nm. The channel diameter or width is 80nm. A non-uniform voltage is applied instead of a uniform voltage of 20V to each memory cell via the corresponding word line. Therefore, the word line of the storage unit 210 applies a programming voltage V _g =20V to the storage unit 210, the word line of the storage unit 220 applies a programming voltage V _g =19.5V to the storage unit 220, and the word line of the storage unit 230 applies a programming voltage V g =19.5V to the storage unit 230. A programming voltage V _g =19V is applied. Therefore, a program voltage applied to a memory cell having a smaller channel diameter or width is smaller than a program voltage applied to a memory cell having a larger channel diameter or width. FIG. 3B shows the variation of the valve voltage of the three memory cells as a function of time when operated with a non-uniform programming voltage. Especially, when the time is 1×10 ⁻⁵ seconds, the variation 6 of the valve voltage of the three memory cells is the smallest. For this reason, applying a non-uniform voltage can reduce the variation of the programming valve voltage among the memory cells and reduce the programming time.

In various embodiments, the programming voltage applied to each memory cell in a string via the corresponding word line can be used to minimize the variation in the valve voltage of the memory cells in the string. For example, the programming voltage, _Vg , for each memory cell in the string can be different. In other embodiments, the string can be divided into two segments or groups, where a first programming voltage is applied to memory cells whose channel diameter or width is equal to or greater than a threshold, and a second programming voltage is applied to the channel Storage cells with a diameter or width smaller than this threshold. In this case, the first programming voltage may be greater than the second programming voltage. In various embodiments, multiple threshold widths can be used to divide the string into sectors or groups, where the memory cells in each sector or group are provided with a specific programming voltage.

In various embodiments, the difference in programming voltages applied to two memory cells may be based on the difference in channel width between the two memory cells. In other embodiments, the programming voltage difference between two adjacent memory cells may be predetermined rather than based on the channel width difference between the two adjacent memory cells. For example, in some embodiments, the programming voltage difference between any two pairs of adjacent memory cells is the same. This refers to a regular programming voltage distribution. Therefore, in the above example, the difference between the programming voltages applied to the memory cells 210 , 220 is the same as the difference between the programming voltages applied to the memory cells 220 , 230 . In other embodiments, the programming voltages between the first pair of adjacent memory cells and the second pair of adjacent memory cells may be different. This refers to an irregular programming voltage distribution. For example, the difference between the programming voltages applied to the memory cells 210 , 220 is different from the difference between the programming voltages applied to the memory cells 220 , 230 .

One of ordinary skill in the art will appreciate that the programming voltage profile applied to a particular string of memory cells can be used to minimize the variation in the valve voltage of the string of memory cells, taking into account other operating constraints. For example, the same programming voltage distribution can be applied to each string comprising semiconductor devices. In another example, a device may be limited to provide k (k is a positive integer) different programming voltages along each string, but a string may include n (n is a positive integer) different memory cells.

4A and 4B illustrate two examples of programming voltage distributions applied to n memory cells in a string, where [Delta] _Vg is a programming voltage variation. For example, in the example shown in FIG. 3A and FIG. 3B , the difference between the programming voltages applied to the memory cells 210 and 220 and the difference ΔV _g between the programming voltages applied to the memory cells 220 and 230 are both 0.5V. As noted above, in various embodiments, the programming voltage distribution may be regular (e.g., the _ΔVg between any two adjacent memory cells or groups may be constant), or the programming voltage distribution may be irregular (e.g., ΔV _g may be different between adjacent memory cells or groups).

FIG. 5 shows an example string including N (N is a positive integer) memory cells. Each memory cell corresponds to a word line, as shown labeled WL1, WL2, WL3, . . . , WLN. The N storage units are divided into n (n is a positive integer less than or equal to N) groups. In some embodiments, the plurality of memory cells in each group are identical. In other embodiments, some groups may include different numbers of memory cells among them. However, each group includes at least one memory cell. Each group is applied with a specific programming voltage. For example, group 1 may include 5 memory cells with the largest channel width among all memory cells along the string, and group 2 may include 4 memory cells with the smallest channel width among all memory cells along the string. The first programming voltage can be applied to the memory cells of the group 1 through the corresponding word lines of the memory cells of the group 1, and the second programming voltage can be applied to the memory cells of the group 2 through the corresponding word lines of the memory cells of the group 1. 2 on these storage units. In this example, the first programming voltage is greater than the second programming voltage.

The right graph of FIG. 5 shows the effect of the group number of n groups of memory cells along the string on the valve voltage distribution, where each group is applied with a specific programming voltage and each group is applied with a different specific programming voltage. For example, all the memory cells in the group 1 are applied with the first programming voltage, and all the memory cells in the group 2 are applied with the second programming voltage, and the first programming voltage and the second programming voltage are not equal. When the number of n groups of memory cells along a string is small, dividing the memory cells along the string into n+1 groups can significantly reduce the valve voltage compared to dividing the memory cells along the string into n groups The width of the distribution. However, after point P, increasing the group number only moderately reduces the width of the valve voltage distribution. Thus, in one embodiment, the number of groups used will coincide with point P such that the valve voltage distribution is reduced and the effect of applying non-uniform programming voltages on other performance characteristics of the memory device is minimized.

FIG. 6 is a flowchart of a process 400 for controlling the programming valve voltage distribution corresponding to a non-volatile memory device according to an embodiment of the present invention. The process 400 begins with step 410, providing a storage device (such as a 3D NAND flash storage device). A memory device may include one or more strings, each string including a plurality of memory cells, such as shown in FIGS. 1A and 1B . Each memory cell corresponds to a portion of the channel area of the string. This portion of the channel area has a specific channel width associated therewith. In step 420, the number of groups used in each string is determined. For example, in one embodiment, an analysis similar to that shown in FIG. 5 can be done to determine the optimal number of groups for each group. In other embodiments, operating constraints or other constraints may be used to determine the number of groups in each string. At step 430, the memory cells in the string are allocated into the groups. For example, the first five memory cells in a string can be assigned to bank 1, the next five memory cells along the string can be assigned to bank 2, and so on.

In step 440, a programming voltage distribution to be applied to each group is determined. In various embodiments, this step may include analyzing the channel widths of the memory cells in the group (e.g., comparing the average channel width of the memory cells of group 1 to the average channel width of the memory cells of group 2 to determine the programming between group 1 and group 2). Voltage difference). In various embodiments, the memory cells of the string are not grouped and the programming voltage for each memory cell is determined. In some embodiments, the distribution of programming voltages may be determined based on operating constraints and/or other constraints.

At step 450, programming functions are implemented. For example, a programming voltage may be applied to each memory cell via a corresponding word line to program the memory cells of a string. The program voltage applied to each memory cell may be based on a predetermined distribution of program voltages. In effect, the programming voltage profile is applied to the memory cells along the string such that the programming voltage applied to a memory cell on the string is different from the programming voltage applied to a second memory cell on the string, thereby reducing the programming voltage along the string. The valve voltage variation of the memory cells of the string. Those of ordinary skill in the technical field of the present invention should understand that, as mentioned above, the present method can be used for various functions, including programming, erasing, reading, and other functions of applying voltage to the memory cells of the same string. Furthermore, it should be understood that the present invention is applicable to various types of semiconductor devices including non-volatile memory devices such as 3D NOR, 3D ROM, 2D NAND, 3D NAND, 2D NOR, MOS memory cells in regular configuration, Or any other device for voltage control in a regular configuration.

In different embodiments, steps 420-440 may be performed once for a device. Next, at each time a function (eg, PGM, ERS, Read, etc.) is performed, a predetermined voltage profile is applied as described herein to control the variation in the valve voltage of the memory cells along each string. For example, a predetermined voltage distribution can be accessed and applied instead of performing steps 420-440 to determine the voltage distribution each time a function is to be performed.

One aspect of the present invention is to provide a non-volatile storage device programmed according to a method of the present invention.

Various modifications and other embodiments of the inventions presented herein will come to mind to one of ordinary skill in the art having the benefit of the teachings presented in the foregoing descriptions and the associated drawings. Therefore, it is to be understood that the inventions are not to be limited to the specific embodiments disclosed and that modifications and other embodiments are to be included within the scope of the following claims. Furthermore, while the above description and associated drawings describe embodiments in the context of certain illustrative combinations of elements and/or functions, it should be understood that different combinations of elements and/or functions may be made without departing from the claims below. provided by alternative embodiments under the category of . Here, for example, combinations of elements and/or functions other than those detailed above are also contemplated as may be presented in some of the following claims. Although specific terms are employed herein, they are used in a generic and descriptive sense only and not for purposes of limitation.

In summary, although the present invention has been disclosed as above with preferred embodiments, it is not intended to limit the present invention. Those skilled in the art to which the present invention belongs may make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention should be determined by what is defined by the claims.

Claims (10)

1. a kind of method that control is distributed corresponding to a threshold voltage of Nonvolatile memory devices, its feature It is, including：

The Nonvolatile memory devices are provided, the Nonvolatile memory devices are gone here and there including one or more, respectively The string includes multiple memory element, and those memory element are deposited including one first memory element and one second Storage unit；And

Apply one first function voltage to first memory element and one is applied to second memory element Second function voltage, to perform a function of the Nonvolatile memory devices, the first function voltage with The second function voltage is different.

2. method according to claim 1, wherein first memory element includes wide by one first One passage area of degree definition, second memory element includes the channel region defined by one second width Domain, first width is different with second width.

3. method according to claim 2, wherein first width are more than second width, should First function voltage is more than the second function voltage.

4. method according to claim 1, wherein those memory element are divided into multiple groups, Respectively the group includes an at least memory element and at least group including multiple memory element, those Group includes one first group and one second group, and first group includes first memory element, Second group includes second memory element, and the execution of the wherein function is included in first group Each memory element apply the first function voltage, and each memory element in second group is applied Plus the second function voltage.

5. method according to claim 1, wherein the first function voltage by be associated with this One first wordline of one memory element applies to first memory element, and the second function voltage is by closing One second wordline for being coupled to second memory element applies to second memory element.

6. method according to claim 1, wherein those memory element include that one the 3rd storage is single Unit, the execution of the function includes applying one the 3rd function voltage, the 3rd work(to the 3rd memory element Energy voltage is identical with the second function voltage.

7. method according to claim 1, wherein the first function voltage and second function electricity Pressure is consistent with a predetermined function voltage's distribiuting.

8. a kind of Nonvolatile memory devices, it is characterised in that include：

Along a string of multiple memory element, wherein：

The string includes a passage area,

Respectively the memory element includes being arranged on the wordline at the string,

Those memory element include one first memory element with one first wordline, and including one the One second memory element of two wordline,

First memory element and the second memory element by one first function voltage via this first Wordline is to the applying of first memory element and one second function voltage via second wordline to this The applying of the second memory element, performs a function thereon, and

The first function voltage is different with the second function voltage.

9. Nonvolatile memory devices according to claim 8, the wherein passage area are to should A part for first memory element is defined by a first passage width, and the passage area is to second depositing A part for storage unit is defined by a second channel width, and the first passage width is more than the second channel Width, the first function voltage is more than the second function voltage.

10. Nonvolatile memory devices according to claim 8, wherein those memory element quilts Be divided into multiple groups, respectively the group include an at least memory element and including multiple memory element extremely A few group, those groups include one first group and one second group, and first group includes should First memory element, second group includes second memory element, and the execution of the wherein function includes Apply the first function voltage to each memory element in first group, and in second group Each memory element apply the second function voltage.