CN106533646B - Clock Data Recovery System in Sequencer/Deserializer - Google Patents
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Abstract
序列器/解序列器中的时钟数据恢复系统。该时钟数据恢复系统包括：一连续时间线性均衡器，产生第一均衡信号；加总器，迭加该第一均衡信号与反馈均衡信号，并产生迭加信号；第一误差切割器，根据时钟信号以及第一切割电压来切割该迭加信号并产生第一误差信号；第二误差切割器，根据该时钟信号以及第二切割电压来切割该迭加信号并产生第二误差信号；数据切割器，根据该时钟信号以及第三切割电压来切割该迭加信号并产生数据信号；时钟数据恢复电路产生该时钟信号；适应性滤波器，接收该数据信号与该第一误差信号，并据以产生参考电压与决策反馈均衡系数组；以及决策反馈均衡器，接收该数据信号与该决策反馈均衡系数组，并产生该反馈均衡信号。
A clock data recovery system in a sequencer/deserializer. The clock data recovery system includes: a continuous time linear equalizer, generating a first equalization signal; a summer, superimposing the first equalization signal and a feedback equalization signal to generate a superimposed signal; a first error cutter, cutting the superimposed signal according to a clock signal and a first cutting voltage to generate a first error signal; a second error cutter, cutting the superimposed signal according to the clock signal and a second cutting voltage to generate a second error signal; a data cutter, cutting the superimposed signal according to the clock signal and a third cutting voltage to generate a data signal; a clock data recovery circuit to generate the clock signal; an adaptive filter, receiving the data signal and the first error signal, and generating a reference voltage and a decision feedback equalization coefficient group accordingly; and a decision feedback equalizer, receiving the data signal and the decision feedback equalization coefficient group, and generating the feedback equalization signal.
Description
Technical field
The present invention relates in a kind of serial device/solution sequence device (Serializer/Deserializer, abbreviation Serdes)
Circuit, and the clock data recovery system in particular to a kind of serial device/solution sequence device (Serdes).
Background technique
Electronic circuit (such as chip, crystal grain, integrated circuit) is the most important hardware foundation of advanced information society；Different
Electronic circuit available channel (channel) connects into interconnection system, with via Channel Exchange signal (such as information, data, message,
Order and/or grouping etc.), allow different electronic circuit can mutually coordinated running, play the comprehensive function of addition.But, lead to
The characteristic in road itself also will affect the quality of signal contact transmission.In general, channel is low-pass nature, therefore suppression signal can be subtracted
In high frequency section, lead to distorted signals (distortion)；For example, when an electronic circuit as transmitting terminal will be through
When the signal of one square-wave waveform being transmitted to the electronic circuit of a receiving end by channel, the signal waveform that receiving end receives can be
The one slow waveform for rising slow drop has been unable to maintain that the liter edge and drop edge of square-wave waveform.Received in the signal waveform,
Vernier (pre-cursor) before its slow ascending part point can be considered one, the slow peak value risen can be considered a main cursor, and by the slow drop of peak value
Part then can be considered one after vernier (post-cursor).Distorted signals interferes (ISI, inter- between further resulting in symbol
Symbol interference), the quality of signal transmission is influenced, such as say it is to improve bit error rate.
In order to compensate the influence caused by passage, filtering mechanism and equalizer set can be respectively set in transmitting terminal and receiving terminal
System.For example, the filtering mechanism of transmitting terminal (transmitter, abbreviation Tx) may include a pre- reinforcing filter (pre-
Emphasis filter) to strengthen the high frequency section for emitting end signal；The equalizer set of receiving end (receiver, abbreviation Rx)
System then may include a continuous time linear equalizer (continuous time linear equalizer, abbreviation CTLE) and one
Decision feedback equalizer (decision feedback equalizer, abbreviation DFE).When transmitting terminal passes a signal to be passed
When sending to receiving end, transmitting end filter can be filtered according to multiple filter factors for signal to be passed, then will be believed after filtering
Number driving is to channel；After the signal that receiving end receiving channel transmits, the signal received can be carried out according to multiple equalizing coefficients
Equilibrium treatment, then by taking also its content and/or other information (such as clock) for carrying in signal after equalization.
Fig. 1 is please referred to, depicted is known array device/solution sequence device (Serdes) schematic diagram.In the electricity of transmitting terminal Tx
In sub-circuit, strengthens filter (pre-emphasis filter) 102 in advance and receive data-signal (data signal) S and generate
The data-signal Sw of filtering.Wherein, strengthen the size (increase for the high frequency section that filter 102 improves in data-signal S in advance
The magnitude of higher frequencies) and become the data-signal Sw filtered.
Later, the data-signal Sw of filtering is sent to the other end via one end of channel (channel) 104 and becomes and receive
Signal Sx and the electronic circuit for inputting receiving end Rx.In the electronic circuit of receiving end Rx, including clock data recovery system
(clock data recovering system) 110, to rebuild data-signal S.
Clock data recovery system 110 includes: data sampler (data sampler) 113, edge sampler (edge
Sampler) 115,117, decision feedback equalizer clock data recovery circuit (clock data recovering circuit)
(decision feedback equalizer) 119 and summer (adder) 111.
Substantially, the reception signal Sx on the other end in channel 104 can input clock data recovery system 110.Aggregation
Device 111 by feedback equalization signal (feedback equalizing signal) Sf that decision feedback equalizer 119 generates with connect
Collection of letters Sx generates superposition signal (superposed signal) Sz after being added up.
Data sampler 113 samples superposition signal Sz according to data clock dCLK and generates data sampling signal
(sampled data signal)Sd.Furthermore edge sampler 115 samples superposition signal Sz according to edge clock eCLK simultaneously
Generate edge sampled signal (sampled edged signal) Sedg.
In addition, clock data recovery circuit 117 receives sampled data signal Sd and edge sampled signal Sedg and generates
Data clock dCLK and edge clock eCLK.Decision feedback equalizer 119 receives sampled data signal Sd and generates feedback
Weigh signal Sf.
Substantially, the clock data recovery system 110 of Fig. 1 is that data and its data are carried out to superposition signal Sz along (data
Edge sampling), and data clock dCLK and edge clock eCLK is generated using clock data recovery circuit 117.It is such
Clock data recovery system 110, clock data recovery circuit 117 needs to generate the data clock dCLK of double data rate
And edge clock eCLK, excessively to sample (over sampling) superposition signal Sz.Furthermore data clock dCLK and
Phase difference between edge clock eCLK is 180 degree.
According to above explanation, need to utilize spring spring phase detectors (bang-bang in clock data recovery circuit 117
Phase detector), for receiving data sampling signal Sd and edge sampled signal Sedg, and phase is generated accordingly and is updated
Phase of the information (phase update information) to adjust data clock dCLK and edge clock eCLK.
, it is clear that known array device/solution sequence device is not particularly suited for the data transmission system of high speed.For example, false
If the data rate of data-signal S is 16Gbps, clock data recovery circuit 117 needs to generate the data for being up to 8GHz rate
Clock dCLK and edge clock eCLK could obtain the information of clock phase difference in such a way that positive negative edge samples, and then rebuild
Data-signal S.
Summary of the invention
An object of the present invention is to propose a kind of clock data recovery system, comprising: a continuous time linear equalizer,
It receives signal and generates one first equalizing signal；One summer, receives first equalizing signal and a feedback equalization is believed
Number, and generate a superposition signal；One first error cutter cuts this according to a clock signal and one first killer voltage
Superposition signal simultaneously generates a first error signal；One second error cutter, according to the clock signal and one second cutting electricity
It presses to cut the superposition signal and generate one second error signal；One data slicer, according to the clock signal and a third
Killer voltage come cut the superposition signal and generate a data-signal；One clock data recovery circuit, receive the data-signal with
Second error signal, and the clock signal is generated accordingly to the data slicer, the first error cutter and second mistake
Poor cutter；One adaptive filter receives the data-signal and the first error signal, and generates a reference voltage accordingly extremely
The first error cutter, and a decision feedback equalization coefficient sets are generated, wherein the reference voltage is equal to the first cutting electricity
Pressure；And a decision feedback equalizer, the data-signal and the decision feedback equalization coefficient sets are received, and generate the feedback accordingly
Equalizing signal is to the summer.
More preferably understand to have to above-mentioned and other aspect of the invention, preferred embodiment is cited below particularly, and cooperates attached
Figure, is described in detail below.
Detailed description of the invention
Fig. 1 depicted is known array device/solution sequence device (Serdes) schematic diagram.
The influence that signal is transmitted in the channel of Fig. 2 citing signal interconnection system.
It is interfered between Fig. 3 citing signal symbol.
Fig. 4 show the schematic diagram of 1 symbol of Xiang Yingyi logic.
Depicted serial device/solution sequence device the clock data recovery system for first embodiment of the invention of Fig. 5 A is illustrated
Figure.
Depicted coupling effect (coupling effect) schematic diagram between signal in first embodiment of Fig. 5 B.
Depicted serial device/solution sequence device the clock data recovery system for second embodiment of the invention of Fig. 6 A is illustrated
Figure.
Depicted uncoupling effect (decoupling effect) signal between signal in second embodiment of Fig. 6 B
Figure.
[symbol description]
102: strengthening filter in advance
104: channel
110: clock data recovery system
111: summer
113: data sampler
115: edge sampler
117: clock data recovery circuit
119: decision feedback equalizer
204: channel
500,600: clock data recovery system
510,610: continuous time linear equalizer
520,620: summer
530,630: data slicer
540,640,645: error cutter
550,650: clock data recovery circuit
560,660: adaptive filter
570,670: decision feedback equalizer
Specific embodiment
The influence that schematic channel transmits signal referring to FIG. 2, it is illustrated.In Fig. 2, a transmitting terminal Tx is through a channel
204 and be connected to a receiving end Rx, when transmitting terminal Tx will send the data-signal Sw of a filtering to receiving end, the data of filtering
Signal Sw can be formed via the propagation in channel 204 receives signal Sx, is received by receiving end Rx.In the example in figure 2, filtering
Data-signal Sw carries 1 symbol of logic in time point t0 with the square wave for continuing a period UI.As caused by channel 204
A slow waveform for rising slow drop can be presented in wave distortion, the square wave in the data-signal Sw of filtering in receiving signal Sx.It is received
Sampling of the Rx to signal Sx is received is held, 1 symbol of logic can be corresponded to the peak value sampling Sx [k0] of time point t [k0], form main cursor.
Relative to main cursor, receiving part of the signal Sx before time point t [k0] is preceding vernier, such as the sampling Sx of time point t [k0-1]
[k0-1]；Part of the signal Sy after time point t [k0] is rear vernier, such as the sampling Sx [k0+1] of time point t [k0+1].Time point
Interval between t [k0-1], t [k0] and t [k0+1] can be equal to period UI.
Ideally, the intensity of preceding vernier and rear vernier should be zero, leave behind main cursor.But, because it is logical
Non-ideal effects caused by road characteristic receive the preceding vernier and rear vernier that can leave suitable intensity in signal Sx, and cause symbol
Between interfere.
Continue Fig. 2, with continued reference to FIG. 3, interfering between its citing signal symbol.In the example in figure 3, the data letter of filtering
Number Sw, to three symbols are carried between t3, is sequentially logic 1,0 and 1 in time point t0.Via the transmitting in channel 204, time point t0 to t1
Between 1 square wave of logic can receiving end Rx formed waveform Wa, time point t2 to 1 square wave of logic between t3 then receiving end Rx formed wave
Shape Wb, and the reception signal Sx of receiving end Rx is to be synthesized by waveform Wa with Wb, the logic 1,0 in the data-signal Sw of filtering with
1 respectively corresponds sampling Sx [k0], the Sx [k0+1] and Sx [k0+2] received in signal Sx.
As seen from Figure 3, because the rear vernier (part after time point t [k0]) of waveform Wa and waveform Wb preceding vernier (when
Part before point t [k0+2]) can be in time point t [k0+1] addition, therefore the intensity for sampling Sx [k0+1] will not drop to zero, make originally
The sampling Sx [k0+1] that logical zero should be represented can be mistaken for logic 1 because interfering between symbol.It can by the discussion of Fig. 2 and Fig. 3
Know, in order to compensate for channel characteristic and subtract suppression symbol between interfere, it should completely to consider the influence of preceding vernier Yu rear vernier.
Substantially, the decision feedback equalizer in clock data recovery system is by reducing the shadow of rear vernier in reception signal Sx
It rings and forms superposition signal Sz；The effect of this equilibrating mechanism can be illustrated with Fig. 4.As shown in figure 4, Xiang Yingyi logic 1 accords with
Member, a slow slow drop waveform of liter can be presented by receiving signal Sx, reflect logic 1, but vernier thereafter in the sampling Sz [k] of superposition signal Sz
Still there is comparable signal strength in part.But, after via decision feedback equalizer, the rear vernier part meeting in signal Sx is received
It is reduced by feedback equalization signal, makes the corresponding sampling Sz [k+1] in rear vernier part, Sz [k+2] etc. that can level off to zero, to inhibit
It is interfered between symbol.
Furthermore in order to reduce the rear vernier part received in signal Sx, decision feedback equalizer is needed according to decision feedback
The variation of equalizing coefficient group (DFE coefficient set) h1, h2, h3, h4, h5 generates feedback equalization signal.Such as Fig. 4 institute
Show, because superposition signal Sz is greater than the intensity of time point t [k+2] in the intensity of time point t [k+1], therefore coefficient h 1 is also greater than coefficient h 2.
Fig. 5 A is please referred to, depicted is serial device/solution sequence device clock and data recovery of first embodiment of the invention
System schematic.Clock data recovery system 500 includes: continuous time linear equalizer 510, data slicer (data
Slicer) 530, error cutter (error slicer) 540, clock data recovery circuit 550, adaptive filter
(adaptive filter) 560, decision feedback equalizer 570 and summer 520.Wherein, adaptive filter 560 can be base
In an adaptive filter (least mean square based adaptive filter) for lowest mean square.
As shown in Figure 5A, the other end in channel 204 is connected to the electronic circuit of receiving end Rx, so that it is defeated to receive signal Sx
The continuous time linear equalizer 510 for entering clock data recovery system 500 receives the high frequency section in signal Sx to improve
Size and become the first equalizing signal (first equalized signal) Sy.Furthermore summer 520 is by decision feedback equalization
The feedback equalization signal Sf and the first equalizing signal Sy that device 570 generates generate superposition signal Sz after being added up.
Data slicer 530 is according to clock signal clk and fixes killer voltage (slicing voltage) Ss, such as
0V, to cut (slice) superposition signal Sz and generate data-signal Sd.Furthermore error cutter 540 is according to clock signal clk
And reference voltage (reference voltage) Vref, to cut (slice) superposition signal Sz and generate error signal
Serr。
Clock data recovery circuit 550 receives data-signal Sd and error signal Serr to generate clock signal clk to number
According to cutter 530 and error cutter 540.Furthermore adaptive filter 560 receives data-signal Sd and error signal Serr and comes
A reference voltage Vref is generated to error cutter 540, and generates a decision feedback equalization coefficient sets (DFE
Coefficient set) h1, h2, h3, h4, h5 to decision feedback equalizer 570.
Furthermore decision feedback equalizer 570 receives data-signal Sd and decision feedback equalization coefficient sets h1, h2, h3, h4,
Feedback equalization signal Sf is generated after h5 to summer 520, to reduce the rear vernier part in the first equalizing signal Sy.Substantially
On, the relationship between superposition signal Sz, feedback equalization signal Sf and the first equalizing signal Sy are as follows:
Substantially, the clock data recovery system 500 of Fig. 5 A be using identical clock signal clk to superposition signal Sz into
The sampling of row data and phase error.Such clock data recovery system 500, what clock data recovery circuit 550 generated
Clock signal is identical as data rate.Therefore, data recovery system 500 can be referred to as Bao rate data recovery system (baud rate
clock data recovering system).It furthermore further include that mesh strangles mesh Le phase inspection in clock data recovery circuit 550
Device (Muler-Muler phase detector) is surveyed to receive data-signal Sd and error signal Serr, and generates phase accordingly
Position more new information (phase update information), to adjust the phase of clock signal clk.
B referring to figure 5., the depicted coupling effect (coupling effect) between signal in first embodiment
Schematic diagram.As shown in Figure 5 B, dotted line I is that feedback equalization signal Sf does not input the superposition signal Sz before superposer 520；Solid line II is
Feedback equalization signal Sf inputs the superposition signal Sz after superposer 520.
Before feedback equalization signal Sf does not input superposer 520, superposition signal Sz becomes dotted line I.At this point, error signal
Serr can be in 1 transition of phase ψ, and the sampling phase (sampled phase) of clock signal clk can be locked 1 position phase ψ.
However, superposition signal Sz becomes solid line II after feedback equalization signal Sf inputs superposer 520.Error signal Serr can be in phase
Position 2 transition of ψ, and the sampling phase (sampled phase) of clock signal clk can be locked 2 position phase ψ.Also that is, locking phase
Position generates the meeting offset of Δ ψ.In other words, coupling effect can be generated between the first equalizing signal Sy and feedback equalization signal Sf,
And the phase of clock signal clk will receive the influence of feedback equalization signal Sf so that system is unstable.
Fig. 6 A is please referred to, depicted is serial device/solution sequence device clock and data recovery of second embodiment of the invention
System schematic.Clock data recovery system 600 includes: continuous time linear equalizer 610, the mistake of data slicer 630, first
Poor cutter 640, the second error cutter 645, clock data recovery circuit 650, adaptive filter 660, decision feedback are equal
Weighing apparatus 670 and summer 620.Wherein, adaptive filter 660 may be based on an adaptive filter (least of lowest mean square
mean square based adaptive filter)。
As shown in Figure 6A, the other end in channel 204 is connected to the electronic circuit of receiving end Rx, so that it is defeated to receive signal Sx
The continuous time linear equalizer 610 for entering clock data recovery system 600 receives the high frequency section in signal Sx to improve
Size and become the first equalizing signal Sy.And the feedback equalization signal Sf that summer 620 generates decision feedback equalizer 670 with
First equalizing signal Sy generates superposition signal Sz after being added up.
Data slicer 630 is according to clock signal clk and fixed killer voltage Ss, such as 0V, to cut superposition signal
Sz simultaneously generates data-signal Sd.Furthermore first error cutter 640 is according to clock signal clk and reference voltage Vref, to cut
It cuts superposition signal Sz and generates first error signal Serr1.Second error cutter 645 is according to clock signal clk and reference
Voltage Vref subtracts the result (Vref-h1) of the first decision feedback equalization coefficient h 1, to cut superposition signal Sz and generate second
Error signal Serr2.
Furthermore clock data recovery circuit 650 receives data-signal Sd and the second error signal Serr2 to generate clock letter
Number CLK is to data slicer 630, first error cutter 640 and the second error cutter 645.
Second embodiment according to the present invention, adaptive filter 660 receive data-signal Sd and first error signal
Serr1 generates a reference voltage Vref to first error cutter 640, and generates a decision feedback equalization coefficient sets (DFE
Coefficient set) h1, h2, h3, h4, h5 to decision feedback equalizer 670.Wherein, reference voltage Vref subtracts first and determines
The result (Vref-h1) for instigating rebellion within enemy camp feedback equalizing coefficient h1 is then transferred to the second error cutter 645.Substantially, adaptive filter
660 dynamically change the reference voltage Vref and decision feedback according to data-signal Sd and the first error signal Serr1
Equalizing coefficient group h1, h2, h3, h4, h5.
Furthermore decision feedback equalizer 670 receives data-signal Sd and decision feedback equalization coefficient sets h1, h2, h3, h4,
Feedback equalization signal Sf is generated after h5 to summer 620, to reduce the rear vernier part in the first equalizing signal Sy.Substantially
On, the relationship between superposition signal Sz, feedback equalization signal Sf and the first equalizing signal Sy are as follows:
Similarly, the clock data recovery system 600 of Fig. 6 A is to be carried out using identical clock signal clk to superposition signal Sz
The sampling of data and phase error.Such clock data recovery system 600, clock data recovery circuit 650 generate when
Clock signal is identical as data rate.Therefore, data recovery system 600 is also referred to as Bao rate data recovery system.Furthermore clock
It further include that mesh strangles mesh Le phase detectors to receive data-signal Sd and the second error signal in data recovery circuit 650
Serr2, and phase more new information is generated accordingly, to adjust the phase of clock signal clk.
Fig. 6 B is please referred to, the depicted uncoupling effect (decoupling between signal in second embodiment
Effect) schematic diagram.As shown in Figure 6B, dotted line I is that feedback equalization signal Sf does not input the superposition signal Sz before superposer 620；
Solid line II is that feedback equalization signal Sf inputs the superposition signal Sz after superposer 620.
Before feedback equalization signal Sf does not input superposer 620, superposition signal Sz becomes dotted line I.At this point, the second error is believed
Number Serr2 can be in 1 transition of phase ψ, and the sampling phase of clock signal clk can be locked 1 position phase ψ.Furthermore when feedback is equal
It weighs after signal Sf input superposer 620, superposition signal Sz becomes solid line II.Second error signal Serr2 also can be 1 turn in phase ψ
State, and the sampling phase of clock signal clk can also be locked 1 position phase ψ.Also that is, locking phase will not generate offset.Change sentence
It talks about, coupling effect can or can not be generated between the first equalizing signal Sy and feedback equalization signal Sf, the phase of clock signal clk is not
It will receive the influence of feedback equalization signal Sf, so that system is more stable.
Compared to first embodiment, one second error is increased in the clock data recovery system 600 of second embodiment and is cut
Cutter 645, and another killer voltage is provided (reference voltage Vref subtracts the result of the first decision feedback equalization coefficient h 1
(Vref-h1)) to the second error cutter 645.In this way, the phase of clock signal clk can be made not will receive feedback equalization
The influence of signal Sf, so that system is more stable.
It can also include a variable gain amplifier furthermore in clock data recovery system 600 of the invention
(variable gain amplifier, abbreviation VGA), is configured at input terminal and the continuous time of clock data recovery system 600
Between linear equalizer 610, to the size of leading amplification channel signal, and after becoming and receiving signal Sx, then consecutive hours is inputted
Between linear equalizer 610.
Although however, it is not to limit the invention in conclusion the present invention is disclosed as above with preferred embodiment.This hair
Bright one of ordinary skill in the art without departing from the spirit and scope of the present invention, when can be used for a variety of modifications and variations.Therefore, originally
The protection scope of invention is subject to view the appended claims confining spectrum.
Claims (7)
1. a kind of clock data recovery system, comprising:
Continuous time linear equalizer receives signal and generates the first equalizing signal；
Summer receives first equalizing signal and feedback equalization signal, and generates superposition signal；
First error cutter cuts the superposition signal according to clock signal and the first killer voltage and generates first error
Signal；
Second error cutter cuts the superposition signal according to the clock signal and the second killer voltage and generates second and misses
Difference signal；
Data slicer cuts the superposition signal according to the clock signal and third killer voltage and generates data-signal；
Clock data recovery circuit receives the data-signal and second error signal, and generates the clock signal accordingly and extremely should
Data slicer, the first error cutter and the second error cutter；
Adaptive filter receives the data-signal and the first error signal, and generates reference voltage accordingly to first mistake
Poor cutter, and decision feedback equalization coefficient sets are generated, wherein the reference voltage is equal to first killer voltage；And
Decision feedback equalizer receives the data-signal and the decision feedback equalization coefficient sets, and generates the feedback equalization accordingly
Signal is to the summer；And
It wherein include the first decision feedback equalization coefficient in the decision feedback equalization coefficient sets, and second killer voltage is equal to this
Reference voltage subtracts the first decision feedback equalization coefficient and the third killer voltage as fixed killer voltage.
2. clock data recovery system as described in claim 1, wherein the continuous time linear equalizer is connected to channel use
To receive the reception signal of channel output.
3. clock data recovery system as described in claim 1, further includes: variable gain amplifier, be connected to channel to
The channel signal of channel output is received, and amplifies the size of the channel signal and becomes the reception signal, and it is continuous to input this
Linearly balanced device.
4. clock data recovery system as described in claim 1, wherein the adaptive filter is according to the data-signal and is somebody's turn to do
First error signal dynamically changes second killer voltage.
5. clock data recovery system as claimed in claim 4, wherein the adaptive filter according to the data-signal and is somebody's turn to do
First error signal dynamically changes the decision feedback equalization coefficient sets.
6. clock data recovery system as described in claim 1 wherein further includes that mesh strangles mesh in the clock data recovery circuit
Phase detectors are strangled, the data-signal and second error signal are received, and generate phase more new information accordingly to adjust
The phase of the clock signal.
7. clock data recovery system as described in claim 1, wherein the adaptive filter is suitable based on lowest mean square
Answering property filter.
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| CN100496032C (en) * | 2003-12-19 | 2009-06-03 | 美国博通公司 | Method and communication system for setting loop delay of decision feedback equalizer |
| CN104253606A (en) * | 2013-06-26 | 2014-12-31 | 创意电子股份有限公司 | Receiving circuit |
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