CN106506019A - A Broadband Large Dynamic Radio Frequency Receiver Chip - Google Patents

Abstract

The invention discloses a kind of broadband Larger Dynamic radiofrequency receiving chip, it is integrated RF LNA, frequency mixer, intermediate frequency controllable gain amplifier and analog-digital converter in a chip, using internal mixing, the process structure that amplifies, sample, the digitized process to radio frequency analog signal is completed.The chip integration is high, reduces significantly hardware volume, and realizes volume production by flow, substantially reduces hardware cost, be particularly well-suited in large scale digital phased array.

Description

A Broadband Large Dynamic Radio Frequency Receiver Chip

technical field

The invention relates to the fields of large-scale digital phased array and aerospace measurement and control.

Background technique

In recent years, with the continuous improvement of the performance of high-speed digital circuits, phased arrays are moving towards full digitalization, and digital phased arrays have become a new research direction. The digital phased array first digitizes the analog signal, then performs amplitude and phase weighting in the digital domain, and then synthesizes the space beam. Since the amplitude and phase weighting is carried out in the digital domain, algorithms such as multi-beam forming and self-adaptation become easy to implement, and the performance of the digital phased array is significantly improved.

The prerequisite for the realization of digital phased array is to have a hardware receiving platform for digitizing analog signals, and the performance of the hardware platform determines the performance of digital phased array. The simplest and most direct hardware receiving platform is to use an analog-to-digital converter capable of direct radio frequency sampling to directly sample and quantize the radio frequency analog signal received by the antenna into a digital signal. The input bandwidth of the analog-to-digital converter required by this hardware platform is higher than the highest frequency of the radio frequency signal, and the input bandwidth of the existing high-performance analog-to-digital converter is only about 3GHz. For signals higher than the 3GHz band, the RF direct acquisition The scheme is no longer applicable, and this analog-to-digital converter is expensive and is not suitable for large-scale digital phased arrays.

At present, the commonly used hardware receiving platform of digital phased array adopts the scheme of down-converting first and then intermediate frequency sampling. The RF signal received by the antenna and the appropriate local oscillator signal are down-converted into an intermediate frequency signal, and then filtered, intermediate frequency amplified, and then sent to the module. The samples are digitized by the digital converter, which reduces the requirement on the input bandwidth of the analog-to-digital converter. This solution is composed of discrete devices cascaded, with many connections, bulky and bulky, which is not conducive to the miniaturization design of the platform, and also brings a lot of inconvenience to the installation and maintenance of large-scale digital phased arrays. In addition, the large number of devices leads to The consistency becomes worse, seriously affecting the performance of the digital phased array.

How to reduce the size and cost of the receiving hardware platform without reducing the performance is the primary problem facing the realization of large-scale digital phased array.

Contents of the invention

The present invention solves the technical problems mentioned in the above-mentioned background technology, and integrates a radio frequency low noise amplifier, a mixer, an intermediate frequency controllable gain amplifier and an analog-to-digital converter in one chip, greatly reducing the size of the hardware, and Chips realize mass production, reduce hardware costs, and provide a high-performance, low-cost, and small-volume receiving hardware platform for digital phased arrays.

The present invention is achieved like this:

A wide-band large dynamic radio frequency receiving chip is characterized in that it includes an integrated drive module, a low noise amplifier, a buffer module, a mixer, a controllable gain amplifier and an analog-to-digital converter; the low noise amplifier receives an externally input radio frequency differential signal , amplify the RF differential signal, and output the amplified RF differential signal to the mixer; the buffer module receives the externally input local oscillator differential signal, adjusts the local oscillator differential signal, and outputs the adjusted local oscillator differential signal to Mixer; the mixer mixes the amplified RF differential signal and the adjusted local oscillator differential signal to form an intermediate frequency differential signal, and outputs the intermediate frequency differential signal; the controllable gain amplifier receives the filtered intermediate frequency differential signal input from the outside , amplify the filtered intermediate frequency differential signal, and output the amplified intermediate frequency differential signal to the outside; the analog-to-digital converter receives the filtered intermediate frequency differential signal input from the outside, converts the filtered intermediate frequency differential signal into a digital signal, and The digital signal is output to the integrated drive module; the integrated drive module integrates the digital signal into DDR data format and outputs it with differential LVDS level; the parameters of the controllable gain amplifier are set through the serial port configuration; the sampling clock is provided for the analog-to-digital converter through the clock interface.

Among them, the low noise amplifier, buffer module, mixer, controllable gain amplifier and analog-to-digital converter form the receiving channel, and the wide-band and large dynamic radio frequency receiving chip includes multiple receiving channels.

Among them, each module inside the broadband large dynamic radio frequency receiving chip adopts an independent power supply mode.

Among them, the wide-band large dynamic radio frequency receiving chip adopts CMOS manufacturing process, adopts QFN88 package form, and the volume is 10mm×10mm×0.85mm.

The present invention has the following advantages:

The invention has the advantages of high integration, small size, low cost, wide frequency band, large dynamics, high precision and good consistency, and is especially suitable for large-scale digital phased arrays.

Description of drawings

Fig. 1 is a structural block diagram of the present invention.

detailed description

Referring to Figure 1, the chip includes an integrated drive module and a receiving channel, and the receiving channel includes a low-noise amplifier, a buffer module, a mixer, a gain-controllable amplifier, and an analog-to-digital converter; the chip includes a first balun, a second balun , the third balun, the fourth balun, filter and filter network; the embodiment of the present invention integrates two parallel channels, and each channel is divided into three parts: radio frequency, intermediate frequency and ADC, wherein the radio frequency part includes low-noise amplifier and frequency mixer The intermediate frequency part includes a controllable gain amplifier, and the ADC part includes a 14-bit, 250MSPS analog-to-digital converter. In addition, an external filter, filter network and balun are required to be used together. The external filter, filter network and balun can be used together. Select and adjust according to different actual parameters.

In the present invention, the RF signal inlet and the local oscillator inlet adopt a differential input mode, and the RF signal is converted into a RF differential signal by the first balun and then input to the low noise amplifier. The frequency range of the input RF signal is 2.2GHz to 2.4GHz, and the RF input signal is electrically The maximum level is -30dBm; the low-noise amplifier amplifies the RF differential signal, and outputs the amplified RF differential signal to the mixer; the local oscillator signal is converted into a local oscillator differential signal by the second balun and then output to the buffer module. The input bandwidth of the vibration signal is 1.6GHz~2.4GHz, and the input level of the local oscillator signal is 0dBm~10dBm; the gain of the low noise amplifier is 13dB, and the gain of the mixer is 9dB. The low noise amplifier can be set to bypass mode through the SPI port , so that the gain of the low noise amplifier is 0dB, so the gain of the radio frequency part is divided into two levels of 22dB and 9dB, and there is an adjustable gain of 13dB.

The buffer module adjusts the local oscillator differential signal, and outputs the adjusted local oscillator differential signal to the mixer; the mixer mixes the amplified radio frequency differential signal and the adjusted local oscillator differential signal to form an intermediate frequency differential signal, Output the intermediate frequency differential signal to the third balun; the third balun converts the intermediate frequency differential signal into an intermediate frequency single-ended signal, and outputs the intermediate frequency single-ended signal to the filter; the filter filters the intermediate frequency single-ended signal, and the filtered The intermediate frequency single-ended signal is output to the fourth balun; the fourth balun converts the filtered intermediate frequency single-ended signal into an intermediate frequency differential signal, and outputs the filtered intermediate frequency differential signal to the controllable gain amplifier; the controllable gain amplifier converts the intermediate frequency differential The signal is amplified, and the amplified intermediate frequency differential signal is output to the filter network. The frequency range of the controllable gain amplifier is 10MHz~550MHz; the maximum gain is 20dB, the gain adjustable range is 20dB, and the gain step is 1dB; the filter network will amplify The final intermediate frequency differential signal filters out clutter and interference, and outputs the filtered intermediate frequency differential signal to the analog-to-digital converter; the analog-to-digital converter converts the filtered intermediate frequency differential signal into a digital signal, and outputs the digital signal to the integrated drive module ;The A/D converter has an overflow flag port, and the FPGA can configure the appropriate RF part gain and IF part gain through the SPI port according to the overflow flag; the maximum sampling frequency of the A/D converter is 250MSPS, according to the Nyquist sampling theorem , corresponding to a sampling bandwidth of 125MHz without spectral aliasing. The full power bandwidth is 600MHz, and the full-scale signal power is 8dBm; the output digit of the analog-to-digital converter is 14 bits. The integrated drive module integrates two channels of digital signals into DDR data format and uses differential LVDS level for output; the output of two channels of analog-to-digital converters is integrated to transmit data in DDR mode, that is, the rising edge of the sampling clock transmits the sampling results of one channel of analog-to-digital converters , the falling edge transmits the sampling result of another analog-to-digital converter, and then drives the output to the lower level, which can reduce the number of data output pins and facilitate the integration of multiple chips on a receiving hardware platform. Set the parameters of the controllable gain amplifier through the serial port configuration; set the clock of the analog-to-digital converter through the sampling clock interface.

The analog-to-digital converter has an overflow flag port, and the FPGA can configure appropriate gain of the radio frequency part and gain of the intermediate frequency part through the SPI port according to the overflow flag. The maximum sampling frequency of the ADC is as high as 250MSPS. According to the Nyquist sampling theorem, the ADC can theoretically sample a 125MHz broadband signal without spectral aliasing. The effective number of digits of the analog-to-digital converter is 10.5 bits, and the corresponding dynamic range is 63dB. In addition to the 13dB adjustable gain of the RF part and the 20dB adjustable gain of the intermediate frequency part, the dynamic range of the chip input can reach up to 96dB. The noise figure of the entire receiving channel is only 7dB. The gain consistency among different channels of different chips is better than ±0.5dB, and the phase consistency is better than ±10°; within the temperature range of -45° to 60°, the gain variation is better than ±2dB, and the phase variation is better than ±3° .

Claims (4)

1. A wide-band large dynamic radio frequency receiving chip is characterized in that it includes an integrated drive module, a low noise amplifier, a buffer module, a mixer, a controllable gain amplifier and an analog-to-digital converter; the low noise amplifier receives the externally input radio frequency Differential signal, amplifies the RF differential signal, and outputs the amplified RF differential signal to the mixer; the buffer module receives the externally input local oscillator differential signal, adjusts the local oscillator differential signal, and outputs the adjusted local oscillator differential signal Output to the mixer; the mixer mixes the amplified RF differential signal and the adjusted local oscillator differential signal to form an intermediate frequency differential signal, and outputs the intermediate frequency differential signal; the controllable gain amplifier receives the filtered intermediate frequency from the external input Differential signal, amplifies the filtered intermediate frequency differential signal, and outputs the amplified intermediate frequency differential signal to the outside; the analog-to-digital converter receives the filtered intermediate frequency differential signal input from the outside, and converts the filtered intermediate frequency differential signal into a digital signal , output the digital signal to the integrated drive module; the integrated drive module integrates the digital signal into DDR data format and outputs it with differential LVDS level; set the parameters of the controllable gain amplifier through the serial port configuration; set the analog-to-digital converter through the sampling clock interface clock. 2. A kind of wideband large dynamic radio frequency receiving chip according to claim 1, is characterized in that, low noise amplifier, buffer module, mixer, controllable gain amplifier and analog-to-digital converter form receiving channel, wideband is large The dynamic radio frequency receiving chip includes multiple receiving channels. 3. A wide-band large dynamic radio frequency receiving chip according to claim 1, wherein each module inside the wide-band large dynamic radio frequency receiving chip adopts an independent power supply mode. 4. A wide-band large dynamic radio frequency receiving chip according to claim 1, characterized in that the wide-band large dynamic radio frequency receiving chip adopts a CMOS manufacturing process, adopts a QFN88 package form, and has a volume of 10mm×10mm×0.85mm.