CN106409335A - Content addressing storage unit circuit and search and write operation methods thereof, and memory - Google Patents

Abstract

The invention discloses a content addressing memory unit circuit, its searching and writing operation method, and memory. The present invention includes: first and second memristors, search signal lines, write signal lines, matching lines, output lines, first and second data lines, common voltage lines, first, second and third transistors; the first memristor The resistor is connected to the second memristor, and the connected place is a voltage dividing point; the first memristor is connected to the first data line, and the second memristor is connected to the second data line; the voltage dividing point, the common voltage line and the writing The signal line is connected to the first transistor, and the output of the write signal line is used to control the on and off between the voltage dividing point and the common voltage line; the voltage dividing point, the search signal line, and the third transistor are respectively connected to the second transistor, The output of the search signal line is used to control the on and off between the voltage dividing point and the third transistor; the matching line, the output line and the second transistor are respectively connected to the third transistor, and the output of the second transistor is used to control the matching line The conduction and disconnection of the output line.

Description

Content addressable storage unit circuit and search and write operation method thereof, memory

technical field

The invention relates to the field of analog circuits, in particular to a content-addressable storage unit circuit, search and write operation methods, and a memory.

Background technique

Content addressable memory (English full name: Content Addressable Memory, abbreviation: CAM) is a special storage array. It compares the input data with all the data items stored in the CAM at the same time, quickly judges whether the input data matches the stored data items in the CAM, and gives the corresponding address and matching information of the matching data items. CAM is widely used in telecommunications, network and other fields due to its high-speed search and large capacity.

Memristor is the fourth basic circuit element besides resistors, capacitors, and inductors, and it represents the relationship between charge and magnetic flux. The resistance of a memristor changes with the amount of current passing through it. Even if the current flow stops, the resistance of the memristor will stay at the previous value until it receives the reverse current. It will not be pushed back. The high-resistance state and low-resistance state of memristor can be used to store "0" and "1" for information storage, and has the advantages of non-volatility, low power consumption, high speed, and high integration. Combining the memristor and the CAM, and using the memristor as the storage material of the CAM, the CAM can still save data when the power is turned off, so that its power consumption can be greatly reduced.

Please refer to FIG. 1 . FIG. 1 is a schematic structural diagram of a conventional memristor-based content storage unit. As shown in FIG. 1 , the sources and drains of MOS transistors T5 , T3 , T4 , and T6 are connected in series in sequence, wherein the source of T5 is connected to the data line D/S, and the drain of T6 is connected to the data line. The gates of T5 and T6 are respectively connected to the search data line SS. The gate of T3 is connected to the source of T1 and one end of the memristor 2 at the same time. The gate of T4 is connected to the source of T2 and one end of the memristor 3 at the same time. The gate of T1 and the gate of T2 are respectively connected to the write signal line WS. The drain of T1 is connected to the data line D/S, and the drain of T2 is connected to the data line. The other end of the memristor 2 and the other end of the memristor 3 are respectively connected to the common voltage line VL. The match line ML and the output line ML(n+1) are respectively connected to the source and drain of the MOS transistor T7, and the gate of T7 is connected to the drain of T3 and the source of T4 at the same time.

The working process of the circuit shown in Figure 1 is described below.

In the write operation, the search signal line SS inputs a low level, so that the MOS transistors T4 and T5 are turned off. The write signal line WS inputs a high level, so that the MOS transistors T1 and T2 are turned on. At this time, the data lines D/S and D/S change the resistance values of the memristors 2 and 3 through the MOS transistors T1 and T2 to perform a write operation. Storing data.

In the read operation, the write signal line WS inputs a low level, so that the MOS transistors T1 and T2 are turned off. The search signal line SS inputs a high level, so that the MOS transistors T4 and T5 are turned on. The potential of the common voltage line VL is set to V _DD /2. According to the data stored in the memristor before (indicated by high and low resistance values), it is determined whether the MOS transistor T3 or T4 is turned on. If T3 is turned on, the potential of the gate of the MOS transistor T7 is the voltage on the data line D/S, and if T4 is turned on, the potential of the gate of the MOS transistor T7 is the voltage on the data line D/S. To sum up, when the voltage stored in the memristor is consistent with the voltage on the data line, the gate voltage of the MOS transistor T7 is at a high level, and the current at the ML(n) terminal of the MOS transistor T7 is passed to the ML(n +1) terminal, and vice versa.

However, in this kind of circuit solution, more MOS transistors are used, which makes the wiring complicated and increases the power consumption and manufacturing cost of the system.

Contents of the invention

The embodiment of the present invention provides a content addressable storage unit circuit with a simple structure.

In the first aspect, a content addressable storage unit circuit is provided, the circuit includes: a first memristor (ME1), a second memristor (ME2), a search signal line (SS), and a write signal line (WS) , match line (WL), output line (OP), first data line (D/S), second data line Common voltage line (VL), first transistor (M1), second transistor (M2), third transistor (M3);

One end of the first memristor (ME1) is connected to one end of the second memristor (ME2), and the connection point is a voltage dividing point; the other end of the first memristor (ME1) is connected to the second memristor (ME2). The first data line (D/S) is connected, and the other end of the second memristor (ME2) is connected to the second data line connected;

The voltage dividing point, the common voltage line (VL) and the write signal line (WS) are respectively connected to the first transistor (M1), and the output of the write signal line (WS) is used to control the conduction and disconnection between the voltage dividing point and the common voltage line (VL);

The voltage dividing point, the search signal line (SS), and the third transistor (M3) are respectively connected to the second transistor (M2), and the output of the search signal line is used to control the voltage dividing point conduction and disconnection with the third transistor (M3);

The matching line (WL), the output line and the second transistor (M2) are respectively connected to the third transistor (M3), and the output of the second transistor (M2) is used to control the matching line (WL) and the conduction and disconnection of the output line.

With reference to the first aspect, in the first implementation manner of the first aspect, the circuit further includes a fourth transistor (M), configured to be connected to the matching line (WL) and the output line, and configured to control the The conduction and disconnection of the matching line (WL) and the output line OP.

With reference to the first aspect, in the second implementation manner of the first aspect, the positive terminal of the first memristor (ME1) is connected to the positive terminal of the second memristor (ME2), or, the The negative terminal of the first memristor (ME1) is connected to the negative terminal of the second memristor (ME2).

With reference to the first aspect, in a third implementation manner of the first aspect, the positive terminal of the first memristor (ME1) is connected to the negative terminal of the second memristor (ME2), or, the first memristor (ME2) is The negative end of a memristor (ME1) is connected to the positive end of said second memristor (ME2).

In a second aspect, there is provided a memory, which is characterized by comprising the content-addressable storage unit circuit as described in any one of the above.

In a third aspect, there is provided a write operation method based on the content-addressable storage unit circuit described in the first aspect, the method comprising:

inputting a voltage to the search signal line (SS), so that the voltage dividing point is disconnected from the third transistor (M3);

inputting a voltage to the write signal line (WS), making conduction between the voltage dividing point and the common voltage line (VL);

input voltage to the first data line (D/S) and the second data line respectively And the voltage is input to the voltage dividing point through the common voltage line, so that one of the resistance of the first memristor (ME1) and the second memristor (ME2) is greater than the resistance of the other A preset multiple, wherein the preset multiple is greater than 1 time.

With reference to the third aspect, in the first implementation manner of the third aspect, in the content addressable storage unit circuit, the positive terminal of the first memristor (ME1) and the second memristor (ME2) ), or the negative terminal of the first memristor (ME1) is connected to the negative terminal of the second memristor (ME2);

The first data line (D/S), the common voltage line (VL), the second data line The voltage on it decreases or increases sequentially.

With reference to the first implementation of the third aspect, in the second implementation of the third aspect, the voltage on the common voltage line (VL) is equal to the voltage on the first data line (D/S) and The second data line The average value of the voltage on the

With reference to the third aspect, in a third implementation manner of the third aspect, the positive terminal of the first memristor (ME1) is connected to the negative terminal of the second memristor (ME2), or, the first memristor (ME2) The negative end of a memristor (ME1) is connected to the positive end of the second memristor (ME2);

The first data line (D/S) and the second data line The voltages on both are greater than or less than the voltage on the common voltage line (VL).

In a fourth aspect, there is provided a search operation method based on the content-addressable storage unit circuit described in the first aspect, the method comprising:

input voltage to the write signal line (WS), so that the voltage dividing point is disconnected from the common voltage line (VL);

input a high level to the matching line WL;

input voltage to the first data line (D/S) and the second data line respectively Wherein the first data line (D/S) and the second data line The voltage of one of them is a high level, and the voltage of the other is a low level, so that the voltage division point A forms a high level or a low level;

inputting a voltage to the search signal line (SS), making conduction between the voltage dividing point and the third transistor (M3);

When the output line OP outputs a high level, it is determined that the data stored in the content addressable storage unit circuit is one between 0 and 1, otherwise it is determined that the data stored in the content addressable storage unit circuit is read Data is another between 0 and 1.

With reference to the fourth aspect, in the first implementation manner of the fourth aspect, the input voltage is applied to the search signal line (SS), so that the conduction between the voltage dividing point and the third transistor (M3) , which previously also included:

Input voltage to the search signal line (SS), so that the voltage dividing point is disconnected from the third transistor (M3). It can be seen from the above technical solutions that the embodiments of the present invention have the following advantages:

In the present invention, the structure and wiring of the content addressing storage unit circuit is simple, and the power consumption and manufacturing cost of the content addressing storage unit circuit are reduced.

Description of drawings

FIG. 1 is a schematic structural diagram of an existing content addressable storage unit circuit;

FIG. 2 is a schematic structural diagram of an embodiment of a content addressable storage unit circuit of the present invention;

FIG. 3 is a schematic flow chart of a write operation based on the content addressable storage unit circuit shown in FIG. 2;

FIG. 4 is a schematic flowchart of a search operation based on the content addressable memory cell circuit shown in FIG. 2 .

detailed description

In order to enable those skilled in the art to better understand the solutions of the present invention, the following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only It is an embodiment of a part of the present invention, but not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts shall fall within the protection scope of the present invention.

The terms "comprising" and "having" in the description and claims of the present invention and the above drawings, as well as any variations thereof, are intended to cover non-exclusive inclusion, for example, processes, methods, A system, product or device is not necessarily limited to those steps or elements explicitly listed, but may include other steps or elements not explicitly listed or inherent to the process, method, system, product or device.

As shown in FIG. 2 , FIG. 2 is a schematic structural diagram of an embodiment of a content addressable storage unit circuit of the present invention.

As shown in Figure 2, the unit circuit in this embodiment includes a first memristor ME1, a second memristor ME2, a search signal line SS, a write signal line WS, a matching line WL, an output line, and a first data line D /S, the second data line The common voltage line VL, the first transistor M1, the second transistor M2, and the third transistor M3.

One end of the first memristor ME1 is connected to one end of the second memristor ME2. For the convenience of description, the junction of the first memristor ME1 and the second memristor ME2 is called a voltage dividing point A. The other end of the first memristor ME1 is connected to the first data line D/S, and the other end of the second memristor ME2 is connected to the second data line connected.

The voltage dividing point A, the common voltage line VL and the writing signal line WS are respectively connected to the first transistor M1, and the output of the writing signal line WS is used to control the voltage dividing point A and the writing signal line WS. The conduction and disconnection between the common voltage lines VL.

The voltage division point A, the search signal line SS, and the third transistor M3 are respectively connected to the second transistor M2, and the output of the search signal line SS is used to control the voltage division point A and the third transistor M3. The third transistor M3 is turned on and off.

The matching line WL, the output line and the second transistor M2 are respectively connected to the third transistor M3, and the output of the second transistor M2 is used to control the conduction between the matching line WL and the output line. On and off.

In this embodiment, there are various structural manners in which the first memristor ME1 is connected to the second memristor ME2.

For example, the first memristor ME1 and the second memristor ME2 are connected to the same terminal. As shown in Figure 2, the end of the memristor with the black border is called the negative end, and the other end is called the positive end. In FIG. 2 , the positive end of the first memristor ME1 is connected to the positive end of the second memristor ME2 . Alternatively, in practical applications, the negative terminal of the first memristor ME1 may also be connected to the negative terminal of the second memristor ME2.

For example, different ends of the first memristor ME1 and the second memristor ME2 are connected. The first data line D/S and the second data line The voltages on the common voltage line VL are greater than or lower than the voltage on the common voltage line VL. In this way, the direction of the potential difference formed between the first data line D/S and the voltage dividing point A is the same as that formed between the voltage dividing point A and the second data line. The direction of the potential difference formed between them is opposite. Since different ends of the first memristor ME1 and the second memristor ME2 are connected, the potential difference in the opposite direction will make the resistance of one memristor increase and the resistance of the other memristor become smaller.

Optionally, in this embodiment, the circuit further includes a fourth transistor M, which is used to connect the matching line WL and the output line OP, and is used to control the connection between the matching line WL and the output line OP. On and off. In this way, the tri-state function of the circuit can be realized. Specifically, a high level is input to the matching line WL; a voltage is input to the fourth transistor M to make conduction between the matching line WL and the output line. In this way, the output line OP can directly output a high level.

For example, when the fourth transistor M is a MOS transistor, the source and drain of the fourth MOS transistor M are respectively connected to the match line WL and the output line OP. Inputting a high level to the gate of the fourth MOS transistor M makes the match line WL conduct with the output line, and the output line OP directly outputs a high level.

In this embodiment, the transistor may be a field effect transistor, a triode or other transistors, which is not limited here. For the convenience of understanding, the circuit structure in this embodiment will be described in detail below by taking a MOS transistor as an example.

Specifically, the gate of the first MOS transistor M1 is connected to the write signal line WS, the source is connected to the common voltage line VL, and the drain is connected to the voltage dividing point A. The gate of the second MOS transistor M2 is connected to the search signal line SS, the source is connected to the voltage dividing point A, and the drain is connected to the gate of the third MOS transistor M3. The drain of the third MOS transistor M3 is connected to the matching line WL, and the source is connected to the output line.

The operation method of the content addressable memory cell circuit shown in FIG. 2 includes a write operation and a search operation. The following describes the writing operation workflow of the circuit shown in FIG. 2 .

As shown in FIG. 3 , FIG. 3 is a schematic flowchart of a write operation based on the content addressable storage unit circuit shown in FIG. 2 . In this embodiment, the operation method includes:

301. Input a voltage to the search signal line SS, so that the voltage dividing point A is disconnected from the third transistor M3.

Specifically, when the second transistor M2 is an NMOS transistor, input a low level to the search signal line SS, so that the source and drain of the second NMOS transistor M2 are disconnected, so that the voltage dividing point A and the third transistor M3 disconnected between.

302. Input a voltage to the write signal line WS, so that the voltage dividing point A and the common voltage line VL are conducted.

Specifically, when the first transistor M1 is an NMOS transistor, a high level is input to the write signal line WS, so that the source and drain of the first NMOS transistor M1 are conducted, so that the voltage of the common voltage line VL can be The voltage at dividing point A is clamped.

303. Input voltage to the first data line D/S and the second data line respectively And the voltage is input to the voltage division point A through the common voltage line, so that one of the resistance value of the first memristor ME1 and the second memristor ME2 is greater than a preset multiple of the other resistance value, wherein the The preset multiple is greater than 1.

In this embodiment, the memristors are defined to represent different logic values according to the different resistances of the memristors. For example, when the resistance value of the memristor is higher than the first preset value, the memristor is defined as representing logic "0", and when the resistance value of the memristor is lower than the second preset value, the memristor is defined as logic "0". Defined to represent a logic "1". Or, when the resistance value of the memristor is higher than the first preset value, the memristor is defined as representing logic "1", and when the resistance value of the memristor is lower than the second preset value, the memristor is Defined to represent a logic "0". Wherein, the first preset value is greater than the second preset value. In this way, when the first memristor M1 and the second memristor M2 are represented as "10", the data stored in the content addressable memory unit circuit is one between 0 and 1, when the first memristor M1 and the second memristor M2 are When the second memristor M2 represents "01", the data stored in the content addressable memory unit circuit is the other between 0 and 1.

In the following, logic "0" is represented when the resistance value of the memristor is higher than the first preset value, and logic "1" is represented when the resistance value of the memristor is lower than the second preset value, and the first memristor When M1 and the second memristor M2 represent "01", the data stored in the content addressable memory unit circuit is 0 as an example for description.

Specifically, the first memristor M1 and the second memristor M2 respectively include a positive terminal and a negative terminal, wherein the positive terminal of the first memristor M1 is connected to the positive terminal of the second memristor M2, or, the first The negative terminal of the memristor M1 is connected to the negative terminal of the second memristor M2. The first data line (D/S), the common voltage line (VL), the second data line The voltage on it decreases or increases sequentially. For example, the voltage on the common voltage line (VL) is the voltage on the first data line (D/S) and the voltage on the second data line The average value of the voltage on the .

Due to the potential difference from the first data line D/S to the voltage dividing point A, and the voltage dividing point A to the second data line The direction of the potential difference is the same, and the positive terminal of the first memristor M1 and the direction of the negative terminal of the second resistor M2 are opposite to each other, therefore, the first memristor M1 forms a high resistance, and the second memristor M2 forms a low resistance, That is, the first memristor M1 represents logic "0", and the second memristor M2 represents logic "1", so as to write data "0" in the content-addressable memory cell circuit. Alternatively, the first memristor M1 forms a low resistance, and the second memristor M2 forms a high resistance, that is, the first memristor M1 represents a logic "1", and the second memristor M2 represents a logic "0", so that in Write data "1" in the content addressable memory cell circuit.

It should be noted that the resistance of the memristor in this embodiment changes only when the voltage difference across the memristor is greater than a predetermined value. Therefore, in this embodiment, the first data line (D/S), the common voltage line (VL), the second data line The magnitude of the voltage on the first memristor M1 and the second memristor M2 needs to be able to change the resistance value, and it is necessary to make the resistance of one of the first memristor M1 and the second memristor M2 The value is greater than another preset multiple of the resistance value, wherein the preset multiple is greater than 1 (the specific reasons and the specific numerical value of the preset multiple are explained in the embodiment shown in Figure 4.)

Of course, in practical applications, the voltage of the voltage input by the common voltage line may not be located between the voltage input by the first data line D/S and the voltage input by the second data line. Between the input voltages, as long as the direction of the voltage difference across the first memristor and the second memristor is opposite, and the voltage difference across the first memristor ME1 and the voltage difference across the second memristor ME2 make One of the two memristors may have a resistance value greater than a preset multiple of the other resistance value.

For example, when the positive end of the first memristor M1 is connected to the negative end of the second memristor M2, or the negative end of the first memristor M1 is connected to the positive end of the second memristor M2, and the The first data line (D/S) and the second data line When the voltages on the first memristor M1 and the second memristor M2 are both greater than or less than the voltage on the common voltage line (VL), since the positive terminals of the first memristor M1 and the second memristor M2 point to the negative terminal in the same direction, the first memristor M1 The voltage differences between the two ends of the resistor M1 and the second memristor M2 are opposite, therefore, the resistance of one of the first memristor M1 and the second memristor M2 is greater than the resistance of the other. Of course, the voltage difference across the first memristor M1 and the voltage difference across the second memristor M2 must be large enough to make the resistance of the first memristor M1 and the resistance of the second memristor M2 change.

As shown in FIG. 4 , FIG. 4 is a schematic flowchart of a search operation based on the content addressable storage unit circuit shown in FIG. 2 . In this embodiment, the operation method includes:

401. Input a voltage to the write signal line WS, so that the voltage dividing point A is disconnected from the common voltage line VL.

In this embodiment, since the data stored in the content addressable memory unit circuit is read instead of written, the voltage dividing point A and the common voltage line VL are first disconnected to avoid writing data. .

Specifically, when the first transistor M1 is an NMOS transistor, input a low level to the write signal line WS, so that the source and drain of the first transistor M1 are disconnected, so that the voltage dividing point A and the common voltage line VL disconnected intermittently.

402. Input a high level to the matching line WL.

The match line WL inputs a high level. The third transistor M3 controls on and off between the match line WL and the output line OP. When it is turned on, the output line OP outputs a high level, and when it is turned off, the output line OP outputs a low level. Then, the output line OP can be used to output a high level to indicate that the read data is consistent with the searched data, and to output a low level to indicate that the read data is inconsistent with the searched data. Alternatively, the output line OP outputs a high level to indicate that the read data is inconsistent, and outputs a low level to indicate that the read data is consistent with the searched data, which is not limited here.

403. Input voltages to the first data line (D/S) and the second data line respectively Wherein the first data line (D/S) and the second data line The voltage of one of them is a high level, and the voltage of the other is a low level, so that the voltage division point A forms a high level or a low level.

In this embodiment, you can input high level to the first data line (D/S), and input low level to the second data line To indicate whether the data stored in the content-addressable storage unit circuit is 1 or not, input low level to the first data line (D/S), and input high level to the second data line To indicate whether the data stored in the content-addressable storage unit circuit is 0 or not. Alternatively, it is also possible to input a high level to the first data line (D/S), and input a low level to the second data line To indicate whether the data stored in the content-addressable storage unit circuit is 0, input low level to the first data line (D/S), and input high level to the second data line to indicate whether the data stored in the content-addressable storage unit circuit is 1 or not, which is not limited here.

In this embodiment, through the input voltage to the first data line (D/S) and the second data line A voltage is formed at the voltage division point A, and the voltage at the voltage division point A (high level or low level) determines whether the third transistor is turned on or off. And since the resistance value of one of the first memristor M1 and the second memristor M2 is greater than the preset multiple of the other resistance value, it is possible to pass the first data line (D/S) and the second memristor data line The setting of the voltage makes the voltage at the voltage dividing point A be high level or low level.

It should be noted that since the first data line D/S and the second data line The voltage is to read the data in the content addressable memory cell circuit, therefore, the first data line D/S and the second data line The voltage on the above makes the voltage difference between the two data lines not change the resistance values of the first memristor M1 and the second memristor M2.

404. Input a voltage to the search signal line SS, so as to conduct between the voltage dividing point and the third transistor M3.

In this embodiment, by making the connection between the voltage dividing point A and the third transistor M3 conduct, the voltage at the voltage dividing point A determines whether the third transistor M3 is turned on or off, that is, the voltage at the voltage dividing point A It is determined whether the high level on the match line WL can be output through the output line OP.

Specifically, when the second transistor M2 and the third transistor M3 are NMOS transistors, a high level is input to the search signal line SS, so that the source and the drain of the second transistor M2 are conducted, so that the voltage dividing point A and the third transistor M3, so that the point-in of the dividing voltage point A is input to the gate of the third NMOS transistor M3.

405. When the output line OP outputs the high level, determine that the data stored in the content-addressable storage unit circuit is one between 0 and 1, otherwise determine that the data stored in the content-addressable storage unit is read The data stored by the unit circuit is another between 0 and 1.

In the following, when the first memristor is a high resistance value and the second memristor is a low resistance value, it means that the data stored in the content addressable memory unit circuit is 0, and the voltage input by the first data line D/S is a low level , the second data line When the input voltage is at a high level, it means that the searched data 0 is described as an example.

When the resistance value of the first memristor in the content addressable memory unit circuit shown in FIG. 2 is greater than the preset multiple of the resistance value of the second memristor (that is, the data stored in the content addressable memory unit circuit is 0) :

If the first data line D/S input low level, the second data line Input a high level (that is, the data to be searched is 0), then the voltage at the voltage dividing point A is a high level, so the third NMOSM3 is turned on, and the output line OP outputs a high level, that is, when the searched data and When the data stored in the content addressable memory unit circuit is the same, output a high level.

If the first data line D/S inputs a high level, the second data line Input low level (that is, the data to be searched is 1), then the voltage at the voltage dividing point A is low level, so the third NMOS transistor M3 is disconnected, and the output line OP outputs low level, that is, when the searched When the data is different from the data stored in the content addressable storage unit circuit, it outputs a low level.

It can be seen from the above search process of the content addressable memory cell circuit shown in FIG. 2 that when the voltage dividing point A needs to form a high level, the specific voltage of the high level needs to make the third NMOS transistor M3 conduct. When the voltage dividing point A needs to form a low level, the specific voltage of the low level needs to make the third NMOS transistor M3 turn off. The specific voltage formed at the voltage dividing point A is determined by the resistance difference between the first memristor ME1 and the second memristor ME2. Therefore, the specific setting of the preset multiple only needs to make the high level formed at the voltage dividing point A The voltage is higher than the conduction threshold of the third NMOS transistor M3, and the formed low-level voltage is lower than the conduction threshold of the third NMOS transistor M3. Similarly, when the third transistor is not an NMOS transistor but other transistors, the principle of setting the preset multiple is the same as above.

Optionally, in this embodiment, in step 404, inputting a voltage to the search signal line SS, so that the conduction between the voltage dividing point and the third transistor M3 is also included before: inputting a voltage to the search The signal line SS is disconnected between the voltage dividing point and the third transistor M3. In this way, the voltage at the voltage dividing point can be stabilized before turning on the voltage dividing point and the third transistor M3.

The present invention also provides a memory, which includes any content-addressable memory unit circuit described herein.

Those skilled in the art can clearly understand that for the convenience and brevity of the description, the specific working process of the above-described system, device and unit can refer to the corresponding process in the foregoing method embodiment, which will not be repeated here.

In the several embodiments provided in this application, it should be understood that the disclosed system, device and method can be implemented in other ways. For example, the device embodiments described above are only illustrative. For example, the division of the units is only a logical function division. In actual implementation, there may be other division methods. For example, multiple units or components can be combined or May be integrated into another system, or some features may be ignored, or not implemented. In another point, the mutual coupling or direct coupling or communication connection shown or discussed may be through some interfaces, and the indirect coupling or communication connection of devices or units may be in electrical, mechanical or other forms.

The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place, or may be distributed to multiple network units. Part or all of the units can be selected according to actual needs to achieve the purpose of the solution of this embodiment.

In addition, each functional unit in each embodiment of the present invention may be integrated into one processing unit, each unit may exist separately physically, or two or more units may be integrated into one unit. The above-mentioned integrated units can be implemented in the form of hardware or in the form of software functional units.

If the integrated unit is realized in the form of a software function unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the essence of the technical solution of the present invention or the part that contributes to the prior art or all or part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a storage medium , including several instructions to make a computer device (which may be a personal computer, a server, or a network device, etc.) execute all or part of the steps of the method described in each embodiment of the present invention. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM, Read-OnlyMemory), random access memory (RAM, Random Access Memory), magnetic disk or optical disk and other media that can store program codes.

As mentioned above, the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that: it can still understand the foregoing The technical solutions recorded in each embodiment are modified, or some of the technical features are replaced equivalently; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the various embodiments of the present invention.

Claims (11)

1. A content addressable storage unit circuit, characterized in that the circuit comprises: a first memristor (ME1), a second memristor (ME2), a search signal line (SS), a write signal line (WS ), match line (WL), output line (OP), first data line (D/S), second data line Common voltage line (VL), first transistor (M1), second transistor (M2), third transistor (M3); One end of the first memristor (ME1) is connected to one end of the second memristor (ME2), and the connection point is a voltage dividing point; the other end of the first memristor (ME1) is connected to the second memristor (ME2). The first data line (D/S) is connected, and the other end of the second memristor (ME2) is connected to the second data line connected; The voltage dividing point, the common voltage line (VL) and the write signal line (WS) are respectively connected to the first transistor (M1), and the output of the write signal line (WS) is used to control the conduction and disconnection between the voltage dividing point and the common voltage line (VL); The voltage dividing point, the search signal line (SS), and the third transistor (M3) are respectively connected to the second transistor (M2), and the output of the search signal line is used to control the voltage dividing point conduction and disconnection with the third transistor (M3); The matching line (WL), the output line and the second transistor (M2) are respectively connected to the third transistor (M3), and the output of the second transistor (M2) is used to control the matching line (WL) and the conduction and disconnection of the output line. 2. The content addressable memory cell circuit according to claim 1, characterized in that, The circuit also includes a fourth transistor (M), which is used to connect with the matching line (WL) and the output line, and is used to control the on and off of the matching line (WL) and the output line OP open. 3. The content addressable memory cell circuit according to claim 1, characterized in that, The positive end of the first memristor (ME1) is connected to the positive end of the second memristor (ME2), or the negative end of the first memristor (ME1) is connected to the second memristor The negative terminal of the resistor (ME2) is connected. 4. The content addressable storage unit circuit according to claim 1, characterized in that, the positive end of the first memristor (ME1) is connected to the negative end of the second memristor (ME2), or, The negative terminal of the first memristor (ME1) is connected to the positive terminal of the second memristor (ME2). 5. A memory, characterized by comprising the content addressable storage unit circuit according to any one of claims 1 to 6. 6. A write operation method based on the content addressable storage unit circuit according to claim 1, characterized in that, the method comprises: inputting a voltage to the search signal line (SS), so that the voltage dividing point is disconnected from the third transistor (M3); inputting a voltage to the write signal line (WS), making conduction between the voltage dividing point and the common voltage line (VL); input voltage to the first data line (D/S) and the second data line respectively And the voltage is input to the voltage dividing point through the common voltage line, so that one of the resistance of the first memristor (ME1) and the second memristor (ME2) is greater than the resistance of the other A preset multiple, wherein the preset multiple is greater than 1 time. 7. The write operation method according to claim 6, characterized in that, in the content addressable storage unit circuit, the positive terminal of the first memristor (ME1) is connected to the positive end of the second memristor (ME2) ), or the negative terminal of the first memristor (ME1) is connected to the negative terminal of the second memristor (ME2); The first data line (D/S), the common voltage line (VL), the second data line The voltage on it decreases or increases sequentially. 8. The write operation method according to claim 7, characterized in that, the voltage on the common voltage line (VL) is the voltage on the first data line (D/S) and the voltage on the second data line The average value of the voltage on the 9. The writing operation method according to claim 6, characterized in that, the positive end of the first memristor (ME1) is connected to the negative end of the second memristor (ME2), or the first memristor (ME2) is connected to the negative end. The negative end of a memristor (ME1) is connected to the positive end of the second memristor (ME2); The first data line (D/S) and the second data line The voltages on both are greater than or less than the voltage on the common voltage line (VL). 10. A search operation method based on the content addressable storage unit circuit according to claim 1, characterized in that, the method comprises: input voltage to the write signal line (WS), so that the voltage dividing point is disconnected from the common voltage line (VL); input a high level to the matching line WL; input voltage to the first data line (D/S) and the second data line respectively Wherein the first data line (D/S) and the second data line The voltage of one of them is a high level, and the voltage of the other is a low level, so that the voltage division point A forms a high level or a low level; inputting a voltage to the search signal line (SS), making conduction between the voltage dividing point and the third transistor (M3); When the output line OP outputs a high level, it is determined that the data stored in the content addressable storage unit circuit is one between 0 and 1, otherwise it is determined that the data stored in the content addressable storage unit circuit is read Data is another between 0 and 1. 11. The search operation method according to claim 10, characterized in that, the input voltage is applied to the search signal line (SS), so that the conduction between the voltage dividing point and the third transistor (M3) , which previously also included: Input voltage to the search signal line (SS), so that the voltage dividing point is disconnected from the third transistor (M3).