CN106299109A - Complementary type resistance-variable storing device and non-destructive read out method thereof - Google Patents

Abstract

The invention discloses a kind of complementary type resistance-variable storing device, the electrochemical metallization memory element connected including the anti-series that two structures are identical；Electrochemical metallization memory element includes layers of active electrodes, resistance change material layer and the inert electrode layer that lamination is arranged successively；Wherein, when electrochemical metallization memory element is in high-impedance state, apply " reading " bias, the volatile Resistance states that electrochemical metallization memory element is between high-impedance state and low resistance state to layers of active electrodes；When cancelling " reading " bias, electrochemical metallization memory element is automatically restored to high-impedance state by volatile Resistance states；" read " to bias between the first positive threshold bias and the second positive threshold bias.The invention also discloses the non-destructive read out method of above-mentioned complementary type resistance-variable storing device.Complementary type resistance-variable storing device according to the present invention utilizes the electrochemical metallization memory element of single high-impedance state volatile nature under the proper, and using this feature as the gating device of intrinsic, it is achieved non-destructive reads.

Description

Complementary resistive memory and its non-destructive reading method

technical field

The invention belongs to the technical field of microelectronics, and in particular relates to a complementary resistive memory and a non-destructive reading method thereof.

Background technique

New types of memory based on semiconductor technology have been widely used in fields such as computers, digital equipment, and mobile storage. Traditional magnetic random dynamic memory and flash memory can no longer meet the requirements of high-density, high-speed, and large-capacity storage due to their physical size limitations; at present, resistive variable memory (RRAM) has strong Low power consumption and other characteristics have attracted extensive attention and research from research institutions and memory manufacturers at home and abroad.

The reason why the RRAM has the potential for miniaturization is that it can be made into a crossbar array (CrossbarArray) structure, that is, the bottom electrode and the top electrode are arranged in a cross, and the storage medium is placed between the upper and lower electrodes. This 3D memory architecture allows each memory cell to be reduced to a size of 4F ² /n (F is the feature size of the manufacturing process, and n is the number of layers of the cross array in the memory). However, the criss-cross array has a technical bottleneck problem in practical application, which is the crosstalk problem (Crosstalk Problem) between adjacent low-resistance state memory cells during operation. Therefore, solving the crosstalk problem of the criss-cross array is very important for the development and application of resistive memory.

In recent years, a concept of a complementary resistive switch memory (Complementary Resistive Switches, CRS) has been proposed to solve the crosstalk problem of the resistive switch memory in a criss-cross array. For CRS devices, binary 0 and 1 are realized through different combinations of high-resistance and low-resistance states of two anti-serial memory cells, and the resistance of the entire device is always in a high-resistance state, thus effectively solving the crosstalk problem. However, this complementary RRAM faces the difficulty of destructive reading in actual operation. The original data is destroyed in the process of reading information, and an additional "rewriting" link is needed to restore the original information after reading the information. This "rewriting" process will increase the reading time of the device and increase the power consumption of the device.

FIG. 1 is an I-V curve of a traditional complementary resistive memory.

Referring to FIG. 1 , the characteristic of the traditional complementary RRAM is that the device is within a suitable voltage range (V _th,3 <V<V _th,1 , where V _th,3 <0, V _th,1 >0, and |V _th,3 |≈|V _th,1 |) are all high-impedance states (hereinafter referred to as HRS), and have two HRS with opposite poles. One of the HRS can realize the transition from HRS to low-resistance state (hereinafter referred to as LRS) when the first positive threshold bias voltage (V _th,1 ) is applied, and the other HRS can realize the transition from the first negative threshold bias voltage (V _{th , 3} ) to realize the transition from HRS _{to LRS} ; (V _th,4 , where, V _th,4 <V _th,3 , and |V _th,4 |≈|V _th,2 |), the complementary resistive memory in LRS can be realized by LRS transition to HRS; therefore, the stable HRS defined in (V _th,4 , V _th,1 ) is the “1” state of the CRM, while in (V _th,3 , V _th,2 ) The stable HRS is the "0" state of the CRM; where "0" and "1" states can be identified by applying a "read" bias (V _th,1 <V<V _th,2 ) , the former ("0" state) remains HRS, while the latter ("1" state) becomes LRS. Among them, reading in the "1" state is destructive (the complementary resistive memory becomes LRS), so after reading, a "write" operation is required to restore the complementary resistive memory to "1"state;"erase" operation can be realized by applying a large forward bias voltage (V>V _th,2 ); "write" operation can be realized by applying a large negative bias voltage (V<V _th,4 ) . Similarly, the stable HRS within (V _th,3 , V _th,2 ) is the “1” state of the CRM, and the “read” bias must satisfy V _th,4 <V<V _{th, 3} , correspondingly, the “write” bias and the “erase” bias need to satisfy the conditions of V<V _th,4 and V>V _th,2 respectively. It is worth noting that when the complementary resistive memory is in the "1" state, a "read" bias is applied to it (V _th,1 <V<V _th,2 ), and the voltage is transmitted through the memory cell in LRS All applied to the memory cell in HRS, the memory cell in HRS becomes the LRS state, and the entire complementary resistive memory is in the LRS state, which is called the "ON" state.

FIG. 2 is a schematic diagram of the steps of the destructive reading method of the traditional complementary RRAM.

Referring to Fig. 2, when the initial state of the traditional complementary resistive variable memory is "0" state, and a "read" bias is applied to it, its state does not change, and no current is generated; continue to apply a "write" bias to it, and it is in The complementary resistive variable memory in the "0" state changes to the "1" state, and at the same time passes through the "ON" state in the middle, so a large current is generated; the third step is to apply the complementary resistive variable memory in the "1" state "Read" bias, the memory cell in HRS changes to the LRS state, correspondingly, a current is generated, and the entire complementary resistive variable memory becomes "ON" state; the fourth step is for the complementary resistive variable memory in the "ON" state The memory applies a "write" bias to restore it to the "1" state, so this step is called a "rewrite" operation, as shown in the dashed box in Figure 2.

After the traditional complementary resistive memory is read and written, its state changes to "ON" state. To make it change to "1" state again, it needs to apply a "write" bias to complete the "rewrite" operation. The "rewrite" operation reduces the reading speed of the complementary resistive variable memory and increases its working energy consumption. Therefore, realizing the non-destructive reading of the CRS device is of great significance for improving the lifespan of the CRS and the commercialization of the CRS.

Contents of the invention

In order to solve the above-mentioned problems in the prior art, the present invention provides a complementary resistive variable memory, which utilizes the volatile characteristics of a single high-resistance electrochemical metallization memory cell at an appropriate voltage, And using this feature as an intrinsic gating device, the non-destructive reading of the complementary resistive memory is realized.

In order to achieve the above-mentioned purpose of the invention, the present invention has adopted following technical scheme:

A complementary resistive variable memory, comprising two anti-series electrochemical metallized memory cells with the same structure; the electrochemical metallized memory cell includes an active electrode layer, a resistive material layer and an inert electrode stacked in sequence layer; wherein, when the electrochemical metallized memory cell is in a high resistance state, when a "read" bias is applied to the active electrode layer, the electrochemical metallized memory cell is in a state between a high resistance state and a low resistance state The volatile resistance state between; when the "read" bias is removed, the electrochemical metallization memory cell automatically recovers from the volatile resistance state to a high resistance state; the "read" bias is between the first forward threshold bias to the second positive threshold bias.

Further, the complementary resistive variable memory includes an inert electrode layer, a resistive material layer, an active electrode layer, an active electrode layer, a resistive material layer, and an inert electrode layer which are sequentially stacked.

Further, the complementary resistive variable memory includes an active electrode layer, a resistive material layer, an inert electrode layer, an inert electrode layer, a resistive material layer, and an active electrode layer that are sequentially stacked.

Further, the material of the active electrode layer is selected from any one of Ag, Cu and Ni.

Further, the material of the inert electrode layer is selected from any one of Pt, Pd and Au.

Further, the resistive material layer is selected from any one of GeS _x (0<x<2), AgS _x (0<x<0.5), ZrO ₂ , Ta ₂ O ₅ , and TiO ₂ .

Another object of the present invention is to provide a non-destructive reading method of a complementary resistive memory, which includes two electrochemical metallized memory cells connected in anti-series with the same structure, the The electrochemical metallization storage unit includes an active electrode layer, a resistive material layer and an inert electrode layer stacked in sequence; the non-destructive reading method includes the steps of: The active electrode layer applies a "read" bias, and the electrochemical metallization memory cell is in a volatile resistance state; when the "read" bias is removed, the electrochemical metallization memory cell is automatically restored from the volatile resistance state It is a high-resistance state; wherein, the volatile resistance state refers to a state in which the resistance of the electrochemical metallization memory cell is between a low-resistance state and a high-resistance state; the "read" bias is between the first forward threshold bias and the second positive-going threshold bias.

Further, the complementary resistive variable memory includes an inert electrode layer, a resistive material layer, an active electrode layer, an active electrode layer, a resistive material layer and an inert electrode layer which are sequentially stacked.

Further, the complementary resistive variable memory includes an active electrode layer, a resistive material layer, an inert electrode layer, an inert electrode layer, a resistive material layer, and an active electrode layer that are sequentially stacked.

Further, the material of the active electrode layer is selected from any one of Ag, Cu, Ni; the material of the inert electrode layer is selected from any one of Pt, Pd, Au; the resistive material layer is selected from Any one of GeS _x (0<x<2), AgS _x (0<x<0.5), ZrO ₂ , Ta ₂ O ₅ , and TiO ₂ .

The present invention prepares a complementary resistive memory that can realize non-destructive reading by connecting two electrochemical metallization memory cells with the same structure in anti-series, which can effectively avoid the destructive reading of traditional complementary memory problem, significantly improving the read rate and reducing device power consumption; at the same time, the complementary resistive memory according to the present invention does not require additional selection devices, has a simple structure, and is of great value for the development of complementary resistive memory.

Description of drawings

The above and other aspects, features and advantages of embodiments of the present invention will become more apparent through the following description in conjunction with the accompanying drawings, in which:

Fig. 1 is the I-V curve of the traditional complementary resistive variable memory;

Fig. 2 is a schematic diagram of steps of a destructive reading method of a traditional complementary resistive variable memory;

3 is a schematic structural diagram of a complementary resistive memory according to an embodiment of the present invention;

Fig. 4 is the volatile I-V curve of a single electrochemical metallization memory cell of a complementary resistive variable memory at a relatively small voltage according to an embodiment of the present invention;

FIG. 5 is a schematic diagram of steps of a non-destructive reading method of a complementary resistive random access memory according to an embodiment of the present invention.

detailed description

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. This invention may, however, be embodied in many different forms and should not be construed as limited to the specific embodiments set forth herein. Rather, the embodiments are provided to explain the principles of the invention and its practical application, thereby enabling others skilled in the art to understand the invention for various embodiments and with various modifications as are suited to particular intended uses. In the drawings, the shapes and dimensions of elements may be exaggerated for clarity, and the same reference numerals will be used throughout to designate the same or like elements.

FIG. 3 is a schematic structural diagram of a complementary RRAM according to an embodiment of the present invention.

Referring to FIG. 3 , a complementary resistive variable memory according to an embodiment of the present invention includes an inert electrode layer 110 , a resistive material layer 120 , an active electrode layer 130 , an active electrode layer 130 , a resistive material layer 120 and an inert electrode layer sequentially stacked. electrode layer 110 .

Specifically, in this embodiment, the material of the inert electrode layer 110 is metal Pt, the material of the resistive material layer 120 is TiO ₂ , and the material of the active electrode layer 130 is metal Cu; the thickness of the inert electrode layer 110 is 100 nm, and the resistance The thickness of the variable material layer 120 and the active electrode layer 130 is 50nm; but the present invention is not limited thereto, for example, the material of the inert electrode layer 110 can also be metals such as Pd, Au, and the material of the active electrode layer 130 can also be Ag, Ni and other metals, and the material of the resistive material layer 120 can also be GeS _x (0<x<2), AgS _x (0<x<0.5) and other sulfide solid electrolytes or ZrO ₂ , Ta ₂ O ₅ , etc. Oxide solid electrolyte; the thickness of the inert electrode layer 110 and the active electrode layer 130 is controlled within the range of 30nm-500nm, and the thickness of the resistive material layer 120 is controlled within the range of 5nm-100nm.

The preparation methods of the inert electrode layer 110 and the active electrode layer 130 may be electron beam evaporation, thermal evaporation, magnetron sputtering, etc., while the preparation method of the resistive material layer 120 may be chemical vapor deposition or physical vapor deposition. , electron beam evaporation method, sputtering method, atomic layer deposition method, thermal evaporation method, sol-gel method, etc. The above-mentioned preparation techniques of the inert electrode layer 110 , the resistive material layer 120 and the active electrode layer 130 are common methods used by those skilled in the art, and will not be described in detail here.

It is worth noting that the above complementary resistive variable memory is essentially obtained by anti-series connection of two electrochemical metallized memory cells (hereinafter referred to as ECM cells), wherein the structure of a single ECM cell is an inert electrode layer 110/resistive material layer 120/Active electrode layer 130. When a single ECM unit is in a high-resistance state, it is driven by an appropriate voltage, that is, when a positive threshold bias is applied to the active electrode layer 130, a conductive filament or a tunneling channel will be formed inside the resistive material layer 120, and the ECM unit The resistance of the wire will change from a high-resistance state to a volatile resistance state (hereinafter referred to as VRS) between a high-resistance state (hereinafter referred to as HRS) and a low-resistance state (hereinafter referred to as LRS); when the voltage is removed, the above-mentioned conductive filament Or the tunneling channel disappears, the ECM unit will recover from VRS to HRS spontaneously. Figure 4 shows the volatile IV curve of a single electrochemical metallization memory cell at a small voltage. It can be seen from Figure 4 that the initial state of the ECM cell is HRS, and the first positive threshold bias is applied to it At V _th,1 , the ECM cell transitions; during subsequent scan voltage drops, at a voltage of the second forward threshold bias V _th,2 , the ECM cell spontaneously reverts to HRS, exhibiting a diode-like The characteristics of the hysteresis curve, which shows that the resistance transition of the ECM unit is volatile at a specific voltage (V _th,1 <V<V _th,2 ), and the ECM unit in HRS is subjected to the first forward threshold Transition to VRS at bias V _th,1 .

FIG. 5 is a schematic diagram of steps of a non-destructive reading method of a complementary resistive random access memory according to an embodiment of the present invention.

Referring to Fig. 5, when the initial state of the complementary resistive variable memory is "0" state, the operation of the first two steps is the same as that of the destructive reading method of the traditional complementary resistive variable memory in Fig. 2, which is not repeated here repeat. The third step applies a "read" bias (V _th,1 <V<V _th,2 ) to the CRM in the "1" state after the first two steps, and the voltage acts directly through the ECM unit in the LRS On the ECM unit in HRS, because of its volatility, the ECM unit in HRS does not become LRS, but becomes VRS. When the "read" bias is cancelled, the ECM unit in VRS The ECM unit returns to HRS spontaneously, and the complementary resistive memory becomes "1" state again, but the process of restoring the ECM unit from VRS to HRS takes a certain time; continue to restore the complementary resistive memory to the "1" state Applying an "erase" bias (V>V _th,2 ) to the memory, the CRM in the "1" state changes to a "0" state, correspondingly, a current is generated.

The complementary RRAM according to the embodiment of the present invention utilizes the volatile characteristics of a single ECM cell, and when a "read" bias (V _th,1 <V<V _th,2 ) is applied to it, the entire complementary The RRAM does not change from the "1" state to the "ON" state, but automatically returns to the "1" state after the "read" bias is cancelled, thereby eliminating the need to apply a "write" bias (V <V _th,4 ) and the "rewrite" operation effectively avoids the problem of destructive reading of traditional complementary memory, significantly improves the read rate of complementary resistive memory, reduces power consumption, and is very important for realizing The 3D stacking of complementary resistive memory cells and the commercial application of general complementary resistive memory are of great significance.

It is worth noting that, in the above embodiments, the structure of the complementary resistive variable memory according to the embodiment of the present invention is an inert electrode layer 110, a resistive material layer 120, an active electrode layer 130, and an active electrode layer stacked in sequence. 130, the resistive variable material layer 120 and the inert electrode layer 110; but the present invention is not limited thereto, for example, in the present invention, the structure of the complementary resistive variable memory can also be the active electrode layer 130, resistive The variable material layer 120 , the inert electrode layer 110 , the inert electrode layer 110 , the resistive variable material layer 120 and the active electrode layer 130 .

Those skilled in the art will understand that, when two ECM units of the same structure are connected in anti-series, they may be adjacent to two identical active electrode layers 130 (as in the embodiment of the present invention), or two identical inert electrode layers 130 may be adjacent. The electrode layers 110 are adjacent, and two adjacent active electrode layers 130 or inert electrode layers 110 can be merged into one layer or one layer can be discarded, that is to say, two ECM units share the same active electrode layer 130 Or the inert electrode layer 140, so the structure of the complementary resistive variable memory according to the present invention can also be expressed as the inert electrode layer 110, the resistive material layer 120, the active electrode layer 130, the resistive material layer 120 and the inert The electrode layer 110 , or the active electrode layer 130 , the resistive material layer 120 , the inert electrode layer 110 , the resistive material layer 120 and the active electrode layer 130 are sequentially stacked.

The complementary resistive memory according to the embodiments of the present invention can realize non-destructive reading without additional selection devices, which not only simplifies the structure of the complementary resistive memory, but also helps to increase the read rate and reduce power consumption. It is of great value to the development of complementary resistive memory.

While the invention has been shown and described with reference to particular embodiments, it will be understood by those skilled in the art that changes may be made in the form and scope thereof without departing from the spirit and scope of the invention as defined by the claims and their equivalents. Various changes in details.

Claims (10)

1. A complementary resistive variable memory, characterized in that it comprises two anti-series electrochemical metallization storage cells identical in structure; A variable material layer and an inert electrode layer; wherein, when the electrochemical metallization memory cell is in a high resistance state, a "read" bias is applied to the active electrode layer, and the electrochemical metallization memory cell is in a high resistance state The volatile resistance state between the low resistance state and the low resistance state; when the "read" bias is removed, the electrochemical metallization memory cell is automatically restored to the high resistance state from the volatile resistance state; the "read" bias is between the first forward threshold bias and the second forward threshold bias. 2. The complementary resistive variable memory according to claim 1, characterized in that the complementary resistive variable memory comprises an inert electrode layer, a resistive variable material layer, an active electrode layer, an active electrode layer, Variable material layer and inert electrode layer. 3. The complementary resistive variable memory according to claim 1, characterized in that, the complementary resistive variable memory comprises an active electrode layer, a resistive variable material layer, an inert electrode layer, an inert electrode layer, a resistor Variable material layer and active electrode layer. 4. The complementary resistive variable memory according to any one of claims 1-3, characterized in that the material of the active electrode layer is selected from any one of Ag, Cu and Ni. 5. The complementary resistive variable memory according to claim 4, wherein the material of the inert electrode layer is selected from any one of Pt, Pd and Au. 6. The complementary resistive variable memory according to claim 5, wherein the resistive variable material layer is selected from GeS _x (0<x<2), AgS _x (0<x<0.5), ZrO ₂ , Any one of Ta ₂ O ₅ and TiO ₂ . 7. A non-destructive reading method of a complementary resistive variable memory, characterized in that the complementary resistive variable memory comprises two electrochemical metallized memory cells connected in anti-series with the same structure, and the electrochemical metallization The memory cell includes an active electrode layer, a resistive material layer and an inert electrode layer stacked in sequence; the non-destructive reading method includes steps: applying a "read" bias to the active electrode layer of said electrochemical metallized memory cell in a high resistance state, said electrochemical metallized memory cell in a volatile resistive state; canceling the "read" bias, and the electrochemical metallization memory cell is automatically restored to a high resistance state from a volatile resistance state; Wherein, the volatile resistance state refers to a state in which the resistance of the electrochemical metallization memory cell is between a low resistance state and a high resistance state; the "read" bias is between the first forward threshold bias and the second forward threshold bias. between forward threshold bias. 8. The non-destructive reading method according to claim 7, wherein the complementary resistive variable memory comprises an inert electrode layer, a resistive material layer, an active electrode layer, an active electrode layer, A resistive material layer and an inert electrode layer. 9. The non-destructive reading method according to claim 7, wherein the complementary resistive variable memory comprises an active electrode layer, a resistive material layer, an inert electrode layer, an inert electrode layer, A resistive material layer and an active electrode layer. 10. according to the non-destructive reading method described in any one of claim 7-9, it is characterized in that, the material of described active electrode layer is selected from any one in Ag, Cu, Ni; The material is selected from any one of Pt, Pd, and Au; the resistive material layer is selected from GeS _x (0<x<2), AgS _x (0<x<0.5), ZrO ₂ , Ta ₂ O ₅ , Any one of _TiO2 .