CN106298636B - A kind of control method of ultralow K dielectric material etching depth - Google Patents
A kind of control method of ultralow K dielectric material etching depth Download PDFInfo
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- 238000005530 etching Methods 0.000 title claims description 220
- 238000000034 method Methods 0.000 title claims description 67
- 239000003989 dielectric material Substances 0.000 title claims description 64
- 239000007789 gas Substances 0.000 claims description 111
- 239000000463 material Substances 0.000 claims description 16
- 238000005259 measurement Methods 0.000 claims description 9
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 claims description 5
- 229910052799 carbon Inorganic materials 0.000 claims description 5
- 229910052731 fluorine Inorganic materials 0.000 claims description 5
- 239000011737 fluorine Substances 0.000 claims description 5
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 claims description 4
- 230000008569 process Effects 0.000 description 20
- 230000008859 change Effects 0.000 description 9
- 238000005457 optimization Methods 0.000 description 9
- 238000010586 diagram Methods 0.000 description 5
- 238000005516 engineering process Methods 0.000 description 5
- 230000004907 flux Effects 0.000 description 4
- 239000002184 metal Substances 0.000 description 4
- 229910052751 metal Inorganic materials 0.000 description 4
- 229920000642 polymer Polymers 0.000 description 4
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 3
- 230000008901 benefit Effects 0.000 description 3
- 229910052802 copper Inorganic materials 0.000 description 3
- 239000010949 copper Substances 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 239000004065 semiconductor Substances 0.000 description 3
- 238000003070 Statistical process control Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 239000002245 particle Substances 0.000 description 2
- 238000001228 spectrum Methods 0.000 description 2
- 230000004075 alteration Effects 0.000 description 1
- 238000004458 analytical method Methods 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 150000001722 carbon compounds Chemical class 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000012937 correction Methods 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 239000002305 electric material Substances 0.000 description 1
- 238000005265 energy consumption Methods 0.000 description 1
- 230000003628 erosive effect Effects 0.000 description 1
- 238000002474 experimental method Methods 0.000 description 1
- 239000004744 fabric Substances 0.000 description 1
- 125000001153 fluoro group Chemical group F* 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000012544 monitoring process Methods 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 150000003384 small molecules Chemical class 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
- H01L21/31116—Etching inorganic layers by chemical means by dry-etching
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/67005—Apparatus not specifically provided for elsewhere
- H01L21/67242—Apparatus for monitoring, sorting or marking
- H01L21/67253—Process monitoring, e.g. flow or thickness monitoring
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- Power Engineering (AREA)
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Abstract
The present invention provides a kind of control method of ultralow K dielectric material etching depth, method includes the following steps: first, set the gas flow of etching gas on etching machine, the ultralow K layer of dielectric material on a wafer is etched using the etching gas, then measures the etching depth of the ultralow K layer of dielectric material of the wafer；Then, according to the etching depth of measurement, judge whether the etching depth deviates target depth by APC system；If the etching depth deviates the etching depth, by the gas flow parameter of the APC system output adjustment, etching machine adjusts etching gas flow according to the parameter, and then the etching depth of lower wafer is made to be more nearly the target depth.The present invention adjusts the flow of etching gas on board by APC feedback, and changes the etching depth of ultralow K dielectric material by the difference of etched flux between wafer and wafer, so that etching depth be made to meet technique requirement.
Description
Technical field
The present invention relates to field of semiconductor manufacture, more particularly to a kind of controlling party of ultralow K dielectric material etching depth
Method.
Background technique
As the node of complementary metal oxide semiconductor (CMOS) device is reduced to 28nm and hereinafter, is partly leading at present
In the last part technology of body manufacture, integrated circuit is constituted in order to connect all parts, usually using the gold with opposite high conductivity
Belong to material such as copper to be routed, that is, metal line.And be used to connect between metal line is usually conductive plunger.With
Conductive plunger is generally in the structure for connecting the active area of semiconductor devices and other integrated circuits.
When characteristic size reaches deep-submicron following technique, when making thin copper film or conductive plunger, it must use
As dielectric layer, (the ultralow k is less than or equal to the dielectric material of ultralow dielectric (Ultra low k, ULK) for dielectric constant
2.5), the advantage is that the K value of ultralow K dielectric material is lower, the interconnection capacitance of the interconnection structure constructed on chip is smaller, because
This, is if using ultralow K dielectric material as the isolation medium of different circuit layers, the influence of RC retardation ratio just very little.Existing
During forming thin copper film or conductive plunger, groove or through-hole are formed by etching ultralow K dielectric material, then in groove
Or conductive materials are filled in through-hole.
Etching depth is generally controlled by etch period in the prior art, when the time for reaching setting, is then automatically stopped
Etching operation, the etching depth of ultralow K dielectric material is target depth at this time.But general used etching gas is
Small molecule single carbon fluoro-gas (CF4) when, the etching depth situation in a linear relationship with etch period is just had, quarter could be relied on
The erosion time controls the etching depth, as shown in Figure 1.The many because being known as of etch rate stability are influenced, for example, chamber ring
Border, etc., when being influenced in etching process by various factors, etching depth is not changing linearly then at any time.In ultralow K
In the etching technics of dielectric material, when etching depth is not changed linearly with the process time, then be difficult with the process time come
Control etching depth.
Currently, if when ultralow K dielectric material is as side wall protection structure, using macromolecular etching gas, such as C4F8, into
Row etching, but the etching depth of this etching gas is not changed linearly with etch period, as shown in Figure 2.Therefore, for
C4F8Such macromolecular etching gas, then be difficult to have etch period to control etching depth.
Therefore it provides a kind of control method of new ultralow K dielectric material etching depth is those skilled in the art's needs
The project of solution.
Summary of the invention
In view of the foregoing deficiencies of prior art, the purpose of the present invention is to provide a kind of ultralow K dielectric materials to etch
The control method of depth can not use the time during etching ultralow K dielectric material for solving etching gas in the prior art
Come the problem of controlling etching depth.
In order to achieve the above objects and other related objects, the present invention provides a kind of control of ultralow K dielectric material etching depth
Method processed, the control method include at least:
The gas flow for setting etching gas on etching machine etches the ultralow K on a wafer using the etching gas and is situated between
Then the material bed of material measures the etching depth of the ultralow K layer of dielectric material of the wafer；
According to the etching depth of measurement, judge whether the etching depth deviates target depth by APC system, if
The etching depth is equal to the target depth, then descends wafer using the etching gas with upper wafer same gas flow
Body；If the etching depth deviates the etching depth, by the gas flow parameter of the APC system output adjustment, etching
Machine adjusts etching gas flow according to the parameter, and then it is deep so that the etching depth of lower wafer is more nearly the target
Degree.
A kind of scheme of optimization of control method as the ultralow K dielectric material etching depth of the present invention, the ultralow K are situated between
The etching depth of the material bed of material is in nonlinear change with etch period.
A kind of scheme of optimization of control method as the ultralow K dielectric material etching depth of the present invention, the ultralow K are situated between
The etching depth and gas flow of the material bed of material are in the linear relationship of inverse ratio.
The scheme of a kind of optimization of control method as the ultralow K dielectric material etching depth of the present invention, if a upper platelet
Round etching depth is greater than target depth, then by APC control system according to the linear relationship of the etching depth and gas flow,
The flow of the etching gas of lower wafer is tuned up；If the etching depth of upper wafer is less than target depth, controlled by APC
System processed turns the flow of the etching gas of lower wafer down according to the linear relationship of the etching depth and gas flow.
A kind of scheme of optimization of control method as the ultralow K dielectric material etching depth of the present invention, is measured using OCD
System measures the etching depth of the ultralow K layer of dielectric material of the wafer.
A kind of scheme of optimization of control method as the ultralow K dielectric material etching depth of the present invention, the ultralow K are situated between
The dielectric constant of the material bed of material is less than 2.6.
A kind of scheme of optimization of control method as the ultralow K dielectric material etching depth of the present invention, etches a platelet
The round time is more than 30s.
A kind of scheme of optimization of control method as the ultralow K dielectric material etching depth of the present invention, the etching gas
Body is fluorine-containing more carbon gases.
A kind of scheme of optimization of control method as the ultralow K dielectric material etching depth of the present invention, the etching gas
Body is C4F8、C4F6Or C5F6One of or a variety of combinations.
A kind of scheme of optimization of control method as the ultralow K dielectric material etching depth of the present invention, the etching gas
The range of flow of gas is 25~40sccm.
As described above, the control method of ultralow K dielectric material etching depth of the invention, this method comprises: firstly, setting
The gas flow of etching gas on etching machine etches the ultralow K layer of dielectric material on a wafer using the etching gas, then
Measure the etching depth of the ultralow K layer of dielectric material of the wafer；Then, according to the etching depth of measurement, by APC system
Judge whether the etching depth deviates target depth, if the etching depth is equal to the target depth, next platelet
Circle is using the etching gas with upper wafer same gas flow；If the etching depth deviates the etching depth, by
The gas flow parameter of the APC system output adjustment, etching machine adjusts etching gas flow according to the parameter, and then makes
The etching depth of lower wafer is more nearly the target depth.The present invention etches gas by APC feedback to adjust on board
The flow of body, and change by the difference of etched flux between wafer and wafer the etching depth of ultralow K dielectric material, to make
Etching depth meets technique requirement.
Detailed description of the invention
Fig. 1 is CF in the prior art4The etching depth of etching gas with the process time variation schematic diagram.
Fig. 2 is C in the prior art4F8The etching depth of etching gas with the process time variation schematic diagram.
Fig. 3 is the ultralow K dielectric material etching depth control method flow chart of the present invention.
Fig. 4 is different flow C in the present invention4F8Etching gas etches remaining depth with the variation schematic diagram of process time.
Fig. 5 is C in the present invention4F8The etching depth of etching gas with gas flow variation schematic diagram.
Specific embodiment
Illustrate embodiments of the present invention below by way of specific specific example, those skilled in the art can be by this specification
Other advantages and efficacy of the present invention can be easily understood for disclosed content.The present invention can also pass through in addition different specific realities
The mode of applying is embodied or practiced, the various details in this specification can also based on different viewpoints and application, without departing from
Various modifications or alterations are carried out under spirit of the invention.
Please refer to attached drawing.It should be noted that only the invention is illustrated in a schematic way for diagram provided in the present embodiment
Basic conception, only shown in schema then with related component in the present invention rather than component count, shape when according to actual implementation
Shape and size are drawn, when actual implementation kenel, quantity and the ratio of each component can arbitrarily change for one kind, and its component cloth
Office's kenel may also be increasingly complex.
In deep-submicron technique below, when making metal line or conductive plunger in last part technology, it is situated between using ultralow K
During electric material is as dielectric layer, inventors have found that if using fluorine-containing more carbon etching gas (such as C4F8) etch period
Control the etching depth (i.e. time reach in setting time then stop etching) of dielectric material, then it is when reaching etch period, super
The etching depth of low-K dielectric material is not the etching depth reached required by technique or the depth as shallow than technique requirement,
Than depth required by technique.In consideration of it, the present invention provides a kind of control method, this method is controlled by control etched flux
The offset of through-hole or etching groove in ultralow K dielectric material can be effectively reduced in the depth of etching.
The present invention provides a kind of control method of ultralow K dielectric material etching depth, as shown in figure 3, the control method
Including at least following steps:
The gas flow for setting etching gas on etching machine etches the ultralow K on a wafer using the etching gas and is situated between
Then the material bed of material measures the etching depth of the ultralow K layer of dielectric material of the wafer；
According to the etching depth of measurement, judge whether the etching depth deviates target depth by APC system, if
The etching depth is equal to the target depth, then descends wafer using the etching gas with upper wafer same gas flow
Body；If the etching depth deviates the etching depth, by the gas flow parameter of the APC system output adjustment, etching
Machine adjusts etching gas flow according to the parameter, and then it is deep so that the etching depth of lower wafer is more nearly the target
Degree.
The control method of ultralow K dielectric material etching depth of the invention is discussed in detail below with reference to specific attached drawing.
Step 1 is first carried out, sets the gas flow of etching gas on etching machine, utilizes etching gas etching one
Then ultralow K layer of dielectric material on wafer measures the etching depth of the ultralow K layer of dielectric material of the wafer.
Etching mode of the invention is related to dry etching, and etching gas is activated under certain condition in active particle, benefit
With the effect of active particle physically or chemically, the shape of required groove or through-hole is etched in layer to be etched.
It is necessary to have good electrical isolations as the barrier material between metal interconnecting wires for the ultralow K layer of dielectric material
Performance, ultralow K dielectric material can be achieved by increasing the modes such as loose hole on the basis of low-K dielectric material.It is described
The dielectric constant of ultralow K layer of dielectric material is below 2.6.
The etching gas can choose fluorine-containing more carbon compound gases, such as C4F8、C4F6Or C5F6One of or
A variety of combinations.Certainly, the etching gas can also be other gases suitable for the ultralow K dielectric material of etching, herein
Unlimited, in the present embodiment, the etching gas is C4F8Gas.
The gas flow of the etching gas is selected at 25~40sccm (standard milliliters per minute).Preferably, the quarter
The gas flow for losing gas controls within the scope of 17~27sccm.
In the present embodiment, it is preferred to use OCD (optical feature dimension measurement) measures the etching depth of wafer.OCD can be with
The surface of ultralow K layer of dielectric material to be etched is projected light beams upon, one group of spectrum line, the spectrum are obtained by reflected light later
Information comprising measurement part in line.
Then step 2 is executed, according to the etching depth of measurement, the etching depth is judged by APC system whether
Deviate target depth, if the etching depth is equal to the target depth, lower wafer is using identical as upper wafer
The etching gas of gas flow；If the etching depth deviates the etching depth, by the gas of the APC system output adjustment
Body flow parameter, etching machine adjust etching gas flow according to the parameter, and then make the etching depth of lower wafer more
The closely described target depth of adjunction.
It should be noted that curve graph as shown in Figure 4 can be obtained according to the experimental result of batch wafer.Wherein, scheme
4 be with etching gas C4F8For, the ordinate in the figure indicates to etch remaining depth, i.e. etching gas eats up some ultra-low K Jie
Material rear surface is with a distance from target depth；Abscissa indicates the process time.As can be seen from Figure 4 C4F8Ultralow K is etched to be situated between
The etching residue depth of the material bed of material is in nonlinear change with the entire process time.If the process time, curve was basic less than 30
It changes linearly, after 30 seconds, curve is gentle, etches remaining depth and does not change again at any time substantially.Therefore, for technique
Etching technics of the time less than 30 seconds is controlled using the process time and etches remaining depth.And being directed in the present embodiment is work
Etching process of the skill time at 30 seconds or more, whole process are in nonlinear change, cannot control etching using the process time again
Remaining depth.Subtract the remaining depth of etching since etching depth is equal to target depth, so etching depth also should be with the process time
In nonlinear change.In addition, uppermost solid line indicates that flow is the etching gas of 25sccm, and intermediate lines indicate in Fig. 4
The etching gas of 22sccm, nethermost lines indicate the etching gas of 20sccm, it can be seen that the variation of this three curves becomes
Gesture is identical, and etching gas flow is smaller, and it is smaller (i.e. etching depth is then bigger) to etch remaining depth.
In addition, obtaining relationship as shown in Figure 5 according to the experiment of early period, ordinate is etching depth, abscissa in the figure
For the etched flux of etching gas, the etching depth and gas flow of ultralow K layer of dielectric material are in the linear relationship of inverse ratio, i.e. gas
Body flow is bigger, etches more shallow；Gas flow is smaller, etches deeper.The reason of why will appear inverse relation is, fluorine-containing
More carbon macromolecular etching gas (such as C4F8And C4F6) when etching ultralow K layer of dielectric material (ULK), it can generate a large amount of more
Polymers (Polymer), polymer can be gathered in channel bottom, slow down trench etch rate, possibly even make under serious situation
Stop at etching groove, so reducing gas flow is actually the amount for reducing polymer and generating, the blocking of etching groove is made
With reduction, the rate of etching is improved, carves deeper.The data of these etching depths and gas flow be transferred to APC system by
APC system storage.
APC system combines statistical process control (SPC) and feedback control (Feedback Control), and utilization is past
Process data predicts the parameter setting of next group processing procedure, can so reduce process variation caused by a variety of causes.
The purpose of APC system is to solve the problems, such as parameters and performance indicator drift in technical process, shorten measurement institute
Take time, timely correction error, its implementation help to improve productivity, reduce energy consumption, improve product quality and continuity, with
And improve the safety etc. of technique, so that process equipment can be realized stringenter process window, meet future 28nm technology
The requirement of node or following technology, effective monitoring technical process and board, to improve yield and overall device efficiency.
After the completion of the etching technics of upper wafer, the etching depth data of the wafer, APC system are acquired by APC
Discriminatory analysis is carried out to the etching depth of collection according to the interior formula set or Rule of judgment, sees whether the etching depth deviates
Target depth, if the etching depth just rests at the target depth, lower wafer is used and upper wafer
The etching gas of same gas flow, i.e. gas flow do not change.If the etching depth deviates the etching depth, by institute
The gas flow parameter of APC system output adjustment is stated, etching machine adjusts etching gas flow according to the parameter, and then under making
The etching depth of wafer is more nearly the target depth.Specifically, if the etching depth of upper wafer is greater than target
Depth (crosses quarter over-etch), then by APC control system according to the linear pass of etching depth as shown in Figure 5 and gas flow
System, the flow of the etching gas of lower wafer is tuned up；If it is (at once shallow that the etching depth of upper wafer is less than target depth
), then by APC control system according to the linear relationship of the etching depth and gas flow as shown in Figure 5, by lower wafer
The flow of etching gas turn down.
It can be seen that the etching depth and gas stream of the above wafer of selection of every wafer etching gas flow
Amount is reference basis, and suitable gas flow parameter is exported by APC system, which is transferred to etching machine, makes etching machine
Be adjusted to corresponding gas flow, so controlled by gas flow current wafer etch ultralow K layer of dielectric material etching it is deep
Degree, to meet technique requirement.
In conclusion the present invention provides a kind of control method of ultralow K dielectric material etching depth, this method includes following
Step: firstly, setting the gas flow of etching gas on etching machine, the etching gas is utilized to etch the ultralow K on a wafer
Then layer of dielectric material measures the etching depth of the ultralow K layer of dielectric material of the wafer；Then, according to the quarter of measurement
Depth is lost, judges whether the etching depth deviates target depth by APC system；If the etching depth deviates the etching
Depth, then by the gas flow parameter of the APC system output adjustment, etching machine adjusts etching gas stream according to the parameter
Amount, and then the etching depth of lower wafer is made to be more nearly the target depth.The present invention adjusts board by APC feedback
The flow of upper etching gas, and the etching for changing by the difference of etched flux between wafer and wafer ultralow K dielectric material is deep
Degree, so that etching depth be made to meet technique requirement.
So the present invention effectively overcomes various shortcoming in the prior art and has high industrial utilization value.
The above-described embodiments merely illustrate the principles and effects of the present invention, and is not intended to limit the present invention.It is any ripe
The personage for knowing this technology all without departing from the spirit and scope of the present invention, carries out modifications and changes to above-described embodiment.Cause
This, institute is complete without departing from the spirit and technical ideas disclosed in the present invention by those of ordinary skill in the art such as
At all equivalent modifications or change, should be covered by the claims of the present invention.
Claims (8)
1. a kind of control method of ultralow K dielectric material etching depth, which is characterized in that the control method includes at least:
The gas flow for setting etching gas on etching machine etches the super low-K dielectric material on a wafer using the etching gas
The bed of material, then measures the etching depth of the ultralow K layer of dielectric material of the wafer, and the etching of the ultralow K layer of dielectric material is deep
Degree is with gas flow in the linear relationship of inverse ratio；
According to the etching depth of measurement, judge whether the etching depth deviates target depth by APC system, if described
Etching depth is equal to the target depth, then descends wafer using the etching gas with upper wafer same gas flow；
If the etching depth deviates the etching depth, by the gas flow parameter of the APC system output adjustment, etching machine root
Etching gas flow is adjusted according to the parameter, and then the etching depth of lower wafer is made to be more nearly the target depth.
2. the control method of ultralow K dielectric material etching depth according to claim 1, it is characterised in that: if upper a piece of
The etching depth of wafer is greater than target depth, then by APC control system according to the linear pass of the etching depth and gas flow
System, the flow of the etching gas of lower wafer is tuned up；If the etching depth of upper wafer is less than target depth, by
APC control system is according to the linear relationship of the etching depth and gas flow, by the flow of the etching gas of lower wafer
It turns down.
3. the control method of ultralow K dielectric material etching depth according to claim 1, it is characterised in that: surveyed using OCD
Amount system measures the etching depth of the ultralow K layer of dielectric material of the wafer.
4. the control method of ultralow K dielectric material etching depth according to claim 1, it is characterised in that: the ultralow K
The dielectric constant of layer of dielectric material is less than 2.6.
5. the control method of ultralow K dielectric material etching depth according to claim 1, it is characterised in that: etching is a piece of
The time of wafer is more than 30s.
6. the control method of ultralow K dielectric material etching depth according to claim 1, it is characterised in that: the etching
Gas is fluorine-containing more carbon gases.
7. the control method of ultralow K dielectric material etching depth according to claim 6, it is characterised in that: the etching
Gas is C4F8、C4F6Or C5F6One of or a variety of combinations.
8. the control method of ultralow K dielectric material etching depth according to claim 1, it is characterised in that: the etching
The range of flow of gas is 25~40sccm.
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| CN107378232B (en) * | 2017-07-14 | 2019-03-15 | 中国科学院微电子研究所 | Method and system for processing wafer by laser |
| CN112490123B (en) * | 2020-11-20 | 2024-05-17 | 北京北方华创微电子装备有限公司 | Complementary etching method and semiconductor etching equipment |
| CN114481333B (en) * | 2022-02-16 | 2023-10-03 | 淮安纳微传感器有限公司 | Sensor monocrystalline silicon etching quality monitoring method |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1518759A (en) * | 2001-06-22 | 2004-08-04 | 东京毅力科创株式会社 | dry etching method |
| CN101599433A (en) * | 2008-06-03 | 2009-12-09 | 中芯国际集成电路制造(北京)有限公司 | Semiconductor etching method and etching system |
| JP2011040601A (en) * | 2009-08-12 | 2011-02-24 | Renesas Electronics Corp | Method of manufacturing semiconductor device |
| CN103915378A (en) * | 2014-04-08 | 2014-07-09 | 上海华力微电子有限公司 | Etching method for improving uniformity of contact hole line width |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9887071B2 (en) * | 2011-12-16 | 2018-02-06 | Taiwan Semiconductor Manufacturing Co., Ltd. | Multi-zone EPD detectors |
-
2015
- 2015-05-22 CN CN201510266174.7A patent/CN106298636B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1518759A (en) * | 2001-06-22 | 2004-08-04 | 东京毅力科创株式会社 | dry etching method |
| CN101599433A (en) * | 2008-06-03 | 2009-12-09 | 中芯国际集成电路制造(北京)有限公司 | Semiconductor etching method and etching system |
| JP2011040601A (en) * | 2009-08-12 | 2011-02-24 | Renesas Electronics Corp | Method of manufacturing semiconductor device |
| CN103915378A (en) * | 2014-04-08 | 2014-07-09 | 上海华力微电子有限公司 | Etching method for improving uniformity of contact hole line width |
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