CN106257647A - Embed the manufacture method of the CMOS of PIP capacitor - Google Patents

Abstract

The invention relates to a method for manufacturing a CMOS embedded in a PIP capacitor, comprising: depositing a sidewall oxide layer, etching the sidewall oxide layer, and forming sidewalls on both sides of the lower plate and both sides of the gate of the PIP capacitor The process is placed before the deposition of the dielectric layer and the second polysilicon layer, so that the dielectric layer and the second polysilicon layer are deposited, and the dielectric layer and the second polysilicon layer are etched to form the dielectric of the PIP capacitor layer and the upper plate of the PIP capacitor, due to the existence of sidewalls, it is avoided to form the residue of the dielectric layer and the second polysilicon layer at the sidewall of the lower plate of the PIP capacitor, thereby improving the reliability of the CMOS semiconductor. A function to prevent noise emission and a function to prevent frequency modulation.

Description

Manufacturing method of CMOS embedded with PIP capacitor

technical field

The invention relates to the technical field of semiconductors, in particular to a method for manufacturing a CMOS embedded with a PIP capacitor.

Background technique

At present, hybrid complementary metal oxide semiconductor field effect transistors (Complementary Metal Oxide Semiconductor, CMOS) include: N-type metal oxide semiconductor field effect transistors (N-Mental-Oxide-Semiconductor, NMOS), P channel metal oxide Semiconductor Field Effect Transistor (Positive channel Metal Oxide Semiconductor, PMOS). Wherein, the NMOS transistor is provided with polysilicon-insulator-polysilicon capacitor (Polysilicon-Insulator-Polysilicon, PIP), and the NMOS transistor and the PMOS transistor are connected by metal wires to form a hybrid CMOS transistor.

In the prior art, the manufacturing method of the CMOS embedded in the PIP capacitor includes: sequentially generating the substrate, the well region, the field oxide layer, the gate oxide layer, the lower plate of the PIP capacitor, the dielectric layer of the PIP capacitor, and the upper pole of the PIP capacitor plate, N type lightly doped drain (N type Lightly Doped Drain, NLDD), side walls, source and drain regions, hole layer, metal wiring layer.

However, in the prior art, as shown in Figure 1, after generating the first polysilicon layer 5 as the lower plate of the PIP capacitor, a dielectric layer 12 is deposited on the surface of the entire device, and a second polysilicon layer is deposited on the dielectric layer. The crystalline silicon layer is used to etch the dielectric layer and the second polysilicon layer to form the dielectric layer and the upper plate 13 of the PIP capacitor. Since the lower plate of the PIP capacitor is stepped, after the dielectric layer and the second polysilicon layer are etched, the sidewall of the lower plate of the PIP capacitor is covered with part of the dielectric layer and part of the second polysilicon layer. The crystalline silicon layer, as shown in FIG. 1, forms a dielectric layer residue 14 and a polysilicon residue 15, which affect the function of preventing noise emission and preventing frequency modulation of the CMOS field effect transistor.

Contents of the invention

The invention provides a method for manufacturing a CMOS embedded with a PIP capacitor, which is used to solve the problem that the existing CMOS embedded with a PIP capacitor has poor functions of preventing noise emission and preventing frequency modulation.

The first aspect of the present invention is to provide a method for manufacturing N-type metal oxide semiconductor in CMOS, including:

Define an active region on the substrate formed with the well region, grow a field oxide layer on the surface of the substrate other than the region corresponding to the active region, and grow a gate oxide layer on the surface of the substrate corresponding to the active region ;

Deposit the first polysilicon layer on the entire device surface, etch the first polysilicon layer, retain the first polysilicon layer on the surface of the partial area near the periphery of the field oxide layer, and the first polysilicon layer on the surface of the gate oxide layer The first polysilicon layer on the surface of some areas to form the lower plate and gate of the PIP capacitor respectively;

forming lightly doped drains in the substrate surface on both sides of the gate by implanting ions;

Depositing a sidewall oxide layer on the entire device surface, etching the sidewall oxide layer, and forming sidewalls on both sides of the first layer of polysilicon and both sides of the gate;

Forming source and drain regions by implanting ions;

A dielectric layer and a second polysilicon layer are sequentially deposited on the surface of a part of the lower plate of the PIP capacitor to form the dielectric layer and the upper plate of the PIP capacitor respectively;

Carry out hole layer fabrication and metal wiring.

Further, a dielectric layer and a second polysilicon layer are sequentially deposited on the surface of a part of the lower plate of the PIP capacitor, including:

sequentially depositing a dielectric layer and a second polysilicon layer over the entire device surface;

Etching the dielectric layer and the second polysilicon layer, retaining the dielectric layer and the second polysilicon layer on the surface of a part of the lower plate of the PIP capacitor.

Further, the formation of lightly doped drains located in the substrate surface on both sides of the gate by implanting ions includes:

Coating a photoresist layer over the entire surface of the device;

performing photolithographic development on the photoresist layer to form ion implantation windows on both sides of the gate;

implanting ions into the ion implantation window to form the lightly doped drain located in the substrate surface on both sides of the gate;

Remove remaining photoresist layer.

Further, the dielectric layer and the second polysilicon layer are etched, and the dielectric layer and the second polysilicon layer on the surface of a part of the lower plate of the PIP capacitor are retained, including:

Coating a photoresist layer over the entire device surface;

Carrying out photolithographic development to the photoresist layer, retaining the photoresist layer on the surface of a part of the lower plate of the PIP capacitor;

The dielectric layer and the second polysilicon layer are etched under the barrier of the photoresist layer, so as to reserve the dielectric layer and the second polysilicon layer on the surface of a part of the lower plate of the PIP capacitor layer;

Remove remaining photoresist layer.

Further, the thickness of the sidewall oxide layer is 1500-4000 angstroms

Further, the dielectric layer is a silicon dioxide layer, a silicon nitride layer, or a mixed layer of silicon dioxide and silicon nitride.

Further, the thickness of the dielectric layer is 200-700 angstroms.

Further, the thickness of the second polysilicon layer of the PIP capacitor is 2000-5000 angstroms.

Further, the etching the sidewall oxide layer includes:

performing dry etching on the side wall oxide layer.

In the present invention, the process of depositing the sidewall oxide layer, etching the sidewall oxide layer, and forming sidewalls on both sides of the lower plate and both sides of the gate of the PIP capacitor is placed in the process of depositing the dielectric layer and the second polycrystalline Before the silicon layer, thus in the process of depositing the dielectric layer and the second polysilicon layer, etching the dielectric layer and the second polysilicon layer to form the dielectric layer of the PIP capacitor and the upper plate of the PIP capacitor, Due to the existence of the side wall, the dielectric layer and the residue of the second polysilicon layer are avoided at the side wall of the lower plate of the PIP capacitor, thereby improving the function of preventing noise emission and frequency modulation of the CMOS semiconductor.

Description of drawings

1 is a schematic diagram of a dielectric layer and polysilicon residues on a CMOS field effect transistor in the prior art;

Fig. 2 is the flow chart of the manufacturing method of the CMOS of embedding PIP electric capacity provided by the present invention;

Figure 3 is to define the active region on the substrate with the well region, grow a field oxide layer on the substrate surface except the region corresponding to the active region, and grow a gate oxide layer on the substrate surface corresponding to the active region Schematic diagram of CMOS embedded with PIP capacitor;

Fig. 4 is the schematic diagram of the CMOS embedded in the PIP capacitor after forming the lower pole plate and the gate of the PIP capacitor;

5 is a schematic diagram of a CMOS embedded with a PIP capacitor after forming an N-type lightly doped drain NLDD;

6 is a schematic diagram of a CMOS embedded with a PIP capacitor after depositing a sidewall oxide layer;

7 is a schematic diagram of a CMOS embedded with a PIP capacitor after etching the sidewall oxide layer and forming sidewalls on both sides of the first layer of polysilicon and both sides of the gate;

8 is a schematic diagram of a CMOS embedded with a PIP capacitor after forming a source region and a drain region;

9 is a schematic diagram of a CMOS embedded with a PIP capacitor after depositing a dielectric layer;

10 is a schematic diagram of depositing a second polysilicon layer to embed a CMOS of a PIP capacitor;

11 is a schematic diagram of a CMOS embedded with a PIP capacitor after etching the dielectric layer and the polysilicon layer to form the dielectric layer of the PIP capacitor and the upper plate of the PIP capacitor.

detailed description

In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments It is a part of embodiments of the present invention, but not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts belong to the protection scope of the present invention.

Fig. 2 is the flow chart of the manufacturing method of the CMOS embedded PIP electric capacity provided by the present invention, as shown in Fig. 2, specifically comprises the following steps:

201. Define an active region on a substrate formed with a well region, grow a field oxide layer on the surface of the substrate except the region corresponding to the active region, and grow a gate oxide layer on the surface of the substrate corresponding to the active region.

Wherein, as shown in FIG. 3, in order to define an active region on the substrate 1 formed with the well region 2, a field oxide layer 3 is grown on the substrate surface except the region corresponding to the active region, and the active region corresponds to A schematic diagram of a CMOS embedded with a PIP capacitor after growing a gate oxide layer 4 on the surface of the substrate.

202. Deposit a first polysilicon layer on the entire device surface, etch the first polysilicon layer, retain the first polysilicon layer on the surface of a part of the field oxide layer near the periphery, and the gate oxide layer The first polysilicon layer on the surface of a part of the area to form the lower plate 5 and the gate 6 of the PIP capacitor respectively.

Wherein, the manner of etching the first polysilicon layer is photoetching. As shown in FIG. 4 , it is a schematic diagram of a CMOS embedded with a PIP capacitor after forming the lower plate and the gate of the PIP capacitor.

203 . Form lightly doped drains 7 located in the substrate surface on both sides of the gate 6 by implanting ions.

Wherein, step 203 may specifically include: coating a photoresist layer on the surface of the entire device; performing photolithography and development on the photoresist layer to form ion implantation windows on both sides of the gate; implanting ions into the ion implantation windows to form lightly doped drain in the substrate surface on the side; remove the remaining photoresist layer.

The purpose of forming the N-type lightly doped drain NLDD is to prevent hot carrier injection between the source region or the drain region and the gate. As shown in FIG. 5 , it is a schematic diagram of a CMOS embedded with a PIP capacitor after forming an N-type lightly doped drain NLDD.

204. Deposit a sidewall oxide layer 8 on the entire device surface, etch the sidewall oxide layer, and form sidewalls 9 on both sides of the first layer of polysilicon and both sides of the gate.

Wherein, the thickness of the sidewall oxide layer is 1500-4000 angstroms. As shown in FIG. 6 , it is a schematic diagram of a CMOS embedded with a PIP capacitor after depositing a sidewall oxide layer. As shown in FIG. 7 , in order to etch the sidewall oxide layer, the sidewalls are formed on both sides of the first layer of polysilicon and both sides of the gate, and then a schematic diagram of a CMOS embedded with a PIP capacitor.

Wherein, the method of growing the sidewall oxide layer may be chemical vapor deposition, and the method of etching the sidewall oxide layer may be dry etching.

205. Form the source region 10 and the drain region 11 by implanting ions.

Among them, after forming sidewalls on both sides of the first layer of polysilicon and both sides of the gate, ions are implanted into the well region through the gate oxide layer on both sides of the gate, so that the N-type lightly doped drain in the well region under the sidewall can be retained NLDD. As shown in FIG. 8 , it is a schematic diagram of a CMOS embedded with a PIP capacitor after forming a source region and a drain region.

206 . Deposit a dielectric layer and a second polysilicon layer sequentially on a partial area surface of the lower plate of the PIP capacitor to form the dielectric layer 12 and the upper plate 13 of the PIP capacitor respectively.

Wherein, the dielectric layer is a silicon dioxide layer, a silicon nitride layer, or a mixed layer of silicon dioxide and silicon nitride. The thickness of the dielectric layer is 200-700 Angstroms. The thickness of the second polysilicon layer of the PIP capacitor is 2000-5000 Angstroms.

Step 206 may specifically include: sequentially depositing a dielectric layer and a second polysilicon layer on the entire device surface; etching the dielectric layer and the second polysilicon layer, and reserving a part of the lower plate of the PIP capacitor Dielectric layer and second polysilicon layer on the surface.

As shown in FIG. 9 , it is a schematic diagram of a CMOS embedded with a PIP capacitor after depositing a dielectric layer. As shown in FIG. 10 , it is a schematic diagram of depositing the second polysilicon layer to embed the CMOS of the PIP capacitor. As shown in FIG. 11 , it is a schematic diagram of a CMOS embedded in a PIP capacitor after etching the dielectric layer and the polysilicon layer to form the dielectric layer of the PIP capacitor and the upper plate of the PIP capacitor.

Among them, the process of etching the dielectric layer and the polysilicon layer can be specifically, coating the photoresist layer on the entire device surface; performing photolithography and development on the photoresist layer, and retaining it on the surface of a part of the lower plate of the PIP capacitor The photoresist layer; the dielectric layer and the second polysilicon layer are etched under the barrier of the photoresist layer, so as to retain the dielectric layer and the second polysilicon layer on the surface of the part of the lower plate of the PIP capacitor Silicon layer; remove remaining photoresist layer.

Among them, the growth of the silicon dioxide layer can use a thermal oxidation process. The process is to put the silicon wafer into a high-temperature furnace tube at a temperature of 800 to 1100 degrees, and introduce oxygen to allow the oxygen to react with polysilicon at high temperature to form silicon dioxide. A layer of silicon dioxide can also be deposited on the surface of the silicon wafer by a chemical vapor deposition process. Silicon nitride can be produced by chemical vapor deposition process. The growth process of the polysilicon layer may be a chemical vapor deposition process.

207. Perform hole layer fabrication and metal wiring.

In this embodiment, the process of depositing the sidewall oxide layer, etching the sidewall oxide layer, and forming sidewalls on both sides of the lower plate and both sides of the gate of the PIP capacitor is placed in the process of depositing the dielectric layer and the second multilayer. Before the crystalline silicon layer, thus in the process of depositing the dielectric layer and the second polysilicon layer, etching the dielectric layer and the second polysilicon layer to form the dielectric layer of the PIP capacitor and the upper plate of the PIP capacitor , due to the existence of the side wall, avoid the formation of the dielectric layer and the residue of the second polysilicon layer at the side wall of the lower plate of the PIP capacitor, thereby improving the function of preventing noise emission and preventing frequency modulation of the CMOS semiconductor .

Those of ordinary skill in the art can understand that all or part of the steps for implementing the above method embodiments can be completed by program instructions and related hardware. The aforementioned program can be stored in a computer-readable storage medium. When the program is executed, it executes the steps including the above-mentioned method embodiments; and the aforementioned storage medium includes: ROM, RAM, magnetic disk or optical disk and other various media that can store program codes.

Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present invention, rather than limiting them; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that: It is still possible to modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements for some or all of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the technical solutions of the various embodiments of the present invention. scope.

Claims (9)

1. A method for making a CMOS embedded in a PIP capacitor, characterized in that, comprising: Define an active region on the substrate formed with the well region, grow a field oxide layer on the surface of the substrate other than the region corresponding to the active region, and grow a gate oxide layer on the surface of the substrate corresponding to the active region ; Deposit the first polysilicon layer on the entire device surface, etch the first polysilicon layer, retain the first polysilicon layer on the surface of the partial area near the periphery of the field oxide layer, and the first polysilicon layer on the surface of the gate oxide layer The first polysilicon layer on the surface of some areas to form the lower plate and gate of the PIP capacitor respectively; forming lightly doped drains in the substrate surface on both sides of the gate by implanting ions; Depositing a sidewall oxide layer on the entire device surface, etching the sidewall oxide layer, and forming sidewalls on both sides of the first layer of polysilicon and both sides of the gate; Forming source and drain regions by implanting ions; A dielectric layer and a second polysilicon layer are sequentially deposited on the surface of a part of the lower plate of the PIP capacitor to form the dielectric layer and the upper plate of the PIP capacitor respectively; Carry out hole layer fabrication and metal wiring. 2. method according to claim 1, is characterized in that, deposits dielectric layer and the second polysilicon layer successively on the part area surface of the lower pole plate of described PIP electric capacity, comprises: sequentially depositing a dielectric layer and a second polysilicon layer over the entire device surface; Etching the dielectric layer and the second polysilicon layer, retaining the dielectric layer and the second polysilicon layer on the surface of a part of the lower plate of the PIP capacitor. 3. The method according to claim 1, wherein the forming lightly doped drains located in the substrate surface on both sides of the gate by implanting ions comprises: Coating a photoresist layer over the entire surface of the device; performing photolithographic development on the photoresist layer to form ion implantation windows on both sides of the gate; implanting ions into the ion implantation window to form the lightly doped drain located in the substrate surface on both sides of the gate; Remove remaining photoresist layer. 4. method according to claim 2, is characterized in that, described dielectric layer and the second polysilicon layer are etched, and keep the dielectric material on the part area surface of the lower pole plate that is positioned at described PIP electric capacity. layer and the second layer of polysilicon, including: Coating a photoresist layer over the entire device surface; Carrying out photolithographic development to the photoresist layer, retaining the photoresist layer on the surface of a part of the lower plate of the PIP capacitor; The dielectric layer and the second polysilicon layer are etched under the barrier of the photoresist layer, so as to reserve the dielectric layer and the second polysilicon layer on the surface of a part of the lower plate of the PIP capacitor layer; Remove remaining photoresist layer. 5. The method of claim 1, wherein, The thickness of the sidewall oxide layer is 1500-4000 angstroms. 6. The method according to claim 1 or 2, characterized in that, The dielectric layer is a silicon dioxide layer, a silicon nitride layer, or a mixed layer of silicon dioxide and silicon nitride. 7. The method according to claim 1 or 2, characterized in that, The thickness of the dielectric layer is 200-700 angstroms. 8. The method of claim 1, wherein, The thickness of the second polysilicon layer is 2000-5000 Angstroms. 9. The method according to claim 1, wherein the etching the sidewall oxide layer comprises: performing dry etching on the side wall oxide layer.