CN106154612A - Embedded touch panel - Google Patents

Abstract

The invention discloses an embedded touch panel, which comprises a plurality of pixels. A laminated structure of each pixel comprises a substrate, a thin film transistor element layer, a liquid crystal layer, a color filter layer, a glass layer and a second conducting layer. The thin film transistor element layer is arranged on the substrate. A first conductive layer and a common voltage electrode are disposed in the TFT element layer. The first conductive layers are arranged in a grid pattern. The liquid crystal layer is arranged above the thin film transistor element layer. The color filter layer is arranged above the liquid crystal layer. The glass layer is arranged above the color filter layer. The second conductive layer is arranged above the glass layer.

Description

Embedded touch panel

technical field

The present invention relates to touch panels, in particular to an in-cell touch panel.

Background technique

Please refer to FIG. 1 . FIG. 1 is a schematic diagram of a stacked structure of a conventional capacitive touch panel with an On-Cell stacked structure. As shown in FIG. 1 , the stacked structure 1 of a conventional On-Cell capacitive touch panel is sequentially from bottom to top: a substrate 10, a thin film transistor (TFT) element layer 11, a liquid crystal layer 12, a color filter layer 13, A glass layer 14 , a touch sensing layer 15 , a polarizer 16 , an adhesive 17 and an overlying lens 18 .

It can be seen from FIG. 1 that in a conventional capacitive touch panel with an On-Cell laminated structure, the touch sensing layer 15 is disposed above the glass layer 14 , that is, disposed outside the liquid crystal display module. Although the thickness of the traditional capacitive touch panel with On-Cell laminated structure is already thinner than that of the one-piece glass touch panel (One Glass Solution, OGS), it is widely used in mobile phones, tablet computers and notebook computers. Under the trend of thin, light and small electronic products, the traditional capacitive touch panel with On-Cell laminated structure has reached its limit and cannot meet the needs of the thinnest touch panel design.

Contents of the invention

In view of this, the present invention proposes an in-cell touch panel to effectively solve the above-mentioned problems encountered in the prior art.

A specific embodiment according to the present invention is an in-cell touch panel. In this embodiment, the in-cell touch panel includes a plurality of pixels (Pixels). A laminated structure of each pixel includes a substrate, a thin film transistor element layer, a liquid crystal layer, a color filter layer, a glass layer and a second conductive layer. The thin film transistor element layer is arranged on the substrate. A first conductive layer and a common voltage electrode (Common Electrode) are arranged in the thin film transistor element layer. The first conductive layer is arranged in a mesh type. The liquid crystal layer is disposed above the thin film transistor element layer. The color filter layer is disposed above the liquid crystal layer. The glass layer is disposed above the color filter layer. A second conductive layer (ITO) is disposed above the glass layer.

In one embodiment, the in-cell touch panel is an in-cell mutual capacitance (Mutual Capacitance) touch panel. The touch electrode of the embedded mutual capacitance touch panel includes a first direction electrode and a second direction electrode, wherein the first direction electrode is formed by the first conductive layer arranged in grid shape and the second direction electrode is formed by the second direction electrode. The conductive layer is formed.

In one embodiment, the second conductive layer is made of transparent conductive material.

In one embodiment, the first conductive layer is formed behind the common voltage electrode.

In one embodiment, the first conductive layer is formed before the common voltage electrode.

In one embodiment, the color filter layer includes a color filter (Color Filter) and a black matrix photoresist (Black Matrix Resist), the black matrix photoresist has good light shielding property, the first conductive layer is located in the black matrix below the photoresist.

In one embodiment, the thin film transistor element layer also includes an original conductive layer, and the original conductive layer is electrically connected to the common voltage electrode, so as to serve as the wiring of the common voltage electrode and reduce the resistance-capacitance load (RC loading) of the common voltage electrode. ).

In one embodiment, the electrodes in the first direction and the electrodes in the second direction are driving electrodes (TX) and sensing electrodes (RX) respectively, or the electrodes in the first direction and the electrodes in the second direction are sensing electrodes (RX) and driving electrodes respectively (TX).

In one embodiment, the area division of the touch electrodes is determined according to the connection or disconnection of the first conductive layer.

In one embodiment, the portion of the first conductive layer that is not formed with the first direction electrode is electrically connected to the common voltage electrode, so as to serve as a wiring of the common voltage electrode and reduce resistance-capacitance load (RC loading) of the common voltage electrode.

In one embodiment, the portion of the first conductive layer not forming the first direction electrode is disposed in a vacant area between the touch electrodes, so as to be electrically connected to the common voltage electrode.

In one embodiment, one gate and the other gate in the thin film transistor element layer are arranged adjacent to each other on the same side of the pixel.

In one embodiment, the other side of the pixel is provided with the first conductive layer or an original conductive layer in the thin film transistor element layer on the other side of the pixel, and is electrically connected to the common voltage electrode as The wiring of the common voltage electrode and reduce the resistive capacitance load (RCloading) of the common voltage electrode.

In one embodiment, when the stacked structure has a half source driving (Half Source Driving, HSD) structure, the stacked structure will leave an additional space for a source line.

In one embodiment, an original conductive layer in the thin film transistor element layer is electrically connected to the first conductive layer by using the additional space of the source line, and serves as a wiring for the first direction electrode.

In one embodiment, the thin film transistor element layer further includes an original conductive layer, and the original conductive layer is electrically connected to the common voltage electrode by using the additional space of the source line, so as to serve as the wiring of the common voltage electrode and Reduce the resistive capacitive load (RC loading) of the common voltage electrode.

In one embodiment, a dummy electrode (dummy electrode) is disposed between the second direction electrodes formed by the second conductive layer, and the dummy electrode is in a floating state.

In one embodiment, when the in-cell touch panel operates in a touch mode, the common voltage electrode is switched to a floating state or a touch-related signal is applied.

In one embodiment, a touch mode and a display mode of the in-cell touch panel are time-divisionally driven, and the in-cell touch panel uses a blanking interval (Blanking interval) of the display cycle to operate in the touch mode.

In one embodiment, the blanking interval includes at least one of a vertical blanking interval (Vertical Blanking Interval, VBI), a horizontal blanking interval (Horizontal Blanking Interval, HBI) and a long horizontal blanking interval (Long Horizontal Blanking Interval). The time length of the long horizontal blank interval is equal to or greater than the time length of the horizontal blank interval, and the long horizontal blank interval is obtained by reallocating multiple horizontal blank intervals or the long horizontal blank interval includes a vertical blank interval.

In one embodiment, the common voltage electrode has a plurality of common voltage electrode regions respectively overlapping with a plurality of touch sensing electrodes of the in-cell touch panel. When the in-cell touch panel operates in the touch mode, multiple touch sensing electrodes are sequentially applied with multiple touch sensing signals, and the common voltage electrodes are correspondingly applied sequentially with the multiple touch sensing signals. Multiple touch-related signals with the same frequency, same amplitude or same phase, or the common voltage electrode presents a floating state.

In one embodiment, the common voltage electrode has a single common voltage electrode region overlapping with the plurality of touch sensing electrodes of the in-cell touch panel. When the in-cell touch panel operates in the touch mode, multiple touch sensing electrodes apply a touch sensing signal and the common voltage electrode applies a touch signal with the same frequency, amplitude or phase as the touch sensing signal Related signals, or the common voltage electrodes are in a floating state.

Compared with the prior art, the in-cell touch panel according to the present invention has the following advantages and effects:

(1) The design of the touch sensing electrodes and their wiring is simple.

(2) The layout method does not affect the original aperture ratio of the in-cell touch panel.

(3) Reduce the resistance and capacitance load (RC loading) of the common voltage electrode itself.

(4) When the in-cell touch panel operates in the touch mode, the common voltage electrode is simultaneously controlled to reduce the overall resistive and capacitive load of the in-cell touch panel.

(5) Time-sharing driving of the touch mode and the display mode to improve the signal-noise ratio (Signal-NoiseRatio, SNR).

The advantages and spirit of the present invention can be further understood through the following detailed description of the invention and the accompanying drawings.

Description of drawings

FIG. 1 is a schematic diagram of a stacked structure of a conventional capacitive touch panel with an On-Cell stacked structure;

2 is a schematic diagram of a touch electrode layout of an in-cell mutual capacitance touch panel according to a specific embodiment of the present invention;

3A is a schematic cross-sectional view of the first embodiment of the stacked structure of the in-cell mutual capacitance touch panel of the present invention;

3B is a schematic diagram of the pixel design of the in-cell mutual capacitance touch panel shown in FIG. 3A;

4A is a schematic cross-sectional view of a second embodiment of the stacked structure of the in-cell mutual capacitance touch panel of the present invention;

4B is a schematic diagram of the pixel design of the in-cell mutual capacitance touch panel shown in FIG. 4A;

5A is a schematic cross-sectional view of a third embodiment of the stacked structure of the in-cell mutual capacitance touch panel of the present invention;

5B is a schematic diagram of the pixel design of the in-cell mutual capacitance touch panel shown in FIG. 5A;

6A is a schematic cross-sectional view of a fourth embodiment of the stacked structure of the in-cell mutual capacitance touch panel of the present invention;

6B is a schematic diagram of the pixel design of the in-cell mutual capacitance touch panel shown in FIG. 6A;

7 is a schematic diagram of pixel design when the stacked structure of the in-cell mutual capacitance touch panel has a half-source driving structure;

8A and 8B are schematic diagrams of different distribution patterns of the touch electrodes of the in-cell mutual capacitance touch panel;

FIG. 9 is a schematic diagram of dummy electrodes disposed between the electrodes in the second direction formed by the second conductive layer;

FIG. 10A is a schematic diagram of an in-cell mutual-capacitance touch panel using a blank space in an image signal to output a touch driving signal to operate in a touch mode;

Fig. 10B is a schematic diagram of a vertical blank interval, a horizontal blank interval and a long horizontal blank interval respectively;

11A is a schematic diagram of a common voltage electrode in an in-cell mutual capacitance touch panel having a plurality of common voltage electrode regions overlapping with a plurality of touch sensing electrodes;

FIG. 11B shows that when the in-cell mutual capacitance touch panel operates in the touch mode, multiple touch sensing electrodes sequentially apply multiple touch sensing signals, and the multiple common voltage electrode areas of the common voltage electrode correspond to each other. A timing diagram of sequentially applying multiple touch-related signals with the same frequency, same amplitude, or same phase as the multiple touch sensing signals;

FIG. 11C shows that when the in-cell mutual capacitance touch panel operates in the touch mode, multiple touch sensing electrodes apply multiple touch sensing signals sequentially, and the multiple common voltage electrode areas of the common voltage electrode all appear floating. The timing diagram of the connected state;

FIG. 12A is a schematic diagram showing that the common voltage electrode in the in-cell mutual capacitance touch panel has a single common voltage electrode region overlapping with multiple touch sensing electrodes of the in-cell mutual capacitance touch panel;

FIG. 12B shows that when the in-cell mutual capacitance touch panel operates in the touch mode, multiple touch sensing electrodes apply multiple touch sensing signals sequentially, and the common voltage electrode is applied at the same time as the multiple touch sensing signals. Timing diagram of touch-related signals with frequency, same amplitude or same phase;

FIG. 12C is a timing diagram of when the in-cell mutual capacitance touch panel operates in the touch mode, multiple touch sensing electrodes are sequentially applied with multiple touch sensing signals and the common voltage electrode is in a floating state.

Description of main component symbols:

20 common voltage electrodes

21, 81 First direction electrode

22, 82 Second direction electrode

VIA through hole

3, 4, 5, 6 laminated structure

30, 40, 50, 60 substrates

31, 41, 51, 61 thin film transistor element layer

32, 42, 52, 62 liquid crystal layer

33, 43, 53, 63 color filter layer

34, 44, 54, 64 glass layers

35, 45, 55, 65 Second conductive layer

310, 410, 510, 610, 710 first conductive layer

312, 412, 512, 612, 712 common voltage electrodes

314, 414, 514, 614, 714 Conductive layer

330, 430, 530, 630 Black Matrix Resist

332, 432, 532, 632 color filters

LC liquid crystal cell

G Gate

S source

D drain

3A～3C, 4A～4C, 5A～5C, 6A～6C, 7A～7C The range marked by dotted line

83 Dummy electrodes

SIM image signal

HSync horizontal synchronization signal

VSync vertical synchronization signal

STH touch drive signal

VBI Vertical Blank Interval

HBI Horizontal Blank Interval

LHBI long horizontal blank interval

VCOM common voltage electrode

VCOM1～VCOM3 common voltage electrode area

TX1～TX3 touch sensing electrodes

TR trace

G1～G3 gate drive signal

S1～S3 source drive signal

STX1～STX3 touch sensing signal

SVCOM1～SVCOM3, SVCOM touch related signals

detailed description

A specific embodiment according to the present invention is an in-cell touch panel. In this embodiment, the in-cell touch panel is an in-cell mutual-capacitive touch panel, but not limited thereto.

The in-cell touch panel in this embodiment includes a plurality of pixels. A laminated structure of each pixel includes a substrate, a thin film transistor element layer, a liquid crystal layer, a color filter layer, a glass layer and a second conductive layer. The thin film transistor element layer is arranged on the substrate. A first conductive layer and a common voltage electrode are arranged in the thin film transistor element layer. The first conductive layer is arranged in grid form. The liquid crystal layer is disposed above the thin film transistor element layer. The color filter layer is disposed above the liquid crystal layer. The glass layer is disposed above the color filter layer. A second conductive layer made of transparent conductive material is disposed above the glass layer.

Please refer to FIG. 2 . FIG. 2 is an embodiment of the touch electrode layout of the in-cell mutual capacitance touch panel of the present invention. As shown in FIG. 2 , the touch electrodes of the in-cell mutual capacitance touch panel include a first direction electrode 21 and a second direction electrode 22, wherein the first direction electrode 21 is formed by a first conductive layer arranged in a grid shape and The second direction electrode 22 is formed by the second conductive layer. Wherein, the first direction electrode 21 and the second direction electrode 22 can be respectively used as the driving electrode (TX) and the sensing electrode (RX) of mutual capacitive touch sensing, or the first direction electrode 21 and the second direction electrode 22 can be respectively As the sensing electrodes (RX) and driving electrodes (TX) for mutual capacitance touch sensing, there is no specific limitation.

It should be noted that since the first conductive layer and the common voltage electrode 20 are disposed in the thin film transistor element layer and the second conductive layer is disposed above the thin film transistor element layer, the second conductive layer will be located above the first conductive layer, That is, the second direction electrode 22 formed by the second conductive layer is located above the first direction electrode 21 formed by the first conductive layer.

In addition, the common voltage electrode trace TR is electrically connected to the common voltage electrode 20 through the via hole VIA, so as to reduce the resistance-capacitance load (RC loading) of the common voltage electrode 20 . Actually, the common voltage electrode trace TR can be formed by the first conductive layer of the part where the first direction electrode 21 is not formed in the thin film transistor element layer or other original conductive layers, but not limited thereto.

Next, please refer to FIG. 3A . FIG. 3A is a schematic cross-sectional view of a first embodiment of the stacked structure of the in-cell mutual capacitance touch panel of the present invention. As shown in FIG. 3A , the laminate structure 3 of the in-cell mutual capacitance touch panel includes a substrate 30 , a thin film transistor element layer 31 , a liquid crystal layer 32 , a color filter layer 33 , a glass layer 34 and a second conductive layer 35 . The thin film transistor element layer 31 is disposed on the substrate 30 . A first conductive layer 310 and a common voltage electrode 312 are disposed in the thin film transistor element layer 31 , and the first conductive layer 310 is formed behind the common voltage electrode 312 . The first conductive layer 310 is arranged in a grid. A liquid crystal layer 32 including a plurality of liquid crystal cells LC is disposed above the thin film transistor element layer 31 . The color filter layer 33 is disposed above the liquid crystal layer 32 . The glass layer 34 is disposed above the color filter layer 33 . The second conductive layer 35 is disposed on the glass layer 34 .

It should be noted that the color filter layer 33 includes a black matrix resist (Black Matrix Resist) 330 and a color filter (Color Filter) 332 . The grid-shaped first conductive layer 310 is disposed under the black matrix photoresist 330 to shield the lower first conductive layer 310 through the black matrix photoresist 330 with good light shielding property.

Please also refer to FIG. 3B , which is a schematic diagram of the pixel design of the in-cell mutual capacitance touch panel of the present invention. As shown in FIG. 3B , the area division of the touch electrodes of the in-cell mutual capacitance touch panel is determined according to the connection or disconnection of the first conductive layer 310 .

For example, in the range 3A marked by a dotted line, since the first conductive layers 310 are connected to each other, the upper and lower pixels belong to the same touch electrode range; in the range 3C marked by a dotted line, since the first conductive layers 310 are disconnected from each other, Therefore, the upper and lower pixels belong to different touch electrode ranges. In addition, in the range 3B marked by the dotted line, the first conductive layer 310 of the portion not forming the first direction electrode can be disposed in a vacant area between the touch electrodes, and can be electrically connected to the common voltage electrode 312 through the via hole VIA. , but not limited to this.

Next, please refer to FIG. 4A . FIG. 4A is a schematic cross-sectional view of a second embodiment of the stacked structure of the in-cell mutual capacitance touch panel of the present invention. As shown in FIG. 4A , the laminated structure 4 of the in-cell mutual capacitance touch panel includes a substrate 40 , a thin film transistor element layer 41 , a liquid crystal layer 42 , a color filter layer 43 , a glass layer 44 and a second conductive layer 45 . The thin film transistor element layer 41 is disposed on the substrate 40 . A first conductive layer 410 and a common voltage electrode 412 are disposed in the thin film transistor element layer 41 , and the first conductive layer 410 is formed before the common voltage electrode 412 . The first conductive layer 410 is arranged in a grid. A liquid crystal layer 42 including a plurality of liquid crystal cells LC is disposed above the thin film transistor element layer 41 . The color filter layer 43 is disposed above the liquid crystal layer 42 . The glass layer 44 is disposed above the color filter layer 43 . The second conductive layer 45 is disposed on the glass layer 44 .

It should be noted that the color filter layer 43 includes a black matrix photoresist 430 and a color filter 432 . The grid-shaped first conductive layer 410 is disposed under the black matrix photoresist 430 so as to shield the lower first conductive layer 410 through the black matrix photoresist 430 with good light shielding property.

Please also refer to FIG. 4B , which is a schematic diagram of the pixel design of the in-cell mutual capacitance touch panel of the present invention. As shown in FIG. 4B , the area division of the touch electrodes of the in-cell mutual capacitance touch panel is determined according to the connection or disconnection of the first conductive layer 410 .

For example, in the range 4A marked by dotted lines, because the first conductive layers 410 are connected to each other, the upper and lower pixels belong to the same touch electrode range; in the range 4C marked by dotted lines, since the first conductive layers 410 are disconnected from each other, Therefore, the upper and lower pixels belong to different touch electrode ranges. In addition, in the range 4B marked by the dotted line, the first conductive layer 410 of the portion not forming the electrodes in the first direction can be disposed in a vacant area between the touch electrodes, and can be electrically connected to the common voltage electrode 412 through the via hole VIA. , but not limited to this.

Next, please refer to FIG. 5A . FIG. 5A is a schematic cross-sectional view of a third embodiment of the stacked structure of the in-cell mutual capacitance touch panel of the present invention. As shown in FIG. 5A , the laminate structure 5 of the in-cell mutual capacitance touch panel includes a substrate 50 , a thin film transistor element layer 51 , a liquid crystal layer 52 , a color filter layer 53 , a glass layer 54 and a second conductive layer 55 . The thin film transistor element layer 51 is disposed on the substrate 50 . A first conductive layer 510 and a common voltage electrode 512 are disposed in the thin film transistor element layer 51 , and the first conductive layer 510 is formed behind the common voltage electrode 512 . The first conductive layer 510 is arranged in a grid. A liquid crystal layer 52 including a plurality of liquid crystal cells LC is disposed above the thin film transistor element layer 51 . The color filter layer 53 is disposed above the liquid crystal layer 52 . The glass layer 54 is disposed above the color filter layer 53 . The second conductive layer 55 is disposed on the glass layer 54 .

It should be noted that the color filter layer 53 includes a black matrix photoresist 530 and a color filter 532 . The grid-shaped first conductive layer 510 is disposed under the black matrix photoresist 530 to shield the lower first conductive layer 510 through the black matrix photoresist 530 with good light shielding property.

Please also refer to FIG. 5B , which is a schematic diagram of pixel design of the in-cell mutual capacitance touch panel of the present invention. As shown in FIG. 5B , the area division of the touch electrodes of the in-cell mutual capacitance touch panel is determined according to the connection or disconnection of the first conductive layer 510 .

For example, in the range 5A marked by a dotted line, since the first conductive layers 510 are disconnected from each other, the upper and lower pixels belong to different touch electrode ranges; in the range 5C marked by a dotted line, since the first conductive layers 510 are connected to each other, Therefore, the upper and lower pixels belong to the same touch electrode range. In addition, within the range 5B marked by the dotted line, the conductive layer (such as the gate conductive layer G) not forming the touch electrode can be electrically connected to the common voltage electrode 512 through the via hole VIA, but not limited thereto.

It should be noted that, as shown in FIG. 5B , the two gates G in the thin film transistor element layer can be arranged adjacent to each other on the same side of the pixel, thereby reducing the width of the upper black matrix photoresist. In addition, the other side of the pixel can be provided with the first conductive layer 510 or other original conductive layers in the thin film transistor element layer and electrically connected with the common voltage electrode 512 as a common voltage. The routing of the electrodes 512 reduces the resistance and capacitance load of the common voltage electrodes 512 .

Next, please refer to FIG. 6A . FIG. 6A is a schematic cross-sectional view of a fourth embodiment of the stacked structure of the in-cell mutual capacitance touch panel of the present invention. As shown in FIG. 6A , the laminate structure 6 of the in-cell mutual capacitance touch panel includes a substrate 60 , a thin film transistor element layer 61 , a liquid crystal layer 62 , a color filter layer 63 , a glass layer 64 and a second conductive layer 65 . The thin film transistor element layer 61 is disposed on the substrate 60 . A first conductive layer 610 and a common voltage electrode 612 are disposed in the thin film transistor element layer 61 , and the first conductive layer 610 is formed before the common voltage electrode 612 . The first conductive layer 610 is arranged in a grid. A liquid crystal layer 62 including a plurality of liquid crystal cells LC is disposed above the thin film transistor element layer 61 . The color filter layer 63 is disposed above the liquid crystal layer 62 . The glass layer 64 is disposed above the color filter layer 63 . The second conductive layer 65 is disposed on the glass layer 64 .

It should be noted that the color filter layer 63 includes a black matrix photoresist 630 and a color filter 632 . The grid-shaped first conductive layer 610 is disposed under the black matrix photoresist 630 so as to shield the lower first conductive layer 610 through the black matrix photoresist 630 with good light shielding property.

Please also refer to FIG. 6B , which is a schematic diagram of the pixel design of the in-cell mutual capacitance touch panel of the present invention. As shown in FIG. 6B , the area division of the touch electrodes of the in-cell mutual capacitance touch panel can be determined according to the connection or disconnection of the first conductive layer 610 .

For example, in the range 6A marked by dotted lines, since the first conductive layers 610 are disconnected from each other, the upper and lower pixels belong to different touch electrode ranges; in the range 6C marked by dotted lines, since the first conductive layers 610 are connected to each other, Therefore, the upper and lower pixels belong to the same touch electrode range. In addition, in the range 6B marked by the dotted line, the conductive layer (such as the gate conductive layer G) not forming the touch electrode can be electrically connected to the common voltage electrode 612 through the via hole VIA, but not limited thereto.

It should be noted that, as shown in FIG. 6B , the two gates G in the thin film transistor element layer can be arranged adjacent to each other on the same side of the pixel, thereby reducing the width of the upper black matrix photoresist. In addition, the other side of the pixel can be provided with the first conductive layer 610 or other original conductive layers in the thin film transistor element layer and electrically connected with the common voltage electrode 612 as a common voltage. The routing of the electrodes 612 reduces the resistance and capacitance load of the common voltage electrodes 612 .

Next, please refer to FIG. 7 , when the stacked structure of the in-cell mutual capacitance touch panel has a half source driving (Half Source Driving, HSD) structure, the stacked structure will leave an additional space for a source line. In the ranges 7A and 7B indicated by the dotted lines, the original conductive layer in the thin film transistor element layer is electrically connected to the first conductive layer 710 by using the space of the extra source line to be formed as the first conductive layer 710. The traces of the touch electrodes (first direction electrodes). In addition, within the range 7C marked by the dotted line, the original conductive layer in the thin film transistor element layer can also be electrically connected to the common voltage electrode 712 by using the extra space of the source line, so as to serve as the common voltage electrode 712. line and reduce the resistive capacitive load on the common voltage electrode 712.

In practical applications, as shown in FIG. 8A and FIG. 8B , the touch electrodes of the in-cell mutual capacitance touch panel include first direction electrodes 81 and second direction electrodes 82 , wherein the first direction electrodes 81 are arranged in a grid The first conductive layer is formed and the second direction electrode 82 is formed by the second conductive layer, and the second direction electrode 82 is located above the first direction electrode 81 .

It should be noted that there is no specific limitation on the distribution pattern of the touch electrodes of the embedded mutual capacitance touch panel, that is, the arrangement and layout of the electrodes 81 in the first direction and the electrodes 82 in the second direction, as shown in FIG. 8A , Figure 8B or other arrangements and layouts. In addition, as shown in FIG. 9, a dummy electrode (Dummy electrode) 83 may be provided between the second direction electrodes 82 formed by the second conductive layer, and the dummy electrode 83 is in a floating state, but does not This is the limit.

The embedded mutual capacitance touch panel of the present invention can operate in the display mode and the touch mode respectively at different times, that is, the touch mode and the display mode of the embedded mutual capacitance touch panel of the present invention are time-division driven.

When the embedded mutual-capacitance touch panel operates in the display mode, its gate driver and source driver will output gate driving signals G1~G3 and source driving signals S1~S3 respectively to drive the embedded mutual-capacitance touch panel. The pixel display screen of the control panel; when the in-cell touch panel operates in the touch mode, the common voltage electrode in the in-cell touch panel can be switched to a floating state or apply a touch-related signal, but This is not the limit.

Referring to FIG. 10A , the in-cell mutual capacitance touch panel utilizes the blanking interval (Blanking interval) in the image signal SIM to output the touch driving signal STH to operate in the touch mode. The in-cell mutual capacitance touch panel 10A performs touch sensing during the non-display sequence (ie blank interval). Please also refer to FIG. 10B . FIG. 10B is a schematic diagram of a vertical blank space, a horizontal blank space, and a long horizontal blank space, respectively. In practical applications, the in-cell mutual-capacitance touch panel can adjust the number of blank spaces it uses according to different driving methods. As shown in FIG. 10B , the blanking interval may include at least one of a vertical blanking interval (Vertical Blanking Interval) VBI, a horizontal blanking interval (Horizontal Blanking Interval) (HBI) and a long horizontal blanking interval (LHBI). Wherein, the time length of the long horizontal blank interval LHBI is equal to or greater than the time length of the horizontal blank interval HBI. The long horizontal blank interval LHBI can be obtained by reallocating multiple horizontal blank intervals HBI or the long horizontal blank interval LHBI includes a vertical blank interval VBI.

In practical applications, the common voltage electrode in the in-cell mutual capacitance touch panel of the present invention may have a single or multiple common voltage electrode areas, and there is no specific limitation.

In one embodiment, as shown in FIG. 11A , the common voltage electrode VCOM in the in-cell mutual capacitance touch panel may have a plurality of common voltage electrode regions VCOM1-VCOM3, and the common voltage electrode regions VCOM1-VCOM3 are respectively connected to the plurality of common voltage electrode regions VCOM1-VCOM3. The touch sensing electrodes TX1 - TX3 overlap. As shown in Figure 11B and Figure 11C, when the in-cell mutual capacitance touch panel operates in the display mode, its gate driver and source driver will output gate driving signals G1~G3 and source driving signals S1~S3 respectively , to drive the pixel display screen of the embedded mutual capacitance touch panel; when the embedded mutual capacitance touch panel operates in the touch mode, the plurality of touch sensing electrodes TX1-TX3 sequentially apply a plurality of touch senses The multiple common voltage electrode regions VCOM1～VCOM3 of the common voltage electrode VCOM are correspondingly applied with multiple touch sensing signals STX1～STX3 with the same frequency, same amplitude or same phase. The signals SVCOM1 - SVCOM3 (as shown in FIG. 11B ), or the multiple common voltage electrode regions VCOM1 - VCOM3 of the common voltage electrode VCOM are in a floating state (as shown in FIG. 11C ).

In another embodiment, as shown in FIG. 12A , the common voltage electrode VCOM in the in-cell mutual capacitive touch panel has a single common voltage electrode area and is compatible with multiple touch senses of the in-cell mutual capacitive touch panel. The measuring electrodes TX1-TX3 all overlap. As shown in Figure 12B and Figure 12C, when the in-cell mutual capacitance touch panel operates in the display mode, its gate driver and source driver will output gate driving signals G1~G3 and source driving signals S1~S3 respectively , to drive the pixel display screen of the embedded mutual capacitance touch panel; when the embedded touch panel operates in the touch mode, multiple touch sensing electrodes TX1-TX3 sequentially apply multiple touch sensing signals STX1-STX3 and the common voltage electrode VCOM apply a touch-related signal SVCOM with the same frequency, amplitude or phase as the multiple touch sensing signals STX1-STX3 (as shown in FIG. 12B ), or the common voltage electrode VCOM is floating. connected state (as shown in Figure 12C).

Compared with the prior art, the in-cell touch panel according to the present invention has the following advantages and effects:

(1) The design of the touch sensing electrodes and their wiring is simple.

(2) The layout method does not affect the original aperture ratio of the in-cell touch panel.

(3) Reduce the resistance and capacitance load of the common voltage electrode itself.

(4) When the in-cell touch panel operates in the touch mode, the common voltage electrode is simultaneously controlled to reduce the overall resistive and capacitive load of the in-cell touch panel.

(5) Time-sharing driving of the touch mode and the display mode to improve the signal-to-noise ratio.

From the above detailed description of the preferred embodiments, it is hoped that the characteristics and spirit of the present invention can be described more clearly, rather than the scope of the present invention is limited by the preferred embodiments disclosed above. On the contrary, the intention is to cover various changes and equivalent arrangements within the scope of the claimed patent scope of the present invention.

Claims (22)

1. An embedded touch panel, characterized in that it comprises: Multiple pixels, a stack of each pixel containing: a substrate; A thin film transistor element layer disposed on the substrate, the thin film transistor element layer is provided with a first conductive layer M3 and a common voltage electrode, wherein the first conductive layer is arranged in a grid; a liquid crystal layer disposed above the thin film transistor element layer; a color filter layer arranged above the liquid crystal layer; a glass layer disposed above the color filter layer; and A second conductive layer ITO is disposed on the glass layer. 2. The in-cell touch panel according to claim 1, characterized in that it is an in-cell mutual capacitance touch panel, and the touch electrodes of the in-cell mutual capacitance touch panel include a first direction electrode and a second direction electrode, wherein the first direction electrode is formed by the first conductive layer arranged in grid shape and the second direction electrode is formed by the second conductive layer. 3. The in-cell touch panel as claimed in claim 1, wherein the second conductive layer is made of a transparent conductive material. 4. The in-cell touch panel as claimed in claim 1, wherein the first conductive layer is formed behind the common voltage electrode. 5. The in-cell touch panel as claimed in claim 1, wherein the first conductive layer is formed before the common voltage electrode. 6. The in-cell touch panel according to claim 1, wherein the color filter layer comprises a color filter and a black matrix photoresist, and the black matrix photoresist has good light shielding properties, The first conductive layer is located under the black matrix photoresist. 7. The in-cell touch panel according to claim 1, wherein the thin film transistor element layer further comprises an original conductive layer, and the original conductive layer is electrically connected to the common voltage electrode as the The wiring of the common voltage electrode and reduce the resistive and capacitive load of the common voltage electrode. 8. The in-cell touch panel according to claim 2, wherein the electrodes in the first direction and the electrodes in the second direction are driving electrodes TX and sensing electrodes RX or the electrodes in the first direction and the second electrodes respectively. The two direction electrodes are the sensing electrode RX and the driving electrode TX respectively. 9 . The in-cell touch panel according to claim 2 , wherein the area division of the touch electrodes is determined according to the connection or disconnection of the first conductive layer. 10. The in-cell touch panel as claimed in claim 2, wherein the first conductive layer where the first direction electrode is not formed is electrically connected to the common voltage electrode to serve as the common voltage electrode. Route and reduce the resistive capacitive load on this common voltage electrode. 11. The in-cell touch panel according to claim 10, wherein the first conductive layer not forming the portion of the first direction electrode is disposed in a vacant area between the touch electrodes, so as to be in contact with the touch electrodes. The common voltage electrodes are electrically connected. 12 . The in-cell touch panel according to claim 1 , wherein one gate and the other gate in the thin film transistor element layer are arranged adjacent to each other on the same side of the pixel. 13 . 13. The in-cell touch panel according to claim 12, characterized in that, the other side of the pixel is provided with a part of the first conductive layer or the thin film transistor element layer where the first direction electrode is not formed. An original conductive layer of the common voltage electrode is electrically connected with the common voltage electrode, so as to serve as the wiring of the common voltage electrode and reduce the resistive capacitance load of the common voltage electrode. 14. The in-cell touch panel as claimed in claim 2, wherein when the stacked structure has a half-source driving structure, the stacked structure will leave an additional space for a source line. 15. The in-cell touch panel as claimed in claim 14, wherein an original conductive layer in the thin film transistor element layer utilizes the extra space of the source line and the first conductive layer Electrically connected to serve as the wiring of the electrodes in the first direction. 16. The in-cell touch panel according to claim 14, wherein the thin film transistor element layer further comprises an original conductive layer, and the original conductive layer utilizes the extra space of the source line It is electrically connected with the common voltage electrode, so as to serve as the wiring of the common voltage electrode and reduce the resistive and capacitive load of the common voltage electrode. 17. The in-cell touch panel according to claim 2, wherein a dummy electrode is disposed between the second direction electrodes formed by the second conductive layer, and the dummy electrode is in a floating state. 18. The in-cell touch panel according to claim 1, wherein when the in-cell touch panel operates in a touch mode, the common voltage electrode is switched to a floating state or a touch is applied. control related signals. 19. The in-cell touch panel according to claim 1, wherein a touch mode and a display mode of the in-cell touch panel are time-division driven, and the in-cell touch panel utilizes a display A blank section of the cycle operates in the touch mode. 20. The in-cell touch panel according to claim 19, wherein the blank space comprises at least one of a vertical blank space, a horizontal blank space and a long horizontal blank space, and the long horizontal blank space The time length of is equal to or greater than the time length of the horizontal blank interval, and the long horizontal blank interval is obtained by reallocating multiple horizontal blank intervals or the long horizontal blank interval includes the vertical blank interval. 21. The in-cell touch panel according to claim 19, wherein the common voltage electrode has a plurality of common voltage electrode areas respectively overlapping with a plurality of touch sensing electrodes of the in-cell touch panel, When the in-cell touch panel operates in the touch mode, the plurality of touch sensing electrodes sequentially apply a plurality of touch sensing signals and the common voltage electrode is correspondingly applied sequentially to the plurality of touch sensing electrodes. Multiple touch-related signals with the same frequency, same amplitude or same phase as the control sensing signal, or the common voltage electrode is in a floating state. 22. The in-cell touch panel as claimed in claim 19, wherein the common voltage electrode has a single common voltage electrode area overlapping with a plurality of touch sensing electrodes of the in-cell touch panel , when the in-cell touch panel operates in the touch mode, the plurality of touch sensing electrodes apply a touch sensing signal and the common voltage electrode applies the same frequency and amplitude as the touch sensing signal Or a touch-related signal in the same phase, or the common voltage electrode is in a floating state.