CN106057157A - Goa circuit and liquid crystal display panel - Google Patents
Goa circuit and liquid crystal display panel Download PDFInfo
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- CN106057157A CN106057157A CN201610623424.2A CN201610623424A CN106057157A CN 106057157 A CN106057157 A CN 106057157A CN 201610623424 A CN201610623424 A CN 201610623424A CN 106057157 A CN106057157 A CN 106057157A
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- film transistor
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- 239000004973 liquid crystal related substance Substances 0.000 title abstract description 7
- 239000010409 thin film Substances 0.000 claims abstract description 242
- 238000012423 maintenance Methods 0.000 claims abstract description 16
- 239000003990 capacitor Substances 0.000 claims abstract description 15
- 239000010408 film Substances 0.000 claims description 27
- 230000005540 biological transmission Effects 0.000 claims description 10
- 239000013078 crystal Substances 0.000 claims description 7
- 238000000465 moulding Methods 0.000 claims description 2
- 238000010408 sweeping Methods 0.000 claims description 2
- 230000002159 abnormal effect Effects 0.000 abstract 1
- 101000940468 Drosophila melanogaster COP9 signalosome complex subunit 2 Proteins 0.000 description 11
- 230000005856 abnormality Effects 0.000 description 5
- 230000000694 effects Effects 0.000 description 3
- 230000005611 electricity Effects 0.000 description 3
- 241000208340 Araliaceae Species 0.000 description 2
- 235000005035 Panax pseudoginseng ssp. pseudoginseng Nutrition 0.000 description 2
- 235000003140 Panax quinquefolius Nutrition 0.000 description 2
- 235000008434 ginseng Nutrition 0.000 description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 238000005034 decoration Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 230000000750 progressive effect Effects 0.000 description 1
- 230000001629 suppression Effects 0.000 description 1
Classifications
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3674—Details of drivers for scan electrodes
- G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3696—Generation of voltages supplied to electrode drivers
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- Engineering & Computer Science (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
- Liquid Crystal Display Device Control (AREA)
Abstract
The invention provides a GOA circuit and a liquid crystal display panel. The GOA circuit comprises an up pull control module, an up pull module, a down pull module, a download module, a down pull maintenance module, a bootstrap capacitor, a first constant voltage low level source, and a second constant voltage low level source. The up pull control module is electrically connected to the up pull module, the down pull module, the download module, the down pull maintenance module, and the bootstrap capacitor. The down pull module is electrically connected to the up pull module. The down pull module is electrically connected to the second constant voltage low level source. The down pull maintenance module is electrically connected to the first constant voltage low level source and the second constant voltage low level source. The down pull module comprises a voltage compensation sub module. According to the GOA circuit and the liquid crystal display panel, through arranging the voltage compensation sub module in a down pull control module, the technical problems of abnormal output of scanning signal and influence on display caused by insufficient scanning signal charging due to the movement of thin film transistor threshold voltage to a negative value of an existing GOA circuit and liquid crystal display panel are solved.
Description
Technical field
The present invention relates to technical field of liquid crystal display, particularly relate to a kind of GOA circuit and there is the liquid crystal of described GOA circuit
Display floater.
Background technology
IGZO, as the most popular TFT active layer, obtains extensive concern, for IGZO-TFT device, due to system
In journey, oxygen vacancy difficulty controls, so IGZO-TFT often shows as depletion type TFT, is also to say when the voltage of Vgs is negative
Waiting, TFT device has already turned on；This shortcoming of IGZO-TFT, the performance to GOA circuit produces serious influence.
Gate Driver On Array, is called for short GOA, i.e. at the array base palte of existing liquid crystal display panel of thin film transistor
Upper making scan drive circuit, it is achieved the type of drive to scan line progressive scan.The structural representation of existing GOA circuit is such as
Shown in Fig. 1, this GOA circuit includes pulling up control module 101, pull-up module 102, lower transmission module 103, drop-down module 104, bootstrapping
Electric capacity and drop-down maintenance module 105.
Described drop-down module 104 includes a thin film transistor (TFT), and the source electrode of this thin film transistor (TFT) connects constant voltage low level source
DCL, the grid of this thin film transistor (TFT) connects scanning signal G (N+1) of next stage, and the drain electrode of this thin film transistor (TFT) connects pull-up control
The outfan of molding block.
When this thin film transistor (TFT) works long hours, its threshold voltage can move toward negative value, causes scanning signal undercharge,
Cause scanning signal output abnormality, and then affect the display effect of display panels.
Therefore, it is necessary to provide a kind of GOA circuit, to solve the problem existing for prior art.
Summary of the invention
The present invention provides a kind of GOA circuit, it is possible to the GOA circuit that suppression thin film transistor (TFT) threshold voltage moves toward negative value,
Move so that scanning signal output abnormality, Jin Erying toward negative value with the existing GOA circuit because thin film transistor (TFT) threshold voltage of solution
Ring the technical problem of display.
For solving the problems referred to above, the technical scheme that the present invention provides is as follows:
The present invention provides a kind of GOA circuit, including:
Pull-up control module, generates the scanning level signal of this grade for receiving the scanning signal of upper level；
Pull-up module, for drawing high described level according to the scanning level signal of described level and the clock signal of this grade
Scanning signal；
Drop-down module, drags down the scanning level signal of described level for the scanning signal according to next stage；
Lower transmission module, for generating the level of this grade according to the scanning level signal of described level and the clock signal of this grade
The number of delivering a letter；
Drop-down maintenance module, for maintaining the low level of the scanning level signal of described level；
Bootstrap capacitor, for generating the high level of the scanning signal of described level；And
First constant voltage low level source, for providing the first constant voltage low level；
Second constant voltage low level source, for providing the second constant voltage low level；
Wherein said pull-up control module respectively with described pull-up module, described drop-down module, described lower transmission module, described
Drop-down maintenance module and described bootstrap capacitor are electrically connected with；Described drop-down module is electrically connected with described pull-up module；Described
Drop-down module is electrically connected with described second constant voltage low level source；Described drop-down maintenance module respectively with the described first low electricity of constant voltage
Flat source, described second constant voltage low level source are electrically connected with.
In the GOA circuit of the present invention, described drop-down module includes the 41st thin film transistor (TFT) and connects the described 4th
The voltage compensation submodule of 11 thin film transistor (TFT)s, described voltage compensation submodule includes the first film transistor, the 40th thin
Film transistor and the first constant voltage high level source；
The grid of described the first film transistor connects the outfan of the level number of delivering a letter of this grade, described the first film transistor
Source electrode connect described first constant voltage high level source, the drain electrode of described the first film transistor connects described 40th film crystal
The drain electrode of pipe；
The grid of described 40th thin film transistor (TFT) and source electrode are all connected with the outfan of described pull-up control module；
The grid of described 41st thin film transistor (TFT) connects the scanning signal of next stage, described 41st film crystal
The source electrode of pipe connects described second constant voltage low level source, and the drain electrode of described 41st thin film transistor (TFT) connects described 40th thin
The drain electrode of film transistor.
In the GOA circuit of the present invention, described pull-up control module includes that the 11st thin film transistor (TFT) and the second constant voltage are high
Level source；
The grid of described 11st thin film transistor (TFT) connects described second constant voltage high level source, described 11st film crystal
The source electrode of pipe connects the scanning signal of described upper level, and the drain electrode of described 11st thin film transistor (TFT) connects described pull-up and controls mould
The outfan of block.
In the GOA circuit of the present invention, described pull-up module includes the 21st thin film transistor (TFT), the described 20th
The grid of one thin film transistor (TFT) connects the outfan of described pull-up control module, and the source electrode of described 21st thin film transistor (TFT) is even
Connecing the clock signal of described level, the drain electrode of described 21st thin film transistor (TFT) connects the scanning signal of described level.
In the GOA circuit of the present invention, described lower transmission module includes the 22nd thin film transistor (TFT), the described 20th
The grid of two thin film transistor (TFT)s connects the outfan of described pull-up control module, and the source electrode of described 22nd thin film transistor (TFT) is even
Connecing the clock signal of described level, the drain electrode of described 22nd thin film transistor (TFT) connects the level number of delivering a letter of described level.
In the GOA circuit of the present invention, described drop-down maintenance module includes the 32nd thin film transistor (TFT), the 42nd thin
Film transistor, the 51st thin film transistor (TFT), the 52nd thin film transistor (TFT), the 53rd thin film transistor (TFT), the 54th thin
Film transistor, the 73rd thin film transistor (TFT), the 74th thin film transistor (TFT), the 81st thin film transistor (TFT), the 82nd thin
Film transistor and the 3rd constant voltage high level source；
The drain electrode of grid described 53rd thin film transistor (TFT) of connection of described 32nd thin film transistor (TFT), the described 3rd
The source electrode of 12 thin film transistor (TFT)s connects described first constant voltage low level source, and the drain electrode of described 32nd thin film transistor (TFT) connects
The scanning signal of described level；
The drain electrode of grid described 53rd thin film transistor (TFT) of connection of described 42nd thin film transistor (TFT), the described 4th
The drain electrode of 12 thin film transistor (TFT)s connects the outfan of described pull-up control module, the source electrode of described 42nd thin film transistor (TFT)
Connect the drain electrode of described 81st thin film transistor (TFT)；
The grid of described 51st thin film transistor (TFT) is connected described 3rd constant voltage high level source with source electrode, and the described 50th
The drain electrode of one thin film transistor (TFT) connects the source electrode of described 52nd thin film transistor (TFT)；
The drain electrode of grid described 11st thin film transistor (TFT) of connection of described 52nd thin film transistor (TFT), the described 50th
The source electrode of two thin film transistor (TFT)s connects described first constant voltage low level source；
The drain electrode of grid described 51st thin film transistor (TFT) of connection of described 53rd thin film transistor (TFT), the described 5th
The source electrode of 13 thin film transistor (TFT)s connects described 3rd constant voltage high level source, and the drain electrode of described 53rd thin film transistor (TFT) connects
The drain electrode of described 54th thin film transistor (TFT)；
The drain electrode of grid described 11st thin film transistor (TFT) of connection of described 54th thin film transistor (TFT), the described 50th
The source electrode of four thin film transistor (TFT)s connects the drain electrode of described 73rd thin film transistor (TFT)；
The drain electrode of grid described 51st thin film transistor (TFT) of connection of described 73rd thin film transistor (TFT), the described 7th
The source electrode of 13 thin film transistor (TFT)s connects described 3rd constant voltage high level source；
The drain electrode of grid described 11st thin film transistor (TFT) of connection of described 74th thin film transistor (TFT), the described 70th
The source electrode of four thin film transistor (TFT)s connects described second constant voltage low level source, and the drain electrode of described 74th thin film transistor (TFT) connects institute
State the source electrode of the 54th thin film transistor (TFT)；
The drain electrode of grid described 11st thin film transistor (TFT) of connection of described 81st thin film transistor (TFT), the described 80th
The source electrode of one thin film transistor (TFT) connects described 3rd constant voltage high level source；
The grid of grid described 32nd thin film transistor (TFT) of connection of described 82nd thin film transistor (TFT), the described 8th
The source electrode of 12 thin film transistor (TFT)s connects described second constant voltage low level source, and the drain electrode of described 82nd thin film transistor (TFT) connects
The drain electrode of described 81st thin film transistor (TFT).
In the GOA circuit of the present invention, described first constant voltage low level source and the level in described second constant voltage low level source
Value is for-5～-8V.
In the GOA circuit of the present invention, described first constant voltage high level source, described second constant voltage high level source and described
The level value in three constant voltage high level sources is 20～30V.
In the GOA circuit of the present invention, one end of described bootstrap capacitor connects the outfan of described pull-up control module, separately
One end connects the scanning signal of described level.
According to the above-mentioned purpose of the present invention, a kind of display panels is proposed, including above GOA circuit.
The invention have the benefit that compared to existing GOA circuit and display panels, the GOA circuit of the present invention
And display panels is by being provided with voltage compensation submodule in drop-down control module, can suppress because of film crystal pipe range
Time service so that its threshold voltage moves toward negative value, and then will not make to scan signal output abnormality, impact display；Solve
Existing GOA circuit and display panels cause scanning signal charging because the threshold voltage of thin film transistor (TFT) moves toward negative value
Deficiency, in turn results in scanning signal output abnormality, the technical problem of impact display.
Accompanying drawing explanation
In order to be illustrated more clearly that embodiment or technical scheme of the prior art, below will be to embodiment or prior art
In description, the required accompanying drawing used is briefly described, it should be apparent that, the accompanying drawing in describing below is only some of invention
Embodiment, for those of ordinary skill in the art, on the premise of not paying creative work, it is also possible to attached according to these
Figure obtains other accompanying drawing.
Fig. 1 is the structural representation of a kind of existing GOA circuit；
Fig. 2 is the structural representation of the preferred embodiment of the GOA circuit of the present invention；
Fig. 3 is the signal waveforms of the preferred embodiment of the GOA circuit of the present invention.
Detailed description of the invention
The explanation of following embodiment is with reference to additional diagram, the particular implementation implemented in order to illustrate the present invention may be used to
Example.The direction term that the present invention is previously mentioned, such as [on], [under], [front], [afterwards], [left], [right], [interior], [outward], [side]
Deng, it is only the direction with reference to annexed drawings.Therefore, the direction term of use is to illustrate and understand the present invention, and is not used to
Limit the present invention.In the drawings, the unit that structure is similar is to represent in order to identical label.
The present invention is directed to existing GOA circuit, when thin film transistor (TFT) works long hours, its threshold voltage can move toward negative value
Dynamic, cause scanning signal undercharge, cause and scan signal output abnormality, and then affect the display effect of display panels
Technical problem, the present embodiment can solve the problem that this defect.
See Fig. 2, for the preferred embodiment structural representation of the GOA circuit of the present invention；
The GOA circuit of this preferred embodiment includes pulling up control module 201, pull-up module 202, drop-down module 204, passing down
Module 203, drop-down maintenance module 205, bootstrap capacitor Cbt, the first constant voltage low level source Vss and the second constant voltage low level source DCL；
Described pull-up control module 201, for receiving scanning signal G (N-1) of upper level, generates scanning level signal；Pull-up module
202, for drawing high scanning signal G (N) of described level according to described scanning level signal；Drop-down module 204, under basis
Scanning signal G (N+1) of one-level drags down the scanning level signal of described level；Lower transmission module 203, for according to described level
Scanning signal G (N) and clock signal CK of this grade, generate the level number of delivering a letter ST (N) of this grade；Drop-down maintenance module 205, is used for
Maintain the low level of scanning signal G (N) of described level；Bootstrap capacitor Cbt be arranged at pull-up control module 201 outfan with
And between the outfan of scanning signal G (N) of described level, for generating the high level of scanning signal G (N) of described level；
First constant voltage low level source Vss, for providing the first constant voltage low level；Second constant voltage low level source DCL, for providing the second perseverance
Force down level；
Wherein, described pull-up control module 201 respectively with described pull-up module 202, described drop-down module 204, described under
Transmission module 203, described drop-down maintenance module 205 and described bootstrap capacitor Cbt are electrically connected with；Described drop-down module 204 and institute
State pull-up module 202 to be electrically connected with；Described drop-down module 204 is electrically connected with described second constant voltage low level source DCL；Under described
Maintenance module 205 is drawn to be electrically connected with described first constant voltage low level source Vss, described second constant voltage low level source DCL respectively.
In the GOA circuit of the present invention, described drop-down module 204 includes the 41st thin film transistor (TFT) T41 and connects institute
Stating the voltage compensation submodule 206 of the 41st thin film transistor (TFT) T41, described voltage compensation submodule 206 includes the first film
Transistor T1, the 40th thin film transistor (TFT) T40 and the first constant voltage high level source VGH；
The grid of described the first film transistor T1 connects the outfan of the level number of delivering a letter ST (N) of this grade, described first thin
The source electrode of film transistor T1 connects the drain electrode of described first constant voltage high level source VGH, described the first film transistor T1 and connects institute
State the drain electrode of the 40th thin film transistor (TFT) T40；
The grid of described 40th thin film transistor (TFT) T40 and source electrode are all connected with the outfan of described pull-up control module 201；
Scanning signal G (N+1) of the grid connection next stage of described 41st thin film transistor (TFT) T41, the described 40th
The source electrode of one thin film transistor (TFT) T41 connects described second constant voltage low level source DCL, described 41st thin film transistor (TFT) T41's
Drain electrode connects the drain electrode of described 40th thin film transistor (TFT) T40.
Described pull-up control module 201 includes the 11st thin film transistor (TFT) T11 and the second constant voltage high level source DCH1；
The grid described second constant voltage high level source DCH1 of connection of described 11st thin film transistor (TFT) T11, the described 11st
The source electrode of thin film transistor (TFT) T11 connects scanning signal G (N-1) of described upper level, the leakage of described 11st thin film transistor (TFT) T11
Pole connects the outfan of described pull-up control module 201.
Described pull-up module 202 includes the 21st thin film transistor (TFT) T21, described 21st thin film transistor (TFT)
The grid of T21 connects the outfan of described pull-up control module 201, and the source electrode of described 21st thin film transistor (TFT) T21 connects
Clock signal CK of described level, the drain electrode of described 21st thin film transistor (TFT) T21 connects the scanning signal G of described level
(N)。
Described lower transmission module 203 includes the 22nd thin film transistor (TFT) T22, described 22nd thin film transistor (TFT)
The grid of T22 connects the outfan of described pull-up control module 201, and the source electrode of described 22nd thin film transistor (TFT) T22 connects
Clock signal CK of described level, the drain electrode of described 22nd thin film transistor (TFT) T22 connects the level number of the delivering a letter ST of described level
(N)。
Described drop-down maintenance module 205 include the 32nd thin film transistor (TFT) T32, the 42nd thin film transistor (TFT) T42,
51 thin film transistor (TFT) T51, the 52nd thin film transistor (TFT) T52, the 53rd thin film transistor (TFT) T53, the 54th thin film
Transistor T54, the 73rd thin film transistor (TFT) T73, the 74th thin film transistor (TFT) T74, the 81st thin film transistor (TFT) T81,
82nd thin film transistor (TFT) T82 and the 3rd constant voltage high level source DCH2；
The grid of described 32nd thin film transistor (TFT) T32 connects the drain electrode of described 53rd thin film transistor (TFT) T53, institute
The source electrode stating the 32nd thin film transistor (TFT) T32 connects described first constant voltage low level source Vss, described 32nd film crystal
The drain electrode of pipe T32 connects scanning signal G (N) of described level；
The grid of described 42nd thin film transistor (TFT) T42 connects the drain electrode of described 53rd thin film transistor (TFT) T53, institute
The drain electrode stating the 42nd thin film transistor (TFT) T42 connects the outfan of described pull-up control module 201, described 42nd thin film
The source electrode of transistor T42 connects the drain electrode of described 81st thin film transistor (TFT) T81；
The grid of described 51st thin film transistor (TFT) T51 is connected described 3rd constant voltage high level source DCH2, institute with source electrode
The drain electrode stating the 51st thin film transistor (TFT) T51 connects the source electrode of described 52nd thin film transistor (TFT) T52；
The grid of described 52nd thin film transistor (TFT) T52 connects the drain electrode of described 11st thin film transistor (TFT) T11, described
The source electrode of the 52nd thin film transistor (TFT) T52 connects described first constant voltage low level source Vss；
The grid of described 53rd thin film transistor (TFT) T53 connects the drain electrode of described 51st thin film transistor (TFT) T51, institute
The source electrode stating the 53rd thin film transistor (TFT) T53 connects described 3rd constant voltage high level source DCH2, and described 53rd thin film is brilliant
The drain electrode of body pipe T53 connects the drain electrode of described 54th thin film transistor (TFT) T54；
The grid of described 54th thin film transistor (TFT) T54 connects the drain electrode of described 11st thin film transistor (TFT) T11, described
The source electrode of the 54th thin film transistor (TFT) T54 connects the drain electrode of described 73rd thin film transistor (TFT) T73；
The grid of described 73rd thin film transistor (TFT) T73 connects the drain electrode of described 51st thin film transistor (TFT) T51, institute
The source electrode stating the 73rd thin film transistor (TFT) T73 connects described 3rd constant voltage high level source DCH2；
The grid of described 74th thin film transistor (TFT) T74 connects the drain electrode of described 11st thin film transistor (TFT) T11, described
The source electrode of the 74th thin film transistor (TFT) T74 connects described second constant voltage low level source DCL, described 74th thin film transistor (TFT)
The drain electrode of T74 connects the source electrode of described 54th thin film transistor (TFT) T54；
The grid of described 81st thin film transistor (TFT) T81 connects the drain electrode of described 11st thin film transistor (TFT) T11, described
The source electrode of the 81st thin film transistor (TFT) T81 connects described 3rd constant voltage high level source DCH2；
The grid of described 82nd thin film transistor (TFT) T82 connects the grid of described 32nd thin film transistor (TFT) T32, institute
The source electrode stating the 82nd thin film transistor (TFT) T82 connects described second constant voltage low level source DCL, described 82nd film crystal
The drain electrode of pipe T82 connects the drain electrode of described 81st thin film transistor (TFT) T81.
The level value of described first constant voltage low level source Vss and described second constant voltage low level source DCL is-5～-8V.
Described first constant voltage high level source VGH, described second constant voltage high level source DCH1 and described 3rd constant voltage high level
The level value of source DCH2 is 20～30V.
One end of described bootstrap capacitor Cbt connects the outfan of described pull-up control module 201, and the other end connects described
Scanning signal G (N) of level.
See Fig. 3, for the signal waveforms of preferred embodiment of the GOA circuit of the present invention；
See Fig. 2 and Fig. 3, the GOA circuit of this preferred embodiment in use, when scanning signal G (N-1) of upper level is
During high level, the 11st thin film transistor (TFT) T11 conducting, the second constant voltage high level source DCH1 passes through the 11st thin film transistor (TFT) T11
Charge to bootstrap capacitor Cbt so that the first reference point Q (N) rises to a higher level.
Scanning signal G (N-1) of upper level subsequently transfers low level to, and the 11st thin film transistor (TFT) T11 closes, the first reference
Point Q (N) maintains a higher level by bootstrap capacitor Cbt.Meanwhile, clock signal CK of this grade transfers high level to, the first ginseng
The constant voltage high level that examination point Q (N) exports sequentially passes through the 22nd thin film transistor (TFT) T22 and the 21st thin film transistor (TFT) T21
Grid, the 22nd thin film transistor (TFT) T22 and the 21st thin film transistor (TFT) T21 opens, and clock signal CK of this grade is passed through
21st thin film transistor (TFT) T21 continues to charge to bootstrap capacitor Cbt so that the first reference point Q (N) reaches a higher electricity
Flat, scanning signal G (N) of this grade and the level number of delivering a letter ST (N) of this grade also transfer high level to.
When scanning signal G (N) of this grade is high level, and the level number of delivering a letter ST (N) of this grade is high level, the scanning of next stage
When signal G (N+1) is low level, the first film transistor T1 turns on, the constant voltage high level that the first constant voltage high level source VGH produces
Reaching the second reference point P (N), constant voltage high level reaches the output of pull-up control module 201 through the 40th thin film transistor (TFT) T40
End, owing to scanning signal G (N+1) of next stage is closed, so the high level of the first reference point Q (N) will not be pulled down into.
The grid of the 73rd thin film transistor (TFT) T73 connects the drain electrode of the 51st thin film transistor (TFT) T51, and the 3rd constant voltage is high
Level source DCH2 exports constant voltage high level, and the 51st thin film transistor (TFT) T51 opens, and constant voltage high level is brilliant through the 51st thin film
Body pipe T51 reaches the 73rd thin film transistor (TFT) T73, and the 73rd thin film transistor (TFT) T73 opens, and is reached down by constant voltage high level
One-level.
Second constant voltage high level source DCH2 opens, and the 11st thin film transistor (TFT) T11 opens, the second constant voltage high level source DCH2
The constant voltage high level produced reaches the 74th thin film transistor (TFT) T74 through the 11st thin film transistor (TFT) T11, and the 74th thin film is brilliant
Body pipe T74 opens, and is flated pass by constant voltage height to the 81st thin film transistor (TFT) T81, the 81st thin film transistor (TFT) T81 and opens, incites somebody to action
Constant voltage high level reaches next stage.
The first constant voltage low level that first constant voltage low level source Vss produces reaches the 32nd thin film transistor (TFT) T32, this level
Scanning signal G (N) transfer low level to.
When scanning signal G (N) of this grade begins to shut off, the level number of delivering a letter ST (N) of this grade is low level, and the first film is brilliant
Body pipe T1 closes, and the first constant voltage high level source VGH will not be to the second reference point P (N) input high level；Meanwhile, the sweeping of next stage
Retouching signal G (N+1) to open, for high level, the 41st thin film transistor (TFT) T41 opens, and the first reference point Q (N) pulled down to
The low level of two constant voltage low level source DCL, scanning signal G (N) of this grade pulled down to low level, so, the waveform one of output
It is directly normal.
Owing to the first reference point Q (N) transfers low level to so that the 52nd thin film transistor (TFT) T52 and the 54th thin film
Transistor T54 closes, and meanwhile, the constant voltage high level that the 3rd constant voltage high level source DCH2 produces makes the 51st thin film transistor (TFT)
T51 and the 53rd thin film transistor (TFT) T53 opens, and the constant voltage high level that the 3rd constant voltage high level source DCH2 produces reaches the 3rd ginseng
Examination point K (N) so that the 42nd thin film transistor (TFT) T42 opens, the second low electricity of constant voltage that the second constant voltage low level source DCL produces
Flat, reach the grid of the 42nd thin film transistor (TFT) T42 through the 82nd thin film transistor (TFT) T82, maintain the first reference point Q
(N) low level.
The GOA circuit of the present invention, by adding voltage compensation module, to ensure the first reference in drop-down module 204
Scanning signal G (N) the power supply abundance of some Q (N) and this grade, thus improve the reliability of GOA circuit.
The present invention also provides for a kind of display panels, and the display panels of this preferred embodiment includes such as Fig. 2 and 3 institute
GOA circuit in the previous embodiment shown, does not repeats them here.
The display panels of the present invention, by adding voltage compensation submodule 206, to protect in drop-down module 204
Demonstrate,prove scanning signal G (N) the power supply abundance of the first reference point Q (N) and this grade, thus improve the reliability of GOA circuit, carry further
Rise the display effect of display panels.
In sum, although the present invention is disclosed above with preferred embodiment, but above preferred embodiment and be not used to limit
The present invention processed, those of ordinary skill in the art, without departing from the spirit and scope of the present invention, all can make various change and profit
Decorations, therefore protection scope of the present invention defines in the range of standard with claim.
Claims (10)
1. a GOA circuit, it is characterised in that including:
Pull-up control module, generates the scanning level signal of this grade for receiving the scanning signal of upper level；
Pull-up module, for drawing high sweeping of described level according to the scanning level signal of described level and the clock signal of this grade
Retouch signal；
Drop-down module, drags down the scanning level signal of described level for the scanning signal according to next stage；
Lower transmission module, delivers a letter for generating the level of this grade according to the scanning level signal of described level and the clock signal of this grade
Number；
Drop-down maintenance module, for maintaining the low level of the scanning level signal of described level；
Bootstrap capacitor, for generating the high level of the scanning signal of described level；And
First constant voltage low level source, for providing the first constant voltage low level；
Second constant voltage low level source, for providing the second constant voltage low level；
Wherein said pull-up control module respectively with described pull-up module, described drop-down module, described lower transmission module, described drop-down
Module and described bootstrap capacitor is maintained to be electrically connected with；Described drop-down module is electrically connected with described pull-up module；Described drop-down
Module is electrically connected with described second constant voltage low level source；Described drop-down maintenance module respectively with described first constant voltage low level
Source, described second constant voltage low level source are electrically connected with.
GOA circuit the most according to claim 1, it is characterised in that described drop-down module includes the 41st film crystal
Managing and connect the voltage compensation submodule of described 41st thin film transistor (TFT), described voltage compensation submodule includes the first film
Transistor, the 40th thin film transistor (TFT) and the first constant voltage high level source；
The grid of described the first film transistor connects the outfan of the level number of delivering a letter of this grade, the source of described the first film transistor
Pole connects described first constant voltage high level source, and the drain electrode of described the first film transistor connects described 40th thin film transistor (TFT)
Drain electrode；
The grid of described 40th thin film transistor (TFT) and source electrode are all connected with the outfan of described pull-up control module；
The grid of described 41st thin film transistor (TFT) connects the scanning signal of next stage, described 41st thin film transistor (TFT)
Source electrode connects described second constant voltage low level source, and it is brilliant that the drain electrode of described 41st thin film transistor (TFT) connects described 40th thin film
The drain electrode of body pipe.
GOA circuit the most according to claim 1, it is characterised in that described pull-up control module includes that the 11st thin film is brilliant
Body pipe and the second constant voltage high level source；
The grid of described 11st thin film transistor (TFT) connects described second constant voltage high level source, described 11st thin film transistor (TFT)
Source electrode connects the scanning signal of described upper level, and the drain electrode of described 11st thin film transistor (TFT) connects described pull-up control module
Outfan.
GOA circuit the most according to claim 1, it is characterised in that described pull-up module includes the 21st thin film
Transistor, the outfan of the grid described pull-up control module of connection of described 21st thin film transistor (TFT), the described 21st
The source electrode of thin film transistor (TFT) connects the clock signal of described level, and the drain electrode of described 21st thin film transistor (TFT) connects described
The scanning signal of level.
GOA circuit the most according to claim 1, it is characterised in that described lower transmission module includes the 22nd thin film
Transistor, the outfan of the grid described pull-up control module of connection of described 22nd thin film transistor (TFT), the described 22nd
The source electrode of thin film transistor (TFT) connects the clock signal of described level, and the drain electrode of described 22nd thin film transistor (TFT) connects described
The level number of delivering a letter of level.
GOA circuit the most according to claim 3, it is characterised in that described drop-down maintenance module includes the 32nd thin film
Transistor, the 42nd thin film transistor (TFT), the 51st thin film transistor (TFT), the 52nd thin film transistor (TFT), the 53rd thin film
Transistor, the 54th thin film transistor (TFT), the 73rd thin film transistor (TFT), the 74th thin film transistor (TFT), the 81st thin film
Transistor, the 82nd thin film transistor (TFT) and the 3rd constant voltage high level source；
The drain electrode of grid described 53rd thin film transistor (TFT) of connection of described 32nd thin film transistor (TFT), the described 32nd
The source electrode of thin film transistor (TFT) connects described first constant voltage low level source, and the drain electrode of described 32nd thin film transistor (TFT) connects described
The scanning signal of this grade；
The drain electrode of grid described 53rd thin film transistor (TFT) of connection of described 42nd thin film transistor (TFT), the described 42nd
The drain electrode of thin film transistor (TFT) connects the outfan of described pull-up control module, and the source electrode of described 42nd thin film transistor (TFT) connects
The drain electrode of described 81st thin film transistor (TFT)；
The grid of described 51st thin film transistor (TFT) is connected described 3rd constant voltage high level source with source electrode, described 51st thin
The drain electrode of film transistor connects the source electrode of described 52nd thin film transistor (TFT)；
The grid of described 52nd thin film transistor (TFT) connects the drain electrode of described 11st thin film transistor (TFT), described 52nd thin
The source electrode of film transistor connects described first constant voltage low level source；
The drain electrode of grid described 51st thin film transistor (TFT) of connection of described 53rd thin film transistor (TFT), the described 53rd
The source electrode of thin film transistor (TFT) connects described 3rd constant voltage high level source, and the drain electrode of described 53rd thin film transistor (TFT) connects described
The drain electrode of the 54th thin film transistor (TFT)；
The grid of described 54th thin film transistor (TFT) connects the drain electrode of described 11st thin film transistor (TFT), described 54th thin
The source electrode of film transistor connects the drain electrode of described 73rd thin film transistor (TFT)；
The drain electrode of grid described 51st thin film transistor (TFT) of connection of described 73rd thin film transistor (TFT), the described 73rd
The source electrode of thin film transistor (TFT) connects described 3rd constant voltage high level source；
The grid of described 74th thin film transistor (TFT) connects the drain electrode of described 11st thin film transistor (TFT), described 74th thin
The source electrode of film transistor connects described second constant voltage low level source, and the drain electrode of described 74th thin film transistor (TFT) connects described the
The source electrode of 54 thin film transistor (TFT)s；
The grid of described 81st thin film transistor (TFT) connects the drain electrode of described 11st thin film transistor (TFT), described 81st thin
The source electrode of film transistor connects described 3rd constant voltage high level source；
The grid of grid described 32nd thin film transistor (TFT) of connection of described 82nd thin film transistor (TFT), the described 82nd
The source electrode of thin film transistor (TFT) connects described second constant voltage low level source, and the drain electrode of described 82nd thin film transistor (TFT) connects described
The drain electrode of the 81st thin film transistor (TFT).
GOA circuit the most according to claim 1, it is characterised in that described first constant voltage low level source is permanent with described second
The level value forcing down level source is-5～-8V.
GOA circuit the most according to claim 1, it is characterised in that described first constant voltage high level source, described second constant voltage
The level value in high level source and described 3rd constant voltage high level source is 20～30V.
GOA circuit the most according to claim 1, it is characterised in that one end of described bootstrap capacitor connects described pull-up control
The outfan of molding block, the other end connects the scanning signal of described level.
10. a display panels, it is characterised in that include the arbitrary described GOA circuit of claim 1-9.
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